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authorKen Wang <Qingqing.Wang@amd.com>2015-06-03 05:36:54 -0400
committerAlex Deucher <alexander.deucher@amd.com>2015-06-03 21:04:01 -0400
commit32bf7106e072b59cade754062ed86023309f50d9 (patch)
tree31ef93eb35ed310e9a9970a4d16a9f62597fd195
parent35074d2d404049c386e7e70a9e48cf77f1379364 (diff)
drm/amdgpu add max_memory_clock for interface query (v2)
Add a query for the max memory clock. v2: handle the dpm enabled case properly Signed-off-by: Ken Wang <Qingqing.Wang@amd.com> Reviewd-by: Jammy Zhou <Jammy.Zhou@amd.com>
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c8
-rw-r--r--include/uapi/drm/amdgpu_drm.h1
2 files changed, 7 insertions, 2 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index b6dd3751d9a5..3c182b6c5a27 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -414,11 +414,15 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file
414 dev_info.num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se; 414 dev_info.num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se;
415 /* return all clocks in KHz */ 415 /* return all clocks in KHz */
416 dev_info.gpu_counter_freq = amdgpu_asic_get_xclk(adev) * 10; 416 dev_info.gpu_counter_freq = amdgpu_asic_get_xclk(adev) * 10;
417 if (adev->pm.dpm_enabled) 417 if (adev->pm.dpm_enabled) {
418 dev_info.max_engine_clock = 418 dev_info.max_engine_clock =
419 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk * 10; 419 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk * 10;
420 else 420 dev_info.max_memory_clock =
421 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk * 10;
422 } else {
421 dev_info.max_engine_clock = adev->pm.default_sclk * 10; 423 dev_info.max_engine_clock = adev->pm.default_sclk * 10;
424 dev_info.max_memory_clock = adev->pm.default_mclk * 10;
425 }
422 dev_info.enabled_rb_pipes_mask = adev->gfx.config.backend_enable_mask; 426 dev_info.enabled_rb_pipes_mask = adev->gfx.config.backend_enable_mask;
423 dev_info.num_rb_pipes = adev->gfx.config.max_backends_per_se * 427 dev_info.num_rb_pipes = adev->gfx.config.max_backends_per_se *
424 adev->gfx.config.max_shader_engines; 428 adev->gfx.config.max_shader_engines;
diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h
index cd54891b1d5c..420c762f2ed7 100644
--- a/include/uapi/drm/amdgpu_drm.h
+++ b/include/uapi/drm/amdgpu_drm.h
@@ -553,6 +553,7 @@ struct drm_amdgpu_info_device {
553 uint32_t num_shader_arrays_per_engine; 553 uint32_t num_shader_arrays_per_engine;
554 uint32_t gpu_counter_freq; /* in KHz */ 554 uint32_t gpu_counter_freq; /* in KHz */
555 uint64_t max_engine_clock; /* in KHz */ 555 uint64_t max_engine_clock; /* in KHz */
556 uint64_t max_memory_clock; /* in KHz */
556 /* cu information */ 557 /* cu information */
557 uint32_t cu_active_number; 558 uint32_t cu_active_number;
558 uint32_t cu_ao_mask; 559 uint32_t cu_ao_mask;