aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorPeter Ujfalusi <peter.ujfalusi@ti.com>2015-10-14 07:42:57 -0400
committerVinod Koul <vinod.koul@intel.com>2015-10-14 10:27:12 -0400
commit3287fb4d23fc906edcd5fa8c1632f30946e9c779 (patch)
tree86c0dcbbced7a8e430cb9a0348ed580bc6026471
parent907f74a0b46890da59c4f2caf7e17a89695e8132 (diff)
dmaengine: edma: Use dev_dbg instead pr_debug
We have access to dev, so it is better to use the dev_dbg for debug prints. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
-rw-r--r--drivers/dma/edma.c24
1 files changed, 12 insertions, 12 deletions
diff --git a/drivers/dma/edma.c b/drivers/dma/edma.c
index a9fe5c92451d..08f9bd0aa0b3 100644
--- a/drivers/dma/edma.c
+++ b/drivers/dma/edma.c
@@ -676,23 +676,23 @@ static int edma_start(struct edma_cc *ecc, unsigned channel)
676 676
677 /* EDMA channels without event association */ 677 /* EDMA channels without event association */
678 if (test_bit(channel, ecc->edma_unused)) { 678 if (test_bit(channel, ecc->edma_unused)) {
679 pr_debug("EDMA: ESR%d %08x\n", j, 679 dev_dbg(ecc->dev, "ESR%d %08x\n", j,
680 edma_shadow0_read_array(ecc, SH_ESR, j)); 680 edma_shadow0_read_array(ecc, SH_ESR, j));
681 edma_shadow0_write_array(ecc, SH_ESR, j, mask); 681 edma_shadow0_write_array(ecc, SH_ESR, j, mask);
682 return 0; 682 return 0;
683 } 683 }
684 684
685 /* EDMA channel with event association */ 685 /* EDMA channel with event association */
686 pr_debug("EDMA: ER%d %08x\n", j, 686 dev_dbg(ecc->dev, "ER%d %08x\n", j,
687 edma_shadow0_read_array(ecc, SH_ER, j)); 687 edma_shadow0_read_array(ecc, SH_ER, j));
688 /* Clear any pending event or error */ 688 /* Clear any pending event or error */
689 edma_write_array(ecc, EDMA_ECR, j, mask); 689 edma_write_array(ecc, EDMA_ECR, j, mask);
690 edma_write_array(ecc, EDMA_EMCR, j, mask); 690 edma_write_array(ecc, EDMA_EMCR, j, mask);
691 /* Clear any SER */ 691 /* Clear any SER */
692 edma_shadow0_write_array(ecc, SH_SECR, j, mask); 692 edma_shadow0_write_array(ecc, SH_SECR, j, mask);
693 edma_shadow0_write_array(ecc, SH_EESR, j, mask); 693 edma_shadow0_write_array(ecc, SH_EESR, j, mask);
694 pr_debug("EDMA: EER%d %08x\n", j, 694 dev_dbg(ecc->dev, "EER%d %08x\n", j,
695 edma_shadow0_read_array(ecc, SH_EER, j)); 695 edma_shadow0_read_array(ecc, SH_EER, j));
696 return 0; 696 return 0;
697 } 697 }
698 698
@@ -730,8 +730,8 @@ static void edma_stop(struct edma_cc *ecc, unsigned channel)
730 /* clear possibly pending completion interrupt */ 730 /* clear possibly pending completion interrupt */
731 edma_shadow0_write_array(ecc, SH_ICR, j, mask); 731 edma_shadow0_write_array(ecc, SH_ICR, j, mask);
732 732
733 pr_debug("EDMA: EER%d %08x\n", j, 733 dev_dbg(ecc->dev, "EER%d %08x\n", j,
734 edma_shadow0_read_array(ecc, SH_EER, j)); 734 edma_shadow0_read_array(ecc, SH_EER, j));
735 735
736 /* REVISIT: consider guarding against inappropriate event 736 /* REVISIT: consider guarding against inappropriate event
737 * chaining by overwriting with dummy_paramset. 737 * chaining by overwriting with dummy_paramset.
@@ -800,8 +800,8 @@ static int edma_trigger_channel(struct edma_cc *ecc, unsigned channel)
800 800
801 edma_shadow0_write_array(ecc, SH_ESR, (channel >> 5), mask); 801 edma_shadow0_write_array(ecc, SH_ESR, (channel >> 5), mask);
802 802
803 pr_debug("EDMA: ESR%d %08x\n", (channel >> 5), 803 dev_dbg(ecc->dev, "ESR%d %08x\n", (channel >> 5),
804 edma_shadow0_read_array(ecc, SH_ESR, (channel >> 5))); 804 edma_shadow0_read_array(ecc, SH_ESR, (channel >> 5)));
805 return 0; 805 return 0;
806} 806}
807 807
@@ -831,8 +831,8 @@ static void edma_clean_channel(struct edma_cc *ecc, unsigned channel)
831 int j = (channel >> 5); 831 int j = (channel >> 5);
832 unsigned int mask = BIT(channel & 0x1f); 832 unsigned int mask = BIT(channel & 0x1f);
833 833
834 pr_debug("EDMA: EMR%d %08x\n", j, 834 dev_dbg(ecc->dev, "EMR%d %08x\n", j,
835 edma_read_array(ecc, EDMA_EMR, j)); 835 edma_read_array(ecc, EDMA_EMR, j));
836 edma_shadow0_write_array(ecc, SH_ECR, j, mask); 836 edma_shadow0_write_array(ecc, SH_ECR, j, mask);
837 /* Clear the corresponding EMR bits */ 837 /* Clear the corresponding EMR bits */
838 edma_write_array(ecc, EDMA_EMCR, j, mask); 838 edma_write_array(ecc, EDMA_EMCR, j, mask);