diff options
author | Lukasz Majewski <lukma@denx.de> | 2017-01-29 16:54:15 -0500 |
---|---|---|
committer | Thierry Reding <thierry.reding@gmail.com> | 2017-01-30 03:13:07 -0500 |
commit | 326ed314fefebb259563926c8c6110a009562e07 (patch) | |
tree | 6632352a509854ee4dc52f8edadaaa8ad4dcf1d4 | |
parent | c322f457755aea8eea91c79c473e17ffa7f12cfc (diff) |
pwm: imx: Add polarity inversion support to i.MX's PWMv2
With this patch the polarity settings for i.MX's PWMv2 is now supported
on top of atomic PWM setting
Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com>
Signed-off-by: Lukasz Majewski <l.majewski@majess.pl>
Reviewed-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
-rw-r--r-- | drivers/pwm/pwm-imx.c | 24 |
1 files changed, 19 insertions, 5 deletions
diff --git a/drivers/pwm/pwm-imx.c b/drivers/pwm/pwm-imx.c index 0a81c028cb11..957099e82ed3 100644 --- a/drivers/pwm/pwm-imx.c +++ b/drivers/pwm/pwm-imx.c | |||
@@ -38,6 +38,7 @@ | |||
38 | #define MX3_PWMCR_DOZEEN (1 << 24) | 38 | #define MX3_PWMCR_DOZEEN (1 << 24) |
39 | #define MX3_PWMCR_WAITEN (1 << 23) | 39 | #define MX3_PWMCR_WAITEN (1 << 23) |
40 | #define MX3_PWMCR_DBGEN (1 << 22) | 40 | #define MX3_PWMCR_DBGEN (1 << 22) |
41 | #define MX3_PWMCR_POUTC (1 << 18) | ||
41 | #define MX3_PWMCR_CLKSRC_IPG_HIGH (2 << 16) | 42 | #define MX3_PWMCR_CLKSRC_IPG_HIGH (2 << 16) |
42 | #define MX3_PWMCR_CLKSRC_IPG (1 << 16) | 43 | #define MX3_PWMCR_CLKSRC_IPG (1 << 16) |
43 | #define MX3_PWMCR_SWR (1 << 3) | 44 | #define MX3_PWMCR_SWR (1 << 3) |
@@ -163,6 +164,7 @@ static int imx_pwm_apply_v2(struct pwm_chip *chip, struct pwm_device *pwm, | |||
163 | struct pwm_state cstate; | 164 | struct pwm_state cstate; |
164 | unsigned long long c; | 165 | unsigned long long c; |
165 | int ret; | 166 | int ret; |
167 | u32 cr; | ||
166 | 168 | ||
167 | pwm_get_state(pwm, &cstate); | 169 | pwm_get_state(pwm, &cstate); |
168 | 170 | ||
@@ -207,11 +209,15 @@ static int imx_pwm_apply_v2(struct pwm_chip *chip, struct pwm_device *pwm, | |||
207 | writel(duty_cycles, imx->mmio_base + MX3_PWMSAR); | 209 | writel(duty_cycles, imx->mmio_base + MX3_PWMSAR); |
208 | writel(period_cycles, imx->mmio_base + MX3_PWMPR); | 210 | writel(period_cycles, imx->mmio_base + MX3_PWMPR); |
209 | 211 | ||
210 | writel(MX3_PWMCR_PRESCALER(prescale) | | 212 | cr = MX3_PWMCR_PRESCALER(prescale) | |
211 | MX3_PWMCR_DOZEEN | MX3_PWMCR_WAITEN | | 213 | MX3_PWMCR_DOZEEN | MX3_PWMCR_WAITEN | |
212 | MX3_PWMCR_DBGEN | MX3_PWMCR_CLKSRC_IPG_HIGH | | 214 | MX3_PWMCR_DBGEN | MX3_PWMCR_CLKSRC_IPG_HIGH | |
213 | MX3_PWMCR_EN, | 215 | MX3_PWMCR_EN; |
214 | imx->mmio_base + MX3_PWMCR); | 216 | |
217 | if (state->polarity == PWM_POLARITY_INVERSED) | ||
218 | cr |= MX3_PWMCR_POUTC; | ||
219 | |||
220 | writel(cr, imx->mmio_base + MX3_PWMCR); | ||
215 | } else if (cstate.enabled) { | 221 | } else if (cstate.enabled) { |
216 | writel(0, imx->mmio_base + MX3_PWMCR); | 222 | writel(0, imx->mmio_base + MX3_PWMCR); |
217 | 223 | ||
@@ -234,6 +240,7 @@ static const struct pwm_ops imx_pwm_ops_v2 = { | |||
234 | }; | 240 | }; |
235 | 241 | ||
236 | struct imx_pwm_data { | 242 | struct imx_pwm_data { |
243 | bool polarity_supported; | ||
237 | const struct pwm_ops *ops; | 244 | const struct pwm_ops *ops; |
238 | }; | 245 | }; |
239 | 246 | ||
@@ -242,6 +249,7 @@ static struct imx_pwm_data imx_pwm_data_v1 = { | |||
242 | }; | 249 | }; |
243 | 250 | ||
244 | static struct imx_pwm_data imx_pwm_data_v2 = { | 251 | static struct imx_pwm_data imx_pwm_data_v2 = { |
252 | .polarity_supported = true, | ||
245 | .ops = &imx_pwm_ops_v2, | 253 | .ops = &imx_pwm_ops_v2, |
246 | }; | 254 | }; |
247 | 255 | ||
@@ -283,6 +291,12 @@ static int imx_pwm_probe(struct platform_device *pdev) | |||
283 | imx->chip.npwm = 1; | 291 | imx->chip.npwm = 1; |
284 | imx->chip.can_sleep = true; | 292 | imx->chip.can_sleep = true; |
285 | 293 | ||
294 | if (data->polarity_supported) { | ||
295 | dev_dbg(&pdev->dev, "PWM supports output inversion\n"); | ||
296 | imx->chip.of_xlate = of_pwm_xlate_with_flags; | ||
297 | imx->chip.of_pwm_n_cells = 3; | ||
298 | } | ||
299 | |||
286 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); | 300 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
287 | imx->mmio_base = devm_ioremap_resource(&pdev->dev, r); | 301 | imx->mmio_base = devm_ioremap_resource(&pdev->dev, r); |
288 | if (IS_ERR(imx->mmio_base)) | 302 | if (IS_ERR(imx->mmio_base)) |