aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorNicolai Hähnle <nicolai.haehnle@amd.com>2016-06-17 13:31:34 -0400
committerAlex Deucher <alexander.deucher@amd.com>2016-07-07 14:54:45 -0400
commit324c614a819a37fbb643528a70139fe313c2ac24 (patch)
tree630a81e4f769261b96df9da514f74a2d687f70c4
parent6f8941a2308811626edc083c70584837d54e0382 (diff)
drm/amdgpu/gfx7: set USER_SHADER_ARRAY_CONFIG based on disable_cu parameter
v2: do not overwrite register when bitmap is zero Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Nicolai Hähnle <nicolai.haehnle@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-rw-r--r--drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c20
1 files changed, 20 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
index be344820b884..bbce38e7dd49 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
@@ -3868,6 +3868,20 @@ static void gfx_v7_0_enable_gfx_cgpg(struct amdgpu_device *adev,
3868 } 3868 }
3869} 3869}
3870 3870
3871static void gfx_v7_0_set_user_cu_inactive_bitmap(struct amdgpu_device *adev,
3872 u32 bitmap)
3873{
3874 u32 data;
3875
3876 if (!bitmap)
3877 return;
3878
3879 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT;
3880 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK;
3881
3882 WREG32(mmGC_USER_SHADER_ARRAY_CONFIG, data);
3883}
3884
3871static u32 gfx_v7_0_get_cu_active_bitmap(struct amdgpu_device *adev) 3885static u32 gfx_v7_0_get_cu_active_bitmap(struct amdgpu_device *adev)
3872{ 3886{
3873 u32 data, mask; 3887 u32 data, mask;
@@ -5033,9 +5047,12 @@ static void gfx_v7_0_get_cu_info(struct amdgpu_device *adev)
5033 int i, j, k, counter, active_cu_number = 0; 5047 int i, j, k, counter, active_cu_number = 0;
5034 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0; 5048 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
5035 struct amdgpu_cu_info *cu_info = &adev->gfx.cu_info; 5049 struct amdgpu_cu_info *cu_info = &adev->gfx.cu_info;
5050 unsigned disable_masks[4 * 2];
5036 5051
5037 memset(cu_info, 0, sizeof(*cu_info)); 5052 memset(cu_info, 0, sizeof(*cu_info));
5038 5053
5054 amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2);
5055
5039 mutex_lock(&adev->grbm_idx_mutex); 5056 mutex_lock(&adev->grbm_idx_mutex);
5040 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 5057 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
5041 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 5058 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
@@ -5043,6 +5060,9 @@ static void gfx_v7_0_get_cu_info(struct amdgpu_device *adev)
5043 ao_bitmap = 0; 5060 ao_bitmap = 0;
5044 counter = 0; 5061 counter = 0;
5045 gfx_v7_0_select_se_sh(adev, i, j); 5062 gfx_v7_0_select_se_sh(adev, i, j);
5063 if (i < 4 && j < 2)
5064 gfx_v7_0_set_user_cu_inactive_bitmap(
5065 adev, disable_masks[i * 2 + j]);
5046 bitmap = gfx_v7_0_get_cu_active_bitmap(adev); 5066 bitmap = gfx_v7_0_get_cu_active_bitmap(adev);
5047 cu_info->bitmap[i][j] = bitmap; 5067 cu_info->bitmap[i][j] = bitmap;
5048 5068