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authorKarl Beldan <kbeldan@baylibre.com>2016-08-16 18:33:37 -0400
committerSekhar Nori <nsekhar@ti.com>2016-08-18 05:25:12 -0400
commit31e3a8817b66034d49c988617f8ca2822275db7c (patch)
treec5bc9e146ae2bd3efc59b15df23d907f31414084
parent44524a010a55fc523e1d901613d5ee213cb79b97 (diff)
ARM: dts: da850,da850-evm: Add an aemif node and use it for the NAND
Currently the davinci da8xx boards use the mach-davinci aemif code. Instantiating an aemif node into the DT allows to use the ti-aemif memory driver and is another step to better DT support. This change adds an aemif node in the dtsi while retiring the nand_cs3 node. The NAND is now instantiated in the dts as a subnode of the aemif one along with its pins. Signed-off-by: Karl Beldan <kbeldan@baylibre.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com>
-rw-r--r--arch/arm/boot/dts/da850-evm.dts49
-rw-r--r--arch/arm/boot/dts/da850.dtsi35
2 files changed, 52 insertions, 32 deletions
diff --git a/arch/arm/boot/dts/da850-evm.dts b/arch/arm/boot/dts/da850-evm.dts
index 1a15db8e376b..eedcc592ba51 100644
--- a/arch/arm/boot/dts/da850-evm.dts
+++ b/arch/arm/boot/dts/da850-evm.dts
@@ -29,6 +29,20 @@
29 0x04 0x00011000 0x000ff000 29 0x04 0x00011000 0x000ff000
30 >; 30 >;
31 }; 31 };
32 nand_pins: nand_pins {
33 pinctrl-single,bits = <
34 /* EMA_WAIT[0], EMA_OE, EMA_WE, EMA_CS[4], EMA_CS[3] */
35 0x1c 0x10110110 0xf0ff0ff0
36 /*
37 * EMA_D[0], EMA_D[1], EMA_D[2],
38 * EMA_D[3], EMA_D[4], EMA_D[5],
39 * EMA_D[6], EMA_D[7]
40 */
41 0x24 0x11111111 0xffffffff
42 /* EMA_A[1], EMA_A[2] */
43 0x30 0x01100000 0x0ff00000
44 >;
45 };
32 }; 46 };
33 serial0: serial@42000 { 47 serial0: serial@42000 {
34 status = "okay"; 48 status = "okay";
@@ -131,11 +145,6 @@
131 status = "okay"; 145 status = "okay";
132 }; 146 };
133 }; 147 };
134 nand_cs3@62000000 {
135 status = "okay";
136 pinctrl-names = "default";
137 pinctrl-0 = <&nand_cs3_pins>;
138 };
139 vbat: fixedregulator@0 { 148 vbat: fixedregulator@0 {
140 compatible = "regulator-fixed"; 149 compatible = "regulator-fixed";
141 regulator-name = "vbat"; 150 regulator-name = "vbat";
@@ -250,3 +259,33 @@
250&edma1 { 259&edma1 {
251 ti,edma-reserved-slot-ranges = <32 90>; 260 ti,edma-reserved-slot-ranges = <32 90>;
252}; 261};
262
263&aemif {
264 pinctrl-names = "default";
265 pinctrl-0 = <&nand_pins>;
266 status = "ok";
267 cs3 {
268 #address-cells = <2>;
269 #size-cells = <1>;
270 clock-ranges;
271 ranges;
272
273 ti,cs-chipselect = <3>;
274
275 nand@2000000,0 {
276 compatible = "ti,davinci-nand";
277 #address-cells = <1>;
278 #size-cells = <1>;
279 reg = <0 0x02000000 0x02000000
280 1 0x00000000 0x00008000>;
281
282 ti,davinci-chipselect = <1>;
283 ti,davinci-mask-ale = <0>;
284 ti,davinci-mask-cle = <0>;
285 ti,davinci-mask-chipsel = <0>;
286 ti,davinci-ecc-mode = "hw";
287 ti,davinci-ecc-bits = <4>;
288 ti,davinci-nand-use-bbt;
289 };
290 };
291};
diff --git a/arch/arm/boot/dts/da850.dtsi b/arch/arm/boot/dts/da850.dtsi
index 5aac622c7959..f79e1b91c680 100644
--- a/arch/arm/boot/dts/da850.dtsi
+++ b/arch/arm/boot/dts/da850.dtsi
@@ -77,22 +77,6 @@
77 0x10 0x00220000 0x00ff0000 77 0x10 0x00220000 0x00ff0000
78 >; 78 >;
79 }; 79 };
80 nand_cs3_pins: pinmux_nand_pins {
81 pinctrl-single,bits = <
82 /* EMA_OE, EMA_WE */
83 0x1c 0x00110000 0x00ff0000
84 /* EMA_CS[4],EMA_CS[3]*/
85 0x1c 0x00000110 0x00000ff0
86 /*
87 * EMA_D[0], EMA_D[1], EMA_D[2],
88 * EMA_D[3], EMA_D[4], EMA_D[5],
89 * EMA_D[6], EMA_D[7]
90 */
91 0x24 0x11111111 0xffffffff
92 /* EMA_A[1], EMA_A[2] */
93 0x30 0x01100000 0x0ff00000
94 >;
95 };
96 i2c0_pins: pinmux_i2c0_pins { 80 i2c0_pins: pinmux_i2c0_pins {
97 pinctrl-single,bits = < 81 pinctrl-single,bits = <
98 /* I2C0_SDA,I2C0_SCL */ 82 /* I2C0_SDA,I2C0_SCL */
@@ -416,17 +400,14 @@
416 dma-names = "tx", "rx"; 400 dma-names = "tx", "rx";
417 }; 401 };
418 }; 402 };
419 nand_cs3@62000000 { 403 aemif: aemif@68000000 {
420 compatible = "ti,davinci-nand"; 404 compatible = "ti,da850-aemif";
421 reg = <0x62000000 0x807ff 405 #address-cells = <2>;
422 0x68000000 0x8000>; 406 #size-cells = <1>;
423 ti,davinci-chipselect = <1>; 407
424 ti,davinci-mask-ale = <0>; 408 reg = <0x68000000 0x00008000>;
425 ti,davinci-mask-cle = <0>; 409 ranges = <0 0 0x60000000 0x08000000
426 ti,davinci-mask-chipsel = <0>; 410 1 0 0x68000000 0x00008000>;
427 ti,davinci-ecc-mode = "hw";
428 ti,davinci-ecc-bits = <4>;
429 ti,davinci-nand-use-bbt;
430 status = "disabled"; 411 status = "disabled";
431 }; 412 };
432}; 413};