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authorBen Skeggs <bskeggs@redhat.com>2015-08-20 00:54:21 -0400
committerBen Skeggs <bskeggs@redhat.com>2015-08-27 22:40:45 -0400
commit31649ecf47a44e02e73bffc5680c8f56d6cf587a (patch)
treed59914684674c64bb608fc01b65d7a05f4080c5b
parent57113c0170b9efeacb3e3e9d4c2178c30d9cd991 (diff)
drm/nouveau/tmr: convert to new-style nvkm_subdev
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat
-rw-r--r--drivers/gpu/drm/nouveau/include/nvkm/subdev/timer.h54
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/device/base.c138
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/device/gf100.c9
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/device/gk104.c8
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c4
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/device/nv04.c2
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c8
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/device/nv20.c4
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/device/nv30.c5
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c16
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c14
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/device/user.c3
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c4
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk20a.c7
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/subdev/therm/base.c6
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/subdev/therm/fan.c12
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/subdev/therm/fantog.c2
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/subdev/therm/temp.c4
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/subdev/timer/Kbuild2
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/subdev/timer/base.c127
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/subdev/timer/gk20a.c45
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/subdev/timer/nv04.c227
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/subdev/timer/nv04.h25
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/subdev/timer/nv40.c88
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/subdev/timer/nv41.c85
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/subdev/timer/priv.h22
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/subdev/timer/regsnv04.h7
27 files changed, 501 insertions, 427 deletions
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/timer.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/timer.h
index f818adcc7467..62ed0880b0e1 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/timer.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/timer.h
@@ -9,15 +9,23 @@ struct nvkm_alarm {
9}; 9};
10 10
11static inline void 11static inline void
12nvkm_alarm_init(struct nvkm_alarm *alarm, 12nvkm_alarm_init(struct nvkm_alarm *alarm, void (*func)(struct nvkm_alarm *))
13 void (*func)(struct nvkm_alarm *))
14{ 13{
15 INIT_LIST_HEAD(&alarm->head); 14 INIT_LIST_HEAD(&alarm->head);
16 alarm->func = func; 15 alarm->func = func;
17} 16}
18 17
19void nvkm_timer_alarm(void *, u32 nsec, struct nvkm_alarm *); 18struct nvkm_timer {
20void nvkm_timer_alarm_cancel(void *, struct nvkm_alarm *); 19 const struct nvkm_timer_func *func;
20 struct nvkm_subdev subdev;
21
22 struct list_head alarms;
23 spinlock_t lock;
24};
25
26u64 nvkm_timer_read(struct nvkm_timer *);
27void nvkm_timer_alarm(struct nvkm_timer *, u32 nsec, struct nvkm_alarm *);
28void nvkm_timer_alarm_cancel(struct nvkm_timer *, struct nvkm_alarm *);
21 29
22/* Delay based on GPU time (ie. PTIMER). 30/* Delay based on GPU time (ie. PTIMER).
23 * 31 *
@@ -31,13 +39,13 @@ void nvkm_timer_alarm_cancel(void *, struct nvkm_alarm *);
31#define nvkm_nsec(d,n,cond...) ({ \ 39#define nvkm_nsec(d,n,cond...) ({ \
32 struct nvkm_device *_device = (d); \ 40 struct nvkm_device *_device = (d); \
33 struct nvkm_timer *_tmr = _device->timer; \ 41 struct nvkm_timer *_tmr = _device->timer; \
34 u64 _nsecs = (n), _time0 = _tmr->read(_tmr); \ 42 u64 _nsecs = (n), _time0 = nvkm_timer_read(_tmr); \
35 s64 _taken = 0; \ 43 s64 _taken = 0; \
36 bool _warn = true; \ 44 bool _warn = true; \
37 \ 45 \
38 do { \ 46 do { \
39 cond \ 47 cond \
40 } while (_taken = _tmr->read(_tmr) - _time0, _taken < _nsecs); \ 48 } while (_taken = nvkm_timer_read(_tmr) - _time0, _taken < _nsecs); \
41 \ 49 \
42 if (_taken >= _nsecs) { \ 50 if (_taken >= _nsecs) { \
43 if (_warn) { \ 51 if (_warn) { \
@@ -51,32 +59,8 @@ void nvkm_timer_alarm_cancel(void *, struct nvkm_alarm *);
51#define nvkm_usec(d,u,cond...) nvkm_nsec((d), (u) * 1000, ##cond) 59#define nvkm_usec(d,u,cond...) nvkm_nsec((d), (u) * 1000, ##cond)
52#define nvkm_msec(d,m,cond...) nvkm_usec((d), (m) * 1000, ##cond) 60#define nvkm_msec(d,m,cond...) nvkm_usec((d), (m) * 1000, ##cond)
53 61
54struct nvkm_timer { 62int nv04_timer_new(struct nvkm_device *, int, struct nvkm_timer **);
55 struct nvkm_subdev subdev; 63int nv40_timer_new(struct nvkm_device *, int, struct nvkm_timer **);
56 u64 (*read)(struct nvkm_timer *); 64int nv41_timer_new(struct nvkm_device *, int, struct nvkm_timer **);
57 void (*alarm)(struct nvkm_timer *, u64 time, struct nvkm_alarm *); 65int gk20a_timer_new(struct nvkm_device *, int, struct nvkm_timer **);
58 void (*alarm_cancel)(struct nvkm_timer *, struct nvkm_alarm *);
59};
60
61static inline struct nvkm_timer *
62nvkm_timer(void *obj)
63{
64 return (void *)nvkm_subdev(obj, NVDEV_SUBDEV_TIMER);
65}
66
67#define nvkm_timer_create(p,e,o,d) \
68 nvkm_subdev_create_((p), (e), (o), 0, "PTIMER", "timer", \
69 sizeof(**d), (void **)d)
70#define nvkm_timer_destroy(p) \
71 nvkm_subdev_destroy(&(p)->subdev)
72#define nvkm_timer_init(p) \
73 nvkm_subdev_init_old(&(p)->subdev)
74#define nvkm_timer_fini(p,s) \
75 nvkm_subdev_fini_old(&(p)->subdev, (s))
76
77int nvkm_timer_create_(struct nvkm_object *, struct nvkm_engine *,
78 struct nvkm_oclass *, int size, void **);
79
80extern struct nvkm_oclass nv04_timer_oclass;
81extern struct nvkm_oclass gk20a_timer_oclass;
82#endif 66#endif
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
index 3734d1fb7756..04895322d371 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
@@ -85,7 +85,7 @@ nv4_chipset = {
85 .imem = nv04_instmem_new, 85 .imem = nv04_instmem_new,
86 .mc = nv04_mc_new, 86 .mc = nv04_mc_new,
87 .mmu = nv04_mmu_new, 87 .mmu = nv04_mmu_new,
88// .timer = nv04_timer_new, 88 .timer = nv04_timer_new,
89// .disp = nv04_disp_new, 89// .disp = nv04_disp_new,
90// .dma = nv04_dma_new, 90// .dma = nv04_dma_new,
91// .fifo = nv04_fifo_new, 91// .fifo = nv04_fifo_new,
@@ -105,7 +105,7 @@ nv5_chipset = {
105 .imem = nv04_instmem_new, 105 .imem = nv04_instmem_new,
106 .mc = nv04_mc_new, 106 .mc = nv04_mc_new,
107 .mmu = nv04_mmu_new, 107 .mmu = nv04_mmu_new,
108// .timer = nv04_timer_new, 108 .timer = nv04_timer_new,
109// .disp = nv04_disp_new, 109// .disp = nv04_disp_new,
110// .dma = nv04_dma_new, 110// .dma = nv04_dma_new,
111// .fifo = nv04_fifo_new, 111// .fifo = nv04_fifo_new,
@@ -126,7 +126,7 @@ nv10_chipset = {
126 .imem = nv04_instmem_new, 126 .imem = nv04_instmem_new,
127 .mc = nv04_mc_new, 127 .mc = nv04_mc_new,
128 .mmu = nv04_mmu_new, 128 .mmu = nv04_mmu_new,
129// .timer = nv04_timer_new, 129 .timer = nv04_timer_new,
130// .disp = nv04_disp_new, 130// .disp = nv04_disp_new,
131// .dma = nv04_dma_new, 131// .dma = nv04_dma_new,
132// .gr = nv10_gr_new, 132// .gr = nv10_gr_new,
@@ -145,7 +145,7 @@ nv11_chipset = {
145 .imem = nv04_instmem_new, 145 .imem = nv04_instmem_new,
146 .mc = nv04_mc_new, 146 .mc = nv04_mc_new,
147 .mmu = nv04_mmu_new, 147 .mmu = nv04_mmu_new,
148// .timer = nv04_timer_new, 148 .timer = nv04_timer_new,
149// .disp = nv04_disp_new, 149// .disp = nv04_disp_new,
150// .dma = nv04_dma_new, 150// .dma = nv04_dma_new,
151// .fifo = nv10_fifo_new, 151// .fifo = nv10_fifo_new,
@@ -166,7 +166,7 @@ nv15_chipset = {
166 .imem = nv04_instmem_new, 166 .imem = nv04_instmem_new,
167 .mc = nv04_mc_new, 167 .mc = nv04_mc_new,
168 .mmu = nv04_mmu_new, 168 .mmu = nv04_mmu_new,
169// .timer = nv04_timer_new, 169 .timer = nv04_timer_new,
170// .disp = nv04_disp_new, 170// .disp = nv04_disp_new,
171// .dma = nv04_dma_new, 171// .dma = nv04_dma_new,
172// .fifo = nv10_fifo_new, 172// .fifo = nv10_fifo_new,
@@ -187,7 +187,7 @@ nv17_chipset = {
187 .imem = nv04_instmem_new, 187 .imem = nv04_instmem_new,
188 .mc = nv04_mc_new, 188 .mc = nv04_mc_new,
189 .mmu = nv04_mmu_new, 189 .mmu = nv04_mmu_new,
190// .timer = nv04_timer_new, 190 .timer = nv04_timer_new,
191// .disp = nv04_disp_new, 191// .disp = nv04_disp_new,
192// .dma = nv04_dma_new, 192// .dma = nv04_dma_new,
193// .fifo = nv17_fifo_new, 193// .fifo = nv17_fifo_new,
@@ -208,7 +208,7 @@ nv18_chipset = {
208 .imem = nv04_instmem_new, 208 .imem = nv04_instmem_new,
209 .mc = nv04_mc_new, 209 .mc = nv04_mc_new,
210 .mmu = nv04_mmu_new, 210 .mmu = nv04_mmu_new,
211// .timer = nv04_timer_new, 211 .timer = nv04_timer_new,
212// .disp = nv04_disp_new, 212// .disp = nv04_disp_new,
213// .dma = nv04_dma_new, 213// .dma = nv04_dma_new,
214// .fifo = nv17_fifo_new, 214// .fifo = nv17_fifo_new,
@@ -229,7 +229,7 @@ nv1a_chipset = {
229 .imem = nv04_instmem_new, 229 .imem = nv04_instmem_new,
230 .mc = nv04_mc_new, 230 .mc = nv04_mc_new,
231 .mmu = nv04_mmu_new, 231 .mmu = nv04_mmu_new,
232// .timer = nv04_timer_new, 232 .timer = nv04_timer_new,
233// .disp = nv04_disp_new, 233// .disp = nv04_disp_new,
234// .dma = nv04_dma_new, 234// .dma = nv04_dma_new,
235// .fifo = nv10_fifo_new, 235// .fifo = nv10_fifo_new,
@@ -250,7 +250,7 @@ nv1f_chipset = {
250 .imem = nv04_instmem_new, 250 .imem = nv04_instmem_new,
251 .mc = nv04_mc_new, 251 .mc = nv04_mc_new,
252 .mmu = nv04_mmu_new, 252 .mmu = nv04_mmu_new,
253// .timer = nv04_timer_new, 253 .timer = nv04_timer_new,
254// .disp = nv04_disp_new, 254// .disp = nv04_disp_new,
255// .dma = nv04_dma_new, 255// .dma = nv04_dma_new,
256// .fifo = nv17_fifo_new, 256// .fifo = nv17_fifo_new,
@@ -271,7 +271,7 @@ nv20_chipset = {
271 .imem = nv04_instmem_new, 271 .imem = nv04_instmem_new,
272 .mc = nv04_mc_new, 272 .mc = nv04_mc_new,
273 .mmu = nv04_mmu_new, 273 .mmu = nv04_mmu_new,
274// .timer = nv04_timer_new, 274 .timer = nv04_timer_new,
275// .disp = nv04_disp_new, 275// .disp = nv04_disp_new,
276// .dma = nv04_dma_new, 276// .dma = nv04_dma_new,
277// .fifo = nv17_fifo_new, 277// .fifo = nv17_fifo_new,
@@ -292,7 +292,7 @@ nv25_chipset = {
292 .imem = nv04_instmem_new, 292 .imem = nv04_instmem_new,
293 .mc = nv04_mc_new, 293 .mc = nv04_mc_new,
294 .mmu = nv04_mmu_new, 294 .mmu = nv04_mmu_new,
295// .timer = nv04_timer_new, 295 .timer = nv04_timer_new,
296// .disp = nv04_disp_new, 296// .disp = nv04_disp_new,
297// .dma = nv04_dma_new, 297// .dma = nv04_dma_new,
298// .fifo = nv17_fifo_new, 298// .fifo = nv17_fifo_new,
@@ -313,7 +313,7 @@ nv28_chipset = {
313 .imem = nv04_instmem_new, 313 .imem = nv04_instmem_new,
314 .mc = nv04_mc_new, 314 .mc = nv04_mc_new,
315 .mmu = nv04_mmu_new, 315 .mmu = nv04_mmu_new,
316// .timer = nv04_timer_new, 316 .timer = nv04_timer_new,
317// .disp = nv04_disp_new, 317// .disp = nv04_disp_new,
318// .dma = nv04_dma_new, 318// .dma = nv04_dma_new,
319// .fifo = nv17_fifo_new, 319// .fifo = nv17_fifo_new,
@@ -334,7 +334,7 @@ nv2a_chipset = {
334 .imem = nv04_instmem_new, 334 .imem = nv04_instmem_new,
335 .mc = nv04_mc_new, 335 .mc = nv04_mc_new,
336 .mmu = nv04_mmu_new, 336 .mmu = nv04_mmu_new,
337// .timer = nv04_timer_new, 337 .timer = nv04_timer_new,
338// .disp = nv04_disp_new, 338// .disp = nv04_disp_new,
339// .dma = nv04_dma_new, 339// .dma = nv04_dma_new,
340// .fifo = nv17_fifo_new, 340// .fifo = nv17_fifo_new,
@@ -355,7 +355,7 @@ nv30_chipset = {
355 .imem = nv04_instmem_new, 355 .imem = nv04_instmem_new,
356 .mc = nv04_mc_new, 356 .mc = nv04_mc_new,
357 .mmu = nv04_mmu_new, 357 .mmu = nv04_mmu_new,
358// .timer = nv04_timer_new, 358 .timer = nv04_timer_new,
359// .disp = nv04_disp_new, 359// .disp = nv04_disp_new,
360// .dma = nv04_dma_new, 360// .dma = nv04_dma_new,
361// .fifo = nv17_fifo_new, 361// .fifo = nv17_fifo_new,
@@ -376,7 +376,7 @@ nv31_chipset = {
376 .imem = nv04_instmem_new, 376 .imem = nv04_instmem_new,
377 .mc = nv04_mc_new, 377 .mc = nv04_mc_new,
378 .mmu = nv04_mmu_new, 378 .mmu = nv04_mmu_new,
379// .timer = nv04_timer_new, 379 .timer = nv04_timer_new,
380// .disp = nv04_disp_new, 380// .disp = nv04_disp_new,
381// .dma = nv04_dma_new, 381// .dma = nv04_dma_new,
382// .fifo = nv17_fifo_new, 382// .fifo = nv17_fifo_new,
@@ -398,7 +398,7 @@ nv34_chipset = {
398 .imem = nv04_instmem_new, 398 .imem = nv04_instmem_new,
399 .mc = nv04_mc_new, 399 .mc = nv04_mc_new,
400 .mmu = nv04_mmu_new, 400 .mmu = nv04_mmu_new,
401// .timer = nv04_timer_new, 401 .timer = nv04_timer_new,
402// .disp = nv04_disp_new, 402// .disp = nv04_disp_new,
403// .dma = nv04_dma_new, 403// .dma = nv04_dma_new,
404// .fifo = nv17_fifo_new, 404// .fifo = nv17_fifo_new,
@@ -420,7 +420,7 @@ nv35_chipset = {
420 .imem = nv04_instmem_new, 420 .imem = nv04_instmem_new,
421 .mc = nv04_mc_new, 421 .mc = nv04_mc_new,
422 .mmu = nv04_mmu_new, 422 .mmu = nv04_mmu_new,
423// .timer = nv04_timer_new, 423 .timer = nv04_timer_new,
424// .disp = nv04_disp_new, 424// .disp = nv04_disp_new,
425// .dma = nv04_dma_new, 425// .dma = nv04_dma_new,
426// .fifo = nv17_fifo_new, 426// .fifo = nv17_fifo_new,
@@ -441,7 +441,7 @@ nv36_chipset = {
441 .imem = nv04_instmem_new, 441 .imem = nv04_instmem_new,
442 .mc = nv04_mc_new, 442 .mc = nv04_mc_new,
443 .mmu = nv04_mmu_new, 443 .mmu = nv04_mmu_new,
444// .timer = nv04_timer_new, 444 .timer = nv04_timer_new,
445// .disp = nv04_disp_new, 445// .disp = nv04_disp_new,
446// .dma = nv04_dma_new, 446// .dma = nv04_dma_new,
447// .fifo = nv17_fifo_new, 447// .fifo = nv17_fifo_new,
@@ -464,7 +464,7 @@ nv40_chipset = {
464 .mc = nv40_mc_new, 464 .mc = nv40_mc_new,
465 .mmu = nv04_mmu_new, 465 .mmu = nv04_mmu_new,
466 .therm = nv40_therm_new, 466 .therm = nv40_therm_new,
467// .timer = nv04_timer_new, 467 .timer = nv40_timer_new,
468// .volt = nv40_volt_new, 468// .volt = nv40_volt_new,
469// .disp = nv04_disp_new, 469// .disp = nv04_disp_new,
470// .dma = nv04_dma_new, 470// .dma = nv04_dma_new,
@@ -489,7 +489,7 @@ nv41_chipset = {
489 .mc = nv40_mc_new, 489 .mc = nv40_mc_new,
490 .mmu = nv41_mmu_new, 490 .mmu = nv41_mmu_new,
491 .therm = nv40_therm_new, 491 .therm = nv40_therm_new,
492// .timer = nv04_timer_new, 492 .timer = nv41_timer_new,
493// .volt = nv40_volt_new, 493// .volt = nv40_volt_new,
494// .disp = nv04_disp_new, 494// .disp = nv04_disp_new,
495// .dma = nv04_dma_new, 495// .dma = nv04_dma_new,
@@ -514,7 +514,7 @@ nv42_chipset = {
514 .mc = nv40_mc_new, 514 .mc = nv40_mc_new,
515 .mmu = nv41_mmu_new, 515 .mmu = nv41_mmu_new,
516 .therm = nv40_therm_new, 516 .therm = nv40_therm_new,
517// .timer = nv04_timer_new, 517 .timer = nv41_timer_new,
518// .volt = nv40_volt_new, 518// .volt = nv40_volt_new,
519// .disp = nv04_disp_new, 519// .disp = nv04_disp_new,
520// .dma = nv04_dma_new, 520// .dma = nv04_dma_new,
@@ -539,7 +539,7 @@ nv43_chipset = {
539 .mc = nv40_mc_new, 539 .mc = nv40_mc_new,
540 .mmu = nv41_mmu_new, 540 .mmu = nv41_mmu_new,
541 .therm = nv40_therm_new, 541 .therm = nv40_therm_new,
542// .timer = nv04_timer_new, 542 .timer = nv41_timer_new,
543// .volt = nv40_volt_new, 543// .volt = nv40_volt_new,
544// .disp = nv04_disp_new, 544// .disp = nv04_disp_new,
545// .dma = nv04_dma_new, 545// .dma = nv04_dma_new,
@@ -564,7 +564,7 @@ nv44_chipset = {
564 .mc = nv44_mc_new, 564 .mc = nv44_mc_new,
565 .mmu = nv44_mmu_new, 565 .mmu = nv44_mmu_new,
566 .therm = nv40_therm_new, 566 .therm = nv40_therm_new,
567// .timer = nv04_timer_new, 567 .timer = nv41_timer_new,
568// .volt = nv40_volt_new, 568// .volt = nv40_volt_new,
569// .disp = nv04_disp_new, 569// .disp = nv04_disp_new,
570// .dma = nv04_dma_new, 570// .dma = nv04_dma_new,
@@ -589,7 +589,7 @@ nv45_chipset = {
589 .mc = nv40_mc_new, 589 .mc = nv40_mc_new,
590 .mmu = nv04_mmu_new, 590 .mmu = nv04_mmu_new,
591 .therm = nv40_therm_new, 591 .therm = nv40_therm_new,
592// .timer = nv04_timer_new, 592 .timer = nv41_timer_new,
593// .volt = nv40_volt_new, 593// .volt = nv40_volt_new,
594// .disp = nv04_disp_new, 594// .disp = nv04_disp_new,
595// .dma = nv04_dma_new, 595// .dma = nv04_dma_new,
@@ -614,7 +614,7 @@ nv46_chipset = {
614 .mc = nv44_mc_new, 614 .mc = nv44_mc_new,
615 .mmu = nv44_mmu_new, 615 .mmu = nv44_mmu_new,
616 .therm = nv40_therm_new, 616 .therm = nv40_therm_new,
617// .timer = nv04_timer_new, 617 .timer = nv41_timer_new,
618// .volt = nv40_volt_new, 618// .volt = nv40_volt_new,
619// .disp = nv04_disp_new, 619// .disp = nv04_disp_new,
620// .dma = nv04_dma_new, 620// .dma = nv04_dma_new,
@@ -639,7 +639,7 @@ nv47_chipset = {
639 .mc = nv40_mc_new, 639 .mc = nv40_mc_new,
640 .mmu = nv41_mmu_new, 640 .mmu = nv41_mmu_new,
641 .therm = nv40_therm_new, 641 .therm = nv40_therm_new,
642// .timer = nv04_timer_new, 642 .timer = nv41_timer_new,
643// .volt = nv40_volt_new, 643// .volt = nv40_volt_new,
644// .disp = nv04_disp_new, 644// .disp = nv04_disp_new,
645// .dma = nv04_dma_new, 645// .dma = nv04_dma_new,
@@ -664,7 +664,7 @@ nv49_chipset = {
664 .mc = nv40_mc_new, 664 .mc = nv40_mc_new,
665 .mmu = nv41_mmu_new, 665 .mmu = nv41_mmu_new,
666 .therm = nv40_therm_new, 666 .therm = nv40_therm_new,
667// .timer = nv04_timer_new, 667 .timer = nv41_timer_new,
668// .volt = nv40_volt_new, 668// .volt = nv40_volt_new,
669// .disp = nv04_disp_new, 669// .disp = nv04_disp_new,
670// .dma = nv04_dma_new, 670// .dma = nv04_dma_new,
@@ -689,7 +689,7 @@ nv4a_chipset = {
689 .mc = nv44_mc_new, 689 .mc = nv44_mc_new,
690 .mmu = nv44_mmu_new, 690 .mmu = nv44_mmu_new,
691 .therm = nv40_therm_new, 691 .therm = nv40_therm_new,
692// .timer = nv04_timer_new, 692 .timer = nv41_timer_new,
693// .volt = nv40_volt_new, 693// .volt = nv40_volt_new,
694// .disp = nv04_disp_new, 694// .disp = nv04_disp_new,
695// .dma = nv04_dma_new, 695// .dma = nv04_dma_new,
@@ -714,7 +714,7 @@ nv4b_chipset = {
714 .mc = nv40_mc_new, 714 .mc = nv40_mc_new,
715 .mmu = nv41_mmu_new, 715 .mmu = nv41_mmu_new,
716 .therm = nv40_therm_new, 716 .therm = nv40_therm_new,
717// .timer = nv04_timer_new, 717 .timer = nv41_timer_new,
718// .volt = nv40_volt_new, 718// .volt = nv40_volt_new,
719// .disp = nv04_disp_new, 719// .disp = nv04_disp_new,
720// .dma = nv04_dma_new, 720// .dma = nv04_dma_new,
@@ -739,7 +739,7 @@ nv4c_chipset = {
739 .mc = nv4c_mc_new, 739 .mc = nv4c_mc_new,
740 .mmu = nv44_mmu_new, 740 .mmu = nv44_mmu_new,
741 .therm = nv40_therm_new, 741 .therm = nv40_therm_new,
742// .timer = nv04_timer_new, 742 .timer = nv41_timer_new,
743// .volt = nv40_volt_new, 743// .volt = nv40_volt_new,
744// .disp = nv04_disp_new, 744// .disp = nv04_disp_new,
745// .dma = nv04_dma_new, 745// .dma = nv04_dma_new,
@@ -764,7 +764,7 @@ nv4e_chipset = {
764 .mc = nv4c_mc_new, 764 .mc = nv4c_mc_new,
765 .mmu = nv44_mmu_new, 765 .mmu = nv44_mmu_new,
766 .therm = nv40_therm_new, 766 .therm = nv40_therm_new,
767// .timer = nv04_timer_new, 767 .timer = nv41_timer_new,
768// .volt = nv40_volt_new, 768// .volt = nv40_volt_new,
769// .disp = nv04_disp_new, 769// .disp = nv04_disp_new,
770// .dma = nv04_dma_new, 770// .dma = nv04_dma_new,
@@ -792,7 +792,7 @@ nv50_chipset = {
792 .mmu = nv50_mmu_new, 792 .mmu = nv50_mmu_new,
793 .mxm = nv50_mxm_new, 793 .mxm = nv50_mxm_new,
794 .therm = nv50_therm_new, 794 .therm = nv50_therm_new,
795// .timer = nv04_timer_new, 795 .timer = nv41_timer_new,
796// .volt = nv40_volt_new, 796// .volt = nv40_volt_new,
797// .disp = nv50_disp_new, 797// .disp = nv50_disp_new,
798// .dma = nv50_dma_new, 798// .dma = nv50_dma_new,
@@ -817,7 +817,7 @@ nv63_chipset = {
817 .mc = nv4c_mc_new, 817 .mc = nv4c_mc_new,
818 .mmu = nv44_mmu_new, 818 .mmu = nv44_mmu_new,
819 .therm = nv40_therm_new, 819 .therm = nv40_therm_new,
820// .timer = nv04_timer_new, 820 .timer = nv41_timer_new,
821// .volt = nv40_volt_new, 821// .volt = nv40_volt_new,
822// .disp = nv04_disp_new, 822// .disp = nv04_disp_new,
823// .dma = nv04_dma_new, 823// .dma = nv04_dma_new,
@@ -842,7 +842,7 @@ nv67_chipset = {
842 .mc = nv4c_mc_new, 842 .mc = nv4c_mc_new,
843 .mmu = nv44_mmu_new, 843 .mmu = nv44_mmu_new,
844 .therm = nv40_therm_new, 844 .therm = nv40_therm_new,
845// .timer = nv04_timer_new, 845 .timer = nv41_timer_new,
846// .volt = nv40_volt_new, 846// .volt = nv40_volt_new,
847// .disp = nv04_disp_new, 847// .disp = nv04_disp_new,
848// .dma = nv04_dma_new, 848// .dma = nv04_dma_new,
@@ -867,7 +867,7 @@ nv68_chipset = {
867 .mc = nv4c_mc_new, 867 .mc = nv4c_mc_new,
868 .mmu = nv44_mmu_new, 868 .mmu = nv44_mmu_new,
869 .therm = nv40_therm_new, 869 .therm = nv40_therm_new,
870// .timer = nv04_timer_new, 870 .timer = nv41_timer_new,
871// .volt = nv40_volt_new, 871// .volt = nv40_volt_new,
872// .disp = nv04_disp_new, 872// .disp = nv04_disp_new,
873// .dma = nv04_dma_new, 873// .dma = nv04_dma_new,
@@ -895,7 +895,7 @@ nv84_chipset = {
895 .mmu = nv50_mmu_new, 895 .mmu = nv50_mmu_new,
896 .mxm = nv50_mxm_new, 896 .mxm = nv50_mxm_new,
897 .therm = g84_therm_new, 897 .therm = g84_therm_new,
898// .timer = nv04_timer_new, 898 .timer = nv41_timer_new,
899// .volt = nv40_volt_new, 899// .volt = nv40_volt_new,
900// .bsp = g84_bsp_new, 900// .bsp = g84_bsp_new,
901// .cipher = g84_cipher_new, 901// .cipher = g84_cipher_new,
@@ -926,7 +926,7 @@ nv86_chipset = {
926 .mmu = nv50_mmu_new, 926 .mmu = nv50_mmu_new,
927 .mxm = nv50_mxm_new, 927 .mxm = nv50_mxm_new,
928 .therm = g84_therm_new, 928 .therm = g84_therm_new,
929// .timer = nv04_timer_new, 929 .timer = nv41_timer_new,
930// .volt = nv40_volt_new, 930// .volt = nv40_volt_new,
931// .bsp = g84_bsp_new, 931// .bsp = g84_bsp_new,
932// .cipher = g84_cipher_new, 932// .cipher = g84_cipher_new,
@@ -957,7 +957,7 @@ nv92_chipset = {
957 .mmu = nv50_mmu_new, 957 .mmu = nv50_mmu_new,
958 .mxm = nv50_mxm_new, 958 .mxm = nv50_mxm_new,
959 .therm = g84_therm_new, 959 .therm = g84_therm_new,
960// .timer = nv04_timer_new, 960 .timer = nv41_timer_new,
961// .volt = nv40_volt_new, 961// .volt = nv40_volt_new,
962// .bsp = g84_bsp_new, 962// .bsp = g84_bsp_new,
963// .cipher = g84_cipher_new, 963// .cipher = g84_cipher_new,
@@ -988,7 +988,7 @@ nv94_chipset = {
988 .mmu = nv50_mmu_new, 988 .mmu = nv50_mmu_new,
989 .mxm = nv50_mxm_new, 989 .mxm = nv50_mxm_new,
990 .therm = g84_therm_new, 990 .therm = g84_therm_new,
991// .timer = nv04_timer_new, 991 .timer = nv41_timer_new,
992// .volt = nv40_volt_new, 992// .volt = nv40_volt_new,
993// .bsp = g84_bsp_new, 993// .bsp = g84_bsp_new,
994// .cipher = g84_cipher_new, 994// .cipher = g84_cipher_new,
@@ -1015,7 +1015,7 @@ nv96_chipset = {
1015 .devinit = g84_devinit_new, 1015 .devinit = g84_devinit_new,
1016 .mc = g94_mc_new, 1016 .mc = g94_mc_new,
1017 .bus = g94_bus_new, 1017 .bus = g94_bus_new,
1018// .timer = nv04_timer_new, 1018 .timer = nv41_timer_new,
1019 .fb = g84_fb_new, 1019 .fb = g84_fb_new,
1020 .imem = nv50_instmem_new, 1020 .imem = nv50_instmem_new,
1021 .mmu = nv50_mmu_new, 1021 .mmu = nv50_mmu_new,
@@ -1046,7 +1046,7 @@ nv98_chipset = {
1046 .devinit = g98_devinit_new, 1046 .devinit = g98_devinit_new,
1047 .mc = g98_mc_new, 1047 .mc = g98_mc_new,
1048 .bus = g94_bus_new, 1048 .bus = g94_bus_new,
1049// .timer = nv04_timer_new, 1049 .timer = nv41_timer_new,
1050 .fb = g84_fb_new, 1050 .fb = g84_fb_new,
1051 .imem = nv50_instmem_new, 1051 .imem = nv50_instmem_new,
1052 .mmu = nv50_mmu_new, 1052 .mmu = nv50_mmu_new,
@@ -1081,7 +1081,7 @@ nva0_chipset = {
1081 .mmu = nv50_mmu_new, 1081 .mmu = nv50_mmu_new,
1082 .mxm = nv50_mxm_new, 1082 .mxm = nv50_mxm_new,
1083 .therm = g84_therm_new, 1083 .therm = g84_therm_new,
1084// .timer = nv04_timer_new, 1084 .timer = nv41_timer_new,
1085// .volt = nv40_volt_new, 1085// .volt = nv40_volt_new,
1086// .bsp = g84_bsp_new, 1086// .bsp = g84_bsp_new,
1087// .cipher = g84_cipher_new, 1087// .cipher = g84_cipher_new,
@@ -1113,7 +1113,7 @@ nva3_chipset = {
1113 .mxm = nv50_mxm_new, 1113 .mxm = nv50_mxm_new,
1114 .pmu = gt215_pmu_new, 1114 .pmu = gt215_pmu_new,
1115 .therm = gt215_therm_new, 1115 .therm = gt215_therm_new,
1116// .timer = nv04_timer_new, 1116 .timer = nv41_timer_new,
1117// .volt = nv40_volt_new, 1117// .volt = nv40_volt_new,
1118// .ce[0] = gt215_ce_new, 1118// .ce[0] = gt215_ce_new,
1119// .disp = gt215_disp_new, 1119// .disp = gt215_disp_new,
@@ -1146,7 +1146,7 @@ nva5_chipset = {
1146 .mxm = nv50_mxm_new, 1146 .mxm = nv50_mxm_new,
1147 .pmu = gt215_pmu_new, 1147 .pmu = gt215_pmu_new,
1148 .therm = gt215_therm_new, 1148 .therm = gt215_therm_new,
1149// .timer = nv04_timer_new, 1149 .timer = nv41_timer_new,
1150// .volt = nv40_volt_new, 1150// .volt = nv40_volt_new,
1151// .ce[0] = gt215_ce_new, 1151// .ce[0] = gt215_ce_new,
1152// .disp = gt215_disp_new, 1152// .disp = gt215_disp_new,
@@ -1178,7 +1178,7 @@ nva8_chipset = {
1178 .mxm = nv50_mxm_new, 1178 .mxm = nv50_mxm_new,
1179 .pmu = gt215_pmu_new, 1179 .pmu = gt215_pmu_new,
1180 .therm = gt215_therm_new, 1180 .therm = gt215_therm_new,
1181// .timer = nv04_timer_new, 1181 .timer = nv41_timer_new,
1182// .volt = nv40_volt_new, 1182// .volt = nv40_volt_new,
1183// .ce[0] = gt215_ce_new, 1183// .ce[0] = gt215_ce_new,
1184// .disp = gt215_disp_new, 1184// .disp = gt215_disp_new,
@@ -1209,7 +1209,7 @@ nvaa_chipset = {
1209 .mmu = nv50_mmu_new, 1209 .mmu = nv50_mmu_new,
1210 .mxm = nv50_mxm_new, 1210 .mxm = nv50_mxm_new,
1211 .therm = g84_therm_new, 1211 .therm = g84_therm_new,
1212// .timer = nv04_timer_new, 1212 .timer = nv41_timer_new,
1213// .volt = nv40_volt_new, 1213// .volt = nv40_volt_new,
1214// .disp = g94_disp_new, 1214// .disp = g94_disp_new,
1215// .dma = nv50_dma_new, 1215// .dma = nv50_dma_new,
@@ -1240,7 +1240,7 @@ nvac_chipset = {
1240 .mmu = nv50_mmu_new, 1240 .mmu = nv50_mmu_new,
1241 .mxm = nv50_mxm_new, 1241 .mxm = nv50_mxm_new,
1242 .therm = g84_therm_new, 1242 .therm = g84_therm_new,
1243// .timer = nv04_timer_new, 1243 .timer = nv41_timer_new,
1244// .volt = nv40_volt_new, 1244// .volt = nv40_volt_new,
1245// .disp = g94_disp_new, 1245// .disp = g94_disp_new,
1246// .dma = nv50_dma_new, 1246// .dma = nv50_dma_new,
@@ -1272,7 +1272,7 @@ nvaf_chipset = {
1272 .mxm = nv50_mxm_new, 1272 .mxm = nv50_mxm_new,
1273 .pmu = gt215_pmu_new, 1273 .pmu = gt215_pmu_new,
1274 .therm = gt215_therm_new, 1274 .therm = gt215_therm_new,
1275// .timer = nv04_timer_new, 1275 .timer = nv41_timer_new,
1276// .volt = nv40_volt_new, 1276// .volt = nv40_volt_new,
1277// .ce[0] = gt215_ce_new, 1277// .ce[0] = gt215_ce_new,
1278// .disp = gt215_disp_new, 1278// .disp = gt215_disp_new,
@@ -1306,7 +1306,7 @@ nvc0_chipset = {
1306 .mxm = nv50_mxm_new, 1306 .mxm = nv50_mxm_new,
1307 .pmu = gf100_pmu_new, 1307 .pmu = gf100_pmu_new,
1308 .therm = gt215_therm_new, 1308 .therm = gt215_therm_new,
1309// .timer = nv04_timer_new, 1309 .timer = nv41_timer_new,
1310// .volt = nv40_volt_new, 1310// .volt = nv40_volt_new,
1311// .ce[0] = gf100_ce0_new, 1311// .ce[0] = gf100_ce0_new,
1312// .ce[1] = gf100_ce1_new, 1312// .ce[1] = gf100_ce1_new,
@@ -1341,7 +1341,7 @@ nvc1_chipset = {
1341 .mxm = nv50_mxm_new, 1341 .mxm = nv50_mxm_new,
1342 .pmu = gf100_pmu_new, 1342 .pmu = gf100_pmu_new,
1343 .therm = gt215_therm_new, 1343 .therm = gt215_therm_new,
1344// .timer = nv04_timer_new, 1344 .timer = nv41_timer_new,
1345// .volt = nv40_volt_new, 1345// .volt = nv40_volt_new,
1346// .ce[0] = gf100_ce0_new, 1346// .ce[0] = gf100_ce0_new,
1347// .disp = gt215_disp_new, 1347// .disp = gt215_disp_new,
@@ -1375,7 +1375,7 @@ nvc3_chipset = {
1375 .mxm = nv50_mxm_new, 1375 .mxm = nv50_mxm_new,
1376 .pmu = gf100_pmu_new, 1376 .pmu = gf100_pmu_new,
1377 .therm = gt215_therm_new, 1377 .therm = gt215_therm_new,
1378// .timer = nv04_timer_new, 1378 .timer = nv41_timer_new,
1379// .volt = nv40_volt_new, 1379// .volt = nv40_volt_new,
1380// .ce[0] = gf100_ce0_new, 1380// .ce[0] = gf100_ce0_new,
1381// .disp = gt215_disp_new, 1381// .disp = gt215_disp_new,
@@ -1409,7 +1409,7 @@ nvc4_chipset = {
1409 .mxm = nv50_mxm_new, 1409 .mxm = nv50_mxm_new,
1410 .pmu = gf100_pmu_new, 1410 .pmu = gf100_pmu_new,
1411 .therm = gt215_therm_new, 1411 .therm = gt215_therm_new,
1412// .timer = nv04_timer_new, 1412 .timer = nv41_timer_new,
1413// .volt = nv40_volt_new, 1413// .volt = nv40_volt_new,
1414// .ce[0] = gf100_ce0_new, 1414// .ce[0] = gf100_ce0_new,
1415// .ce[1] = gf100_ce1_new, 1415// .ce[1] = gf100_ce1_new,
@@ -1444,7 +1444,7 @@ nvc8_chipset = {
1444 .mxm = nv50_mxm_new, 1444 .mxm = nv50_mxm_new,
1445 .pmu = gf100_pmu_new, 1445 .pmu = gf100_pmu_new,
1446 .therm = gt215_therm_new, 1446 .therm = gt215_therm_new,
1447// .timer = nv04_timer_new, 1447 .timer = nv41_timer_new,
1448// .volt = nv40_volt_new, 1448// .volt = nv40_volt_new,
1449// .ce[0] = gf100_ce0_new, 1449// .ce[0] = gf100_ce0_new,
1450// .ce[1] = gf100_ce1_new, 1450// .ce[1] = gf100_ce1_new,
@@ -1479,7 +1479,7 @@ nvce_chipset = {
1479 .mxm = nv50_mxm_new, 1479 .mxm = nv50_mxm_new,
1480 .pmu = gf100_pmu_new, 1480 .pmu = gf100_pmu_new,
1481 .therm = gt215_therm_new, 1481 .therm = gt215_therm_new,
1482// .timer = nv04_timer_new, 1482 .timer = nv41_timer_new,
1483// .volt = nv40_volt_new, 1483// .volt = nv40_volt_new,
1484// .ce[0] = gf100_ce0_new, 1484// .ce[0] = gf100_ce0_new,
1485// .ce[1] = gf100_ce1_new, 1485// .ce[1] = gf100_ce1_new,
@@ -1514,7 +1514,7 @@ nvcf_chipset = {
1514 .mxm = nv50_mxm_new, 1514 .mxm = nv50_mxm_new,
1515 .pmu = gf100_pmu_new, 1515 .pmu = gf100_pmu_new,
1516 .therm = gt215_therm_new, 1516 .therm = gt215_therm_new,
1517// .timer = nv04_timer_new, 1517 .timer = nv41_timer_new,
1518// .volt = nv40_volt_new, 1518// .volt = nv40_volt_new,
1519// .ce[0] = gf100_ce0_new, 1519// .ce[0] = gf100_ce0_new,
1520// .disp = gt215_disp_new, 1520// .disp = gt215_disp_new,
@@ -1547,7 +1547,7 @@ nvd7_chipset = {
1547 .mmu = gf100_mmu_new, 1547 .mmu = gf100_mmu_new,
1548 .mxm = nv50_mxm_new, 1548 .mxm = nv50_mxm_new,
1549 .therm = gf119_therm_new, 1549 .therm = gf119_therm_new,
1550// .timer = nv04_timer_new, 1550 .timer = nv41_timer_new,
1551// .ce[0] = gf100_ce0_new, 1551// .ce[0] = gf100_ce0_new,
1552// .disp = gf119_disp_new, 1552// .disp = gf119_disp_new,
1553// .dma = gf119_dma_new, 1553// .dma = gf119_dma_new,
@@ -1580,7 +1580,7 @@ nvd9_chipset = {
1580 .mxm = nv50_mxm_new, 1580 .mxm = nv50_mxm_new,
1581 .pmu = gf119_pmu_new, 1581 .pmu = gf119_pmu_new,
1582 .therm = gf119_therm_new, 1582 .therm = gf119_therm_new,
1583// .timer = nv04_timer_new, 1583 .timer = nv41_timer_new,
1584// .volt = nv40_volt_new, 1584// .volt = nv40_volt_new,
1585// .ce[0] = gf100_ce0_new, 1585// .ce[0] = gf100_ce0_new,
1586// .disp = gf119_disp_new, 1586// .disp = gf119_disp_new,
@@ -1614,7 +1614,7 @@ nve4_chipset = {
1614 .mxm = nv50_mxm_new, 1614 .mxm = nv50_mxm_new,
1615 .pmu = gk104_pmu_new, 1615 .pmu = gk104_pmu_new,
1616 .therm = gf119_therm_new, 1616 .therm = gf119_therm_new,
1617// .timer = nv04_timer_new, 1617 .timer = nv41_timer_new,
1618// .volt = nv40_volt_new, 1618// .volt = nv40_volt_new,
1619// .ce[0] = gk104_ce0_new, 1619// .ce[0] = gk104_ce0_new,
1620// .ce[1] = gk104_ce1_new, 1620// .ce[1] = gk104_ce1_new,
@@ -1650,7 +1650,7 @@ nve6_chipset = {
1650 .mxm = nv50_mxm_new, 1650 .mxm = nv50_mxm_new,
1651 .pmu = gk104_pmu_new, 1651 .pmu = gk104_pmu_new,
1652 .therm = gf119_therm_new, 1652 .therm = gf119_therm_new,
1653// .timer = nv04_timer_new, 1653 .timer = nv41_timer_new,
1654// .volt = nv40_volt_new, 1654// .volt = nv40_volt_new,
1655// .ce[0] = gk104_ce0_new, 1655// .ce[0] = gk104_ce0_new,
1656// .ce[1] = gk104_ce1_new, 1656// .ce[1] = gk104_ce1_new,
@@ -1686,7 +1686,7 @@ nve7_chipset = {
1686 .mxm = nv50_mxm_new, 1686 .mxm = nv50_mxm_new,
1687 .pmu = gf119_pmu_new, 1687 .pmu = gf119_pmu_new,
1688 .therm = gf119_therm_new, 1688 .therm = gf119_therm_new,
1689// .timer = nv04_timer_new, 1689 .timer = nv41_timer_new,
1690// .volt = nv40_volt_new, 1690// .volt = nv40_volt_new,
1691// .ce[0] = gk104_ce0_new, 1691// .ce[0] = gk104_ce0_new,
1692// .ce[1] = gk104_ce1_new, 1692// .ce[1] = gk104_ce1_new,
@@ -1716,7 +1716,7 @@ nvea_chipset = {
1716 .mc = gk20a_mc_new, 1716 .mc = gk20a_mc_new,
1717 .mmu = gf100_mmu_new, 1717 .mmu = gf100_mmu_new,
1718 .pmu = gk20a_pmu_new, 1718 .pmu = gk20a_pmu_new,
1719// .timer = gk20a_timer_new, 1719 .timer = gk20a_timer_new,
1720// .volt = gk20a_volt_new, 1720// .volt = gk20a_volt_new,
1721// .ce[2] = gk104_ce2_new, 1721// .ce[2] = gk104_ce2_new,
1722// .dma = gf119_dma_new, 1722// .dma = gf119_dma_new,
@@ -1746,7 +1746,7 @@ nvf0_chipset = {
1746 .mxm = nv50_mxm_new, 1746 .mxm = nv50_mxm_new,
1747 .pmu = gk110_pmu_new, 1747 .pmu = gk110_pmu_new,
1748 .therm = gf119_therm_new, 1748 .therm = gf119_therm_new,
1749// .timer = nv04_timer_new, 1749 .timer = nv41_timer_new,
1750// .volt = nv40_volt_new, 1750// .volt = nv40_volt_new,
1751// .ce[0] = gk104_ce0_new, 1751// .ce[0] = gk104_ce0_new,
1752// .ce[1] = gk104_ce1_new, 1752// .ce[1] = gk104_ce1_new,
@@ -1782,7 +1782,7 @@ nvf1_chipset = {
1782 .mxm = nv50_mxm_new, 1782 .mxm = nv50_mxm_new,
1783 .pmu = gk110_pmu_new, 1783 .pmu = gk110_pmu_new,
1784 .therm = gf119_therm_new, 1784 .therm = gf119_therm_new,
1785// .timer = nv04_timer_new, 1785 .timer = nv41_timer_new,
1786// .volt = nv40_volt_new, 1786// .volt = nv40_volt_new,
1787// .ce[0] = gk104_ce0_new, 1787// .ce[0] = gk104_ce0_new,
1788// .ce[1] = gk104_ce1_new, 1788// .ce[1] = gk104_ce1_new,
@@ -1818,7 +1818,7 @@ nv106_chipset = {
1818 .mxm = nv50_mxm_new, 1818 .mxm = nv50_mxm_new,
1819 .pmu = gk208_pmu_new, 1819 .pmu = gk208_pmu_new,
1820 .therm = gf119_therm_new, 1820 .therm = gf119_therm_new,
1821// .timer = nv04_timer_new, 1821 .timer = nv41_timer_new,
1822// .volt = nv40_volt_new, 1822// .volt = nv40_volt_new,
1823// .ce[0] = gk104_ce0_new, 1823// .ce[0] = gk104_ce0_new,
1824// .ce[1] = gk104_ce1_new, 1824// .ce[1] = gk104_ce1_new,
@@ -1853,7 +1853,7 @@ nv108_chipset = {
1853 .mxm = nv50_mxm_new, 1853 .mxm = nv50_mxm_new,
1854 .pmu = gk208_pmu_new, 1854 .pmu = gk208_pmu_new,
1855 .therm = gf119_therm_new, 1855 .therm = gf119_therm_new,
1856// .timer = nv04_timer_new, 1856 .timer = nv41_timer_new,
1857// .volt = nv40_volt_new, 1857// .volt = nv40_volt_new,
1858// .ce[0] = gk104_ce0_new, 1858// .ce[0] = gk104_ce0_new,
1859// .ce[1] = gk104_ce1_new, 1859// .ce[1] = gk104_ce1_new,
@@ -1888,7 +1888,7 @@ nv117_chipset = {
1888 .mxm = nv50_mxm_new, 1888 .mxm = nv50_mxm_new,
1889 .pmu = gm107_pmu_new, 1889 .pmu = gm107_pmu_new,
1890 .therm = gm107_therm_new, 1890 .therm = gm107_therm_new,
1891// .timer = gk20a_timer_new, 1891 .timer = gk20a_timer_new,
1892// .ce[0] = gk104_ce0_new, 1892// .ce[0] = gk104_ce0_new,
1893// .ce[2] = gk104_ce2_new, 1893// .ce[2] = gk104_ce2_new,
1894// .disp = gm107_disp_new, 1894// .disp = gm107_disp_new,
@@ -1916,7 +1916,7 @@ nv124_chipset = {
1916 .mmu = gf100_mmu_new, 1916 .mmu = gf100_mmu_new,
1917 .mxm = nv50_mxm_new, 1917 .mxm = nv50_mxm_new,
1918 .pmu = gm107_pmu_new, 1918 .pmu = gm107_pmu_new,
1919// .timer = gk20a_timer_new, 1919 .timer = gk20a_timer_new,
1920// .ce[0] = gm204_ce0_new, 1920// .ce[0] = gm204_ce0_new,
1921// .ce[1] = gm204_ce1_new, 1921// .ce[1] = gm204_ce1_new,
1922// .ce[2] = gm204_ce2_new, 1922// .ce[2] = gm204_ce2_new,
@@ -1945,7 +1945,7 @@ nv126_chipset = {
1945 .mmu = gf100_mmu_new, 1945 .mmu = gf100_mmu_new,
1946 .mxm = nv50_mxm_new, 1946 .mxm = nv50_mxm_new,
1947 .pmu = gm107_pmu_new, 1947 .pmu = gm107_pmu_new,
1948// .timer = gk20a_timer_new, 1948 .timer = gk20a_timer_new,
1949// .ce[0] = gm204_ce0_new, 1949// .ce[0] = gm204_ce0_new,
1950// .ce[1] = gm204_ce1_new, 1950// .ce[1] = gm204_ce1_new,
1951// .ce[2] = gm204_ce2_new, 1951// .ce[2] = gm204_ce2_new,
@@ -1969,7 +1969,7 @@ nv12b_chipset = {
1969 .mc = gk20a_mc_new, 1969 .mc = gk20a_mc_new,
1970 .mmu = gf100_mmu_new, 1970 .mmu = gf100_mmu_new,
1971 .mmu = gf100_mmu_new, 1971 .mmu = gf100_mmu_new,
1972// .timer = gk20a_timer_new, 1972 .timer = gk20a_timer_new,
1973// .ce[2] = gm204_ce2_new, 1973// .ce[2] = gm204_ce2_new,
1974// .dma = gf119_dma_new, 1974// .dma = gf119_dma_new,
1975// .fifo = gm20b_fifo_new, 1975// .fifo = gm20b_fifo_new,
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/gf100.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/gf100.c
index dcaa480cd310..28421e6f1f26 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/gf100.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/gf100.c
@@ -28,7 +28,6 @@ gf100_identify(struct nvkm_device *device)
28{ 28{
29 switch (device->chipset) { 29 switch (device->chipset) {
30 case 0xc0: 30 case 0xc0:
31 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
32 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; 31 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
33 device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass; 32 device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass;
34 device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass; 33 device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
@@ -43,7 +42,6 @@ gf100_identify(struct nvkm_device *device)
43 device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass; 42 device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass;
44 break; 43 break;
45 case 0xc4: 44 case 0xc4:
46 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
47 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; 45 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
48 device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass; 46 device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass;
49 device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass; 47 device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
@@ -58,7 +56,6 @@ gf100_identify(struct nvkm_device *device)
58 device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass; 56 device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass;
59 break; 57 break;
60 case 0xc3: 58 case 0xc3:
61 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
62 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; 59 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
63 device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass; 60 device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass;
64 device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass; 61 device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
@@ -72,7 +69,6 @@ gf100_identify(struct nvkm_device *device)
72 device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass; 69 device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass;
73 break; 70 break;
74 case 0xce: 71 case 0xce:
75 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
76 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; 72 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
77 device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass; 73 device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass;
78 device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass; 74 device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
@@ -87,7 +83,6 @@ gf100_identify(struct nvkm_device *device)
87 device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass; 83 device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass;
88 break; 84 break;
89 case 0xcf: 85 case 0xcf:
90 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
91 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; 86 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
92 device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass; 87 device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass;
93 device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass; 88 device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
@@ -101,7 +96,6 @@ gf100_identify(struct nvkm_device *device)
101 device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass; 96 device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass;
102 break; 97 break;
103 case 0xc1: 98 case 0xc1:
104 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
105 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; 99 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
106 device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass; 100 device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass;
107 device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass; 101 device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
@@ -115,7 +109,6 @@ gf100_identify(struct nvkm_device *device)
115 device->oclass[NVDEV_ENGINE_PM ] = gf108_pm_oclass; 109 device->oclass[NVDEV_ENGINE_PM ] = gf108_pm_oclass;
116 break; 110 break;
117 case 0xc8: 111 case 0xc8:
118 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
119 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; 112 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
120 device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass; 113 device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass;
121 device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass; 114 device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
@@ -130,7 +123,6 @@ gf100_identify(struct nvkm_device *device)
130 device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass; 123 device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass;
131 break; 124 break;
132 case 0xd9: 125 case 0xd9:
133 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
134 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; 126 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
135 device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass; 127 device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
136 device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass; 128 device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
@@ -144,7 +136,6 @@ gf100_identify(struct nvkm_device *device)
144 device->oclass[NVDEV_ENGINE_PM ] = gf117_pm_oclass; 136 device->oclass[NVDEV_ENGINE_PM ] = gf117_pm_oclass;
145 break; 137 break;
146 case 0xd7: 138 case 0xd7:
147 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
148 device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass; 139 device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
149 device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass; 140 device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
150 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; 141 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/gk104.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/gk104.c
index 048f1beab81d..25d9092455aa 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/gk104.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/gk104.c
@@ -28,7 +28,6 @@ gk104_identify(struct nvkm_device *device)
28{ 28{
29 switch (device->chipset) { 29 switch (device->chipset) {
30 case 0xe4: 30 case 0xe4:
31 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
32 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; 31 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
33 device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass; 32 device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
34 device->oclass[NVDEV_ENGINE_FIFO ] = gk104_fifo_oclass; 33 device->oclass[NVDEV_ENGINE_FIFO ] = gk104_fifo_oclass;
@@ -44,7 +43,6 @@ gk104_identify(struct nvkm_device *device)
44 device->oclass[NVDEV_ENGINE_PM ] = gk104_pm_oclass; 43 device->oclass[NVDEV_ENGINE_PM ] = gk104_pm_oclass;
45 break; 44 break;
46 case 0xe7: 45 case 0xe7:
47 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
48 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; 46 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
49 device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass; 47 device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
50 device->oclass[NVDEV_ENGINE_FIFO ] = gk104_fifo_oclass; 48 device->oclass[NVDEV_ENGINE_FIFO ] = gk104_fifo_oclass;
@@ -60,7 +58,6 @@ gk104_identify(struct nvkm_device *device)
60 device->oclass[NVDEV_ENGINE_PM ] = gk104_pm_oclass; 58 device->oclass[NVDEV_ENGINE_PM ] = gk104_pm_oclass;
61 break; 59 break;
62 case 0xe6: 60 case 0xe6:
63 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
64 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; 61 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
65 device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass; 62 device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
66 device->oclass[NVDEV_ENGINE_FIFO ] = gk104_fifo_oclass; 63 device->oclass[NVDEV_ENGINE_FIFO ] = gk104_fifo_oclass;
@@ -76,7 +73,6 @@ gk104_identify(struct nvkm_device *device)
76 device->oclass[NVDEV_ENGINE_PM ] = gk104_pm_oclass; 73 device->oclass[NVDEV_ENGINE_PM ] = gk104_pm_oclass;
77 break; 74 break;
78 case 0xea: 75 case 0xea:
79 device->oclass[NVDEV_SUBDEV_TIMER ] = &gk20a_timer_oclass;
80 device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass; 76 device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
81 device->oclass[NVDEV_ENGINE_FIFO ] = gk20a_fifo_oclass; 77 device->oclass[NVDEV_ENGINE_FIFO ] = gk20a_fifo_oclass;
82 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; 78 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
@@ -86,7 +82,6 @@ gk104_identify(struct nvkm_device *device)
86 device->oclass[NVDEV_SUBDEV_VOLT ] = &gk20a_volt_oclass; 82 device->oclass[NVDEV_SUBDEV_VOLT ] = &gk20a_volt_oclass;
87 break; 83 break;
88 case 0xf0: 84 case 0xf0:
89 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
90 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; 85 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
91 device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass; 86 device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
92 device->oclass[NVDEV_ENGINE_FIFO ] = gk104_fifo_oclass; 87 device->oclass[NVDEV_ENGINE_FIFO ] = gk104_fifo_oclass;
@@ -102,7 +97,6 @@ gk104_identify(struct nvkm_device *device)
102 device->oclass[NVDEV_ENGINE_PM ] = &gk110_pm_oclass; 97 device->oclass[NVDEV_ENGINE_PM ] = &gk110_pm_oclass;
103 break; 98 break;
104 case 0xf1: 99 case 0xf1:
105 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
106 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; 100 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
107 device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass; 101 device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
108 device->oclass[NVDEV_ENGINE_FIFO ] = gk104_fifo_oclass; 102 device->oclass[NVDEV_ENGINE_FIFO ] = gk104_fifo_oclass;
@@ -118,7 +112,6 @@ gk104_identify(struct nvkm_device *device)
118 device->oclass[NVDEV_ENGINE_PM ] = &gk110_pm_oclass; 112 device->oclass[NVDEV_ENGINE_PM ] = &gk110_pm_oclass;
119 break; 113 break;
120 case 0x106: 114 case 0x106:
121 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
122 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; 115 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
123 device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass; 116 device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
124 device->oclass[NVDEV_ENGINE_FIFO ] = gk208_fifo_oclass; 117 device->oclass[NVDEV_ENGINE_FIFO ] = gk208_fifo_oclass;
@@ -133,7 +126,6 @@ gk104_identify(struct nvkm_device *device)
133 device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass; 126 device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass;
134 break; 127 break;
135 case 0x108: 128 case 0x108:
136 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
137 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; 129 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
138 device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass; 130 device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
139 device->oclass[NVDEV_ENGINE_FIFO ] = gk208_fifo_oclass; 131 device->oclass[NVDEV_ENGINE_FIFO ] = gk208_fifo_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c
index e2d00b465b80..4b570a27e13a 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c
@@ -28,7 +28,6 @@ gm100_identify(struct nvkm_device *device)
28{ 28{
29 switch (device->chipset) { 29 switch (device->chipset) {
30 case 0x117: 30 case 0x117:
31 device->oclass[NVDEV_SUBDEV_TIMER ] = &gk20a_timer_oclass;
32 31
33#if 0 32#if 0
34 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; 33 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
@@ -54,7 +53,6 @@ gm100_identify(struct nvkm_device *device)
54 /* looks to be some non-trivial changes */ 53 /* looks to be some non-trivial changes */
55 /* priv ring says no to 0x10eb14 writes */ 54 /* priv ring says no to 0x10eb14 writes */
56#endif 55#endif
57 device->oclass[NVDEV_SUBDEV_TIMER ] = &gk20a_timer_oclass;
58#if 0 56#if 0
59 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; 57 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
60#endif 58#endif
@@ -77,7 +75,6 @@ gm100_identify(struct nvkm_device *device)
77 /* looks to be some non-trivial changes */ 75 /* looks to be some non-trivial changes */
78 /* priv ring says no to 0x10eb14 writes */ 76 /* priv ring says no to 0x10eb14 writes */
79#endif 77#endif
80 device->oclass[NVDEV_SUBDEV_TIMER ] = &gk20a_timer_oclass;
81#if 0 78#if 0
82 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; 79 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
83#endif 80#endif
@@ -97,7 +94,6 @@ gm100_identify(struct nvkm_device *device)
97 break; 94 break;
98 case 0x12b: 95 case 0x12b:
99 96
100 device->oclass[NVDEV_SUBDEV_TIMER ] = &gk20a_timer_oclass;
101 device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass; 97 device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
102 device->oclass[NVDEV_ENGINE_FIFO ] = gm20b_fifo_oclass; 98 device->oclass[NVDEV_ENGINE_FIFO ] = gm20b_fifo_oclass;
103 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; 99 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv04.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv04.c
index 99e837f4879e..1b2ebda82c1f 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv04.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv04.c
@@ -28,7 +28,6 @@ nv04_identify(struct nvkm_device *device)
28{ 28{
29 switch (device->chipset) { 29 switch (device->chipset) {
30 case 0x04: 30 case 0x04:
31 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
32 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; 31 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
33 device->oclass[NVDEV_ENGINE_FIFO ] = nv04_fifo_oclass; 32 device->oclass[NVDEV_ENGINE_FIFO ] = nv04_fifo_oclass;
34 device->oclass[NVDEV_ENGINE_SW ] = nv04_sw_oclass; 33 device->oclass[NVDEV_ENGINE_SW ] = nv04_sw_oclass;
@@ -36,7 +35,6 @@ nv04_identify(struct nvkm_device *device)
36 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; 35 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
37 break; 36 break;
38 case 0x05: 37 case 0x05:
39 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
40 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; 38 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
41 device->oclass[NVDEV_ENGINE_FIFO ] = nv04_fifo_oclass; 39 device->oclass[NVDEV_ENGINE_FIFO ] = nv04_fifo_oclass;
42 device->oclass[NVDEV_ENGINE_SW ] = nv04_sw_oclass; 40 device->oclass[NVDEV_ENGINE_SW ] = nv04_sw_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c
index 6f106f632e63..c5ecdddfbce3 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c
@@ -28,13 +28,11 @@ nv10_identify(struct nvkm_device *device)
28{ 28{
29 switch (device->chipset) { 29 switch (device->chipset) {
30 case 0x10: 30 case 0x10:
31 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
32 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; 31 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
33 device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass; 32 device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass;
34 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; 33 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
35 break; 34 break;
36 case 0x15: 35 case 0x15:
37 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
38 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; 36 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
39 device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass; 37 device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass;
40 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; 38 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
@@ -42,7 +40,6 @@ nv10_identify(struct nvkm_device *device)
42 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; 40 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
43 break; 41 break;
44 case 0x16: 42 case 0x16:
45 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
46 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; 43 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
47 device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass; 44 device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass;
48 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; 45 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
@@ -50,7 +47,6 @@ nv10_identify(struct nvkm_device *device)
50 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; 47 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
51 break; 48 break;
52 case 0x1a: 49 case 0x1a:
53 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
54 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; 50 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
55 device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass; 51 device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass;
56 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; 52 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
@@ -58,7 +54,6 @@ nv10_identify(struct nvkm_device *device)
58 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; 54 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
59 break; 55 break;
60 case 0x11: 56 case 0x11:
61 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
62 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; 57 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
63 device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass; 58 device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass;
64 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; 59 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
@@ -66,7 +61,6 @@ nv10_identify(struct nvkm_device *device)
66 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; 61 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
67 break; 62 break;
68 case 0x17: 63 case 0x17:
69 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
70 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; 64 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
71 device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; 65 device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
72 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; 66 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
@@ -74,7 +68,6 @@ nv10_identify(struct nvkm_device *device)
74 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; 68 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
75 break; 69 break;
76 case 0x1f: 70 case 0x1f:
77 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
78 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; 71 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
79 device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; 72 device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
80 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; 73 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
@@ -82,7 +75,6 @@ nv10_identify(struct nvkm_device *device)
82 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; 75 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
83 break; 76 break;
84 case 0x18: 77 case 0x18:
85 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
86 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; 78 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
87 device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; 79 device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
88 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; 80 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv20.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv20.c
index 2a84c3ff8538..104ed4f093b5 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv20.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv20.c
@@ -28,7 +28,6 @@ nv20_identify(struct nvkm_device *device)
28{ 28{
29 switch (device->chipset) { 29 switch (device->chipset) {
30 case 0x20: 30 case 0x20:
31 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
32 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; 31 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
33 device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; 32 device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
34 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; 33 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
@@ -36,7 +35,6 @@ nv20_identify(struct nvkm_device *device)
36 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; 35 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
37 break; 36 break;
38 case 0x25: 37 case 0x25:
39 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
40 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; 38 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
41 device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; 39 device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
42 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; 40 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
@@ -44,7 +42,6 @@ nv20_identify(struct nvkm_device *device)
44 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; 42 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
45 break; 43 break;
46 case 0x28: 44 case 0x28:
47 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
48 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; 45 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
49 device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; 46 device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
50 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; 47 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
@@ -52,7 +49,6 @@ nv20_identify(struct nvkm_device *device)
52 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; 49 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
53 break; 50 break;
54 case 0x2a: 51 case 0x2a:
55 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
56 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; 52 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
57 device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; 53 device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
58 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; 54 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv30.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv30.c
index b03249099bb5..5ea263c85043 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv30.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv30.c
@@ -28,7 +28,6 @@ nv30_identify(struct nvkm_device *device)
28{ 28{
29 switch (device->chipset) { 29 switch (device->chipset) {
30 case 0x30: 30 case 0x30:
31 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
32 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; 31 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
33 device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; 32 device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
34 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; 33 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
@@ -36,7 +35,6 @@ nv30_identify(struct nvkm_device *device)
36 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; 35 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
37 break; 36 break;
38 case 0x35: 37 case 0x35:
39 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
40 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; 38 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
41 device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; 39 device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
42 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; 40 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
@@ -44,7 +42,6 @@ nv30_identify(struct nvkm_device *device)
44 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; 42 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
45 break; 43 break;
46 case 0x31: 44 case 0x31:
47 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
48 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; 45 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
49 device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; 46 device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
50 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; 47 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
@@ -53,7 +50,6 @@ nv30_identify(struct nvkm_device *device)
53 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; 50 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
54 break; 51 break;
55 case 0x36: 52 case 0x36:
56 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
57 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; 53 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
58 device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; 54 device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
59 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; 55 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
@@ -62,7 +58,6 @@ nv30_identify(struct nvkm_device *device)
62 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; 58 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
63 break; 59 break;
64 case 0x34: 60 case 0x34:
65 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
66 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; 61 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
67 device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; 62 device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
68 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; 63 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c
index 5aa4cac00402..31df1b8ae705 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c
@@ -28,7 +28,6 @@ nv40_identify(struct nvkm_device *device)
28{ 28{
29 switch (device->chipset) { 29 switch (device->chipset) {
30 case 0x40: 30 case 0x40:
31 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
32 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; 31 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
33 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; 32 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
34 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; 33 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
@@ -39,7 +38,6 @@ nv40_identify(struct nvkm_device *device)
39 device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; 38 device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
40 break; 39 break;
41 case 0x41: 40 case 0x41:
42 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
43 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; 41 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
44 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; 42 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
45 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; 43 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
@@ -50,7 +48,6 @@ nv40_identify(struct nvkm_device *device)
50 device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; 48 device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
51 break; 49 break;
52 case 0x42: 50 case 0x42:
53 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
54 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; 51 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
55 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; 52 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
56 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; 53 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
@@ -61,7 +58,6 @@ nv40_identify(struct nvkm_device *device)
61 device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; 58 device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
62 break; 59 break;
63 case 0x43: 60 case 0x43:
64 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
65 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; 61 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
66 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; 62 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
67 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; 63 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
@@ -72,7 +68,6 @@ nv40_identify(struct nvkm_device *device)
72 device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; 68 device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
73 break; 69 break;
74 case 0x45: 70 case 0x45:
75 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
76 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; 71 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
77 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; 72 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
78 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; 73 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
@@ -83,7 +78,6 @@ nv40_identify(struct nvkm_device *device)
83 device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; 78 device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
84 break; 79 break;
85 case 0x47: 80 case 0x47:
86 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
87 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; 81 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
88 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; 82 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
89 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; 83 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
@@ -94,7 +88,6 @@ nv40_identify(struct nvkm_device *device)
94 device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; 88 device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
95 break; 89 break;
96 case 0x49: 90 case 0x49:
97 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
98 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; 91 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
99 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; 92 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
100 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; 93 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
@@ -105,7 +98,6 @@ nv40_identify(struct nvkm_device *device)
105 device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; 98 device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
106 break; 99 break;
107 case 0x4b: 100 case 0x4b:
108 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
109 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; 101 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
110 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; 102 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
111 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; 103 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
@@ -116,7 +108,6 @@ nv40_identify(struct nvkm_device *device)
116 device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; 108 device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
117 break; 109 break;
118 case 0x44: 110 case 0x44:
119 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
120 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; 111 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
121 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; 112 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
122 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; 113 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
@@ -127,7 +118,6 @@ nv40_identify(struct nvkm_device *device)
127 device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; 118 device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
128 break; 119 break;
129 case 0x46: 120 case 0x46:
130 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
131 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; 121 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
132 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; 122 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
133 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; 123 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
@@ -138,7 +128,6 @@ nv40_identify(struct nvkm_device *device)
138 device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; 128 device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
139 break; 129 break;
140 case 0x4a: 130 case 0x4a:
141 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
142 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; 131 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
143 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; 132 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
144 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; 133 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
@@ -149,7 +138,6 @@ nv40_identify(struct nvkm_device *device)
149 device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; 138 device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
150 break; 139 break;
151 case 0x4c: 140 case 0x4c:
152 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
153 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; 141 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
154 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; 142 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
155 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; 143 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
@@ -160,7 +148,6 @@ nv40_identify(struct nvkm_device *device)
160 device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; 148 device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
161 break; 149 break;
162 case 0x4e: 150 case 0x4e:
163 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
164 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; 151 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
165 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; 152 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
166 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; 153 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
@@ -171,7 +158,6 @@ nv40_identify(struct nvkm_device *device)
171 device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; 158 device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
172 break; 159 break;
173 case 0x63: 160 case 0x63:
174 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
175 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; 161 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
176 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; 162 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
177 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; 163 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
@@ -182,7 +168,6 @@ nv40_identify(struct nvkm_device *device)
182 device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; 168 device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
183 break; 169 break;
184 case 0x67: 170 case 0x67:
185 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
186 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; 171 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
187 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; 172 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
188 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; 173 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
@@ -193,7 +178,6 @@ nv40_identify(struct nvkm_device *device)
193 device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; 178 device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
194 break; 179 break;
195 case 0x68: 180 case 0x68:
196 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
197 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; 181 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
198 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; 182 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
199 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; 183 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
index 8cc924046b78..e01add48ceb3 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
@@ -28,7 +28,6 @@ nv50_identify(struct nvkm_device *device)
28{ 28{
29 switch (device->chipset) { 29 switch (device->chipset) {
30 case 0x50: 30 case 0x50:
31 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
32 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; 31 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
33 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; 32 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
34 device->oclass[NVDEV_ENGINE_FIFO ] = nv50_fifo_oclass; 33 device->oclass[NVDEV_ENGINE_FIFO ] = nv50_fifo_oclass;
@@ -39,7 +38,6 @@ nv50_identify(struct nvkm_device *device)
39 device->oclass[NVDEV_ENGINE_PM ] = nv50_pm_oclass; 38 device->oclass[NVDEV_ENGINE_PM ] = nv50_pm_oclass;
40 break; 39 break;
41 case 0x84: 40 case 0x84:
42 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
43 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; 41 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
44 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; 42 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
45 device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass; 43 device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
@@ -53,7 +51,6 @@ nv50_identify(struct nvkm_device *device)
53 device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass; 51 device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass;
54 break; 52 break;
55 case 0x86: 53 case 0x86:
56 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
57 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; 54 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
58 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; 55 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
59 device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass; 56 device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
@@ -67,7 +64,6 @@ nv50_identify(struct nvkm_device *device)
67 device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass; 64 device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass;
68 break; 65 break;
69 case 0x92: 66 case 0x92:
70 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
71 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; 67 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
72 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; 68 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
73 device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass; 69 device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
@@ -81,7 +77,6 @@ nv50_identify(struct nvkm_device *device)
81 device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass; 77 device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass;
82 break; 78 break;
83 case 0x94: 79 case 0x94:
84 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
85 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; 80 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
86 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; 81 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
87 device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass; 82 device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
@@ -95,7 +90,6 @@ nv50_identify(struct nvkm_device *device)
95 device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass; 90 device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass;
96 break; 91 break;
97 case 0x96: 92 case 0x96:
98 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
99 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; 93 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
100 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; 94 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
101 device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass; 95 device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
@@ -109,7 +103,6 @@ nv50_identify(struct nvkm_device *device)
109 device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass; 103 device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass;
110 break; 104 break;
111 case 0x98: 105 case 0x98:
112 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
113 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; 106 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
114 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; 107 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
115 device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass; 108 device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
@@ -123,7 +116,6 @@ nv50_identify(struct nvkm_device *device)
123 device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass; 116 device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass;
124 break; 117 break;
125 case 0xa0: 118 case 0xa0:
126 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
127 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; 119 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
128 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; 120 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
129 device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass; 121 device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
@@ -137,7 +129,6 @@ nv50_identify(struct nvkm_device *device)
137 device->oclass[NVDEV_ENGINE_PM ] = gt200_pm_oclass; 129 device->oclass[NVDEV_ENGINE_PM ] = gt200_pm_oclass;
138 break; 130 break;
139 case 0xaa: 131 case 0xaa:
140 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
141 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; 132 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
142 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; 133 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
143 device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass; 134 device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
@@ -151,7 +142,6 @@ nv50_identify(struct nvkm_device *device)
151 device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass; 142 device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass;
152 break; 143 break;
153 case 0xac: 144 case 0xac:
154 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
155 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; 145 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
156 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; 146 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
157 device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass; 147 device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
@@ -165,7 +155,6 @@ nv50_identify(struct nvkm_device *device)
165 device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass; 155 device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass;
166 break; 156 break;
167 case 0xa3: 157 case 0xa3:
168 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
169 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; 158 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
170 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; 159 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
171 device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass; 160 device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
@@ -180,7 +169,6 @@ nv50_identify(struct nvkm_device *device)
180 device->oclass[NVDEV_ENGINE_PM ] = gt215_pm_oclass; 169 device->oclass[NVDEV_ENGINE_PM ] = gt215_pm_oclass;
181 break; 170 break;
182 case 0xa5: 171 case 0xa5:
183 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
184 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; 172 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
185 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; 173 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
186 device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass; 174 device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
@@ -194,7 +182,6 @@ nv50_identify(struct nvkm_device *device)
194 device->oclass[NVDEV_ENGINE_PM ] = gt215_pm_oclass; 182 device->oclass[NVDEV_ENGINE_PM ] = gt215_pm_oclass;
195 break; 183 break;
196 case 0xa8: 184 case 0xa8:
197 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
198 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; 185 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
199 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; 186 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
200 device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass; 187 device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
@@ -208,7 +195,6 @@ nv50_identify(struct nvkm_device *device)
208 device->oclass[NVDEV_ENGINE_PM ] = gt215_pm_oclass; 195 device->oclass[NVDEV_ENGINE_PM ] = gt215_pm_oclass;
209 break; 196 break;
210 case 0xaf: 197 case 0xaf:
211 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
212 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; 198 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
213 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; 199 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
214 device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass; 200 device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/user.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/user.c
index c5da091c058c..a9df61bf3780 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/user.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/user.c
@@ -118,14 +118,13 @@ static int
118nvkm_udevice_time(struct nvkm_udevice *udev, void *data, u32 size) 118nvkm_udevice_time(struct nvkm_udevice *udev, void *data, u32 size)
119{ 119{
120 struct nvkm_device *device = udev->device; 120 struct nvkm_device *device = udev->device;
121 struct nvkm_timer *tmr = device->timer;
122 union { 121 union {
123 struct nv_device_time_v0 v0; 122 struct nv_device_time_v0 v0;
124 } *args = data; 123 } *args = data;
125 int ret; 124 int ret;
126 125
127 if (nvif_unpack(args->v0, 0, 0, false)) { 126 if (nvif_unpack(args->v0, 0, 0, false)) {
128 args->v0.time = tmr->read(tmr); 127 args->v0.time = nvkm_timer_read(device->timer);
129 } 128 }
130 129
131 return ret; 130 return ret;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c
index 403d2c9aff3b..2a5bc9270fb9 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c
@@ -218,7 +218,7 @@ g84_gr_tlb_flush(struct nvkm_engine *engine)
218 spin_lock_irqsave(&gr->lock, flags); 218 spin_lock_irqsave(&gr->lock, flags);
219 nvkm_mask(device, 0x400500, 0x00000001, 0x00000000); 219 nvkm_mask(device, 0x400500, 0x00000001, 0x00000000);
220 220
221 start = tmr->read(tmr); 221 start = nvkm_timer_read(tmr);
222 do { 222 do {
223 idle = true; 223 idle = true;
224 224
@@ -237,7 +237,7 @@ g84_gr_tlb_flush(struct nvkm_engine *engine)
237 idle = false; 237 idle = false;
238 } 238 }
239 } while (!idle && 239 } while (!idle &&
240 !(timeout = tmr->read(tmr) - start > 2000000000)); 240 !(timeout = nvkm_timer_read(tmr) - start > 2000000000));
241 241
242 if (timeout) { 242 if (timeout) {
243 nvkm_error(subdev, "PGRAPH TLB flush idle timeout fail\n"); 243 nvkm_error(subdev, "PGRAPH TLB flush idle timeout fail\n");
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk20a.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk20a.c
index 860c8bc2b422..6689d0290a7e 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk20a.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk20a.c
@@ -124,6 +124,7 @@ gk20a_pmu_dvfs_work(struct nvkm_alarm *alarm)
124 struct nvkm_subdev *subdev = &pmu->base.subdev; 124 struct nvkm_subdev *subdev = &pmu->base.subdev;
125 struct nvkm_device *device = subdev->device; 125 struct nvkm_device *device = subdev->device;
126 struct nvkm_clk *clk = device->clk; 126 struct nvkm_clk *clk = device->clk;
127 struct nvkm_timer *tmr = device->timer;
127 struct nvkm_volt *volt = device->volt; 128 struct nvkm_volt *volt = device->volt;
128 u32 utilization = 0; 129 u32 utilization = 0;
129 int state, ret; 130 int state, ret;
@@ -162,14 +163,14 @@ gk20a_pmu_dvfs_work(struct nvkm_alarm *alarm)
162 163
163resched: 164resched:
164 gk20a_pmu_dvfs_reset_dev_status(pmu); 165 gk20a_pmu_dvfs_reset_dev_status(pmu);
165 nvkm_timer_alarm(pmu, 100000000, alarm); 166 nvkm_timer_alarm(tmr, 100000000, alarm);
166} 167}
167 168
168static int 169static int
169gk20a_pmu_fini(struct nvkm_subdev *subdev, bool suspend) 170gk20a_pmu_fini(struct nvkm_subdev *subdev, bool suspend)
170{ 171{
171 struct gk20a_pmu *pmu = gk20a_pmu(subdev); 172 struct gk20a_pmu *pmu = gk20a_pmu(subdev);
172 nvkm_timer_alarm_cancel(pmu, &pmu->alarm); 173 nvkm_timer_alarm_cancel(subdev->device->timer, &pmu->alarm);
173 return 0; 174 return 0;
174} 175}
175 176
@@ -190,7 +191,7 @@ gk20a_pmu_init(struct nvkm_subdev *subdev)
190 nvkm_wr32(device, 0x10a50c + (BUSY_SLOT * 0x10), 0x00000002); 191 nvkm_wr32(device, 0x10a50c + (BUSY_SLOT * 0x10), 0x00000002);
191 nvkm_wr32(device, 0x10a50c + (CLK_SLOT * 0x10), 0x00000003); 192 nvkm_wr32(device, 0x10a50c + (CLK_SLOT * 0x10), 0x00000003);
192 193
193 nvkm_timer_alarm(pmu, 2000000000, &pmu->alarm); 194 nvkm_timer_alarm(device->timer, 2000000000, &pmu->alarm);
194 return 0; 195 return 0;
195} 196}
196 197
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/base.c
index 304bdfc54445..949dc6101a58 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/base.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/base.c
@@ -102,7 +102,7 @@ nvkm_therm_update(struct nvkm_therm *therm, int mode)
102 102
103 switch (mode) { 103 switch (mode) {
104 case NVKM_THERM_CTRL_MANUAL: 104 case NVKM_THERM_CTRL_MANUAL:
105 tmr->alarm_cancel(tmr, &therm->alarm); 105 nvkm_timer_alarm_cancel(tmr, &therm->alarm);
106 duty = nvkm_therm_fan_get(therm); 106 duty = nvkm_therm_fan_get(therm);
107 if (duty < 0) 107 if (duty < 0)
108 duty = 100; 108 duty = 100;
@@ -126,12 +126,12 @@ nvkm_therm_update(struct nvkm_therm *therm, int mode)
126 break; 126 break;
127 case NVKM_THERM_CTRL_NONE: 127 case NVKM_THERM_CTRL_NONE:
128 default: 128 default:
129 tmr->alarm_cancel(tmr, &therm->alarm); 129 nvkm_timer_alarm_cancel(tmr, &therm->alarm);
130 poll = false; 130 poll = false;
131 } 131 }
132 132
133 if (list_empty(&therm->alarm.head) && poll) 133 if (list_empty(&therm->alarm.head) && poll)
134 tmr->alarm(tmr, 1000000000ULL, &therm->alarm); 134 nvkm_timer_alarm(tmr, 1000000000ULL, &therm->alarm);
135 spin_unlock_irqrestore(&therm->lock, flags); 135 spin_unlock_irqrestore(&therm->lock, flags);
136 136
137 if (duty >= 0) { 137 if (duty >= 0) {
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/fan.c b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/fan.c
index a2be18167770..91198d79393a 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/fan.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/fan.c
@@ -95,7 +95,7 @@ nvkm_fan_update(struct nvkm_fan *fan, bool immediate, int target)
95 else 95 else
96 delay = bump_period; 96 delay = bump_period;
97 97
98 tmr->alarm(tmr, delay * 1000 * 1000, &fan->alarm); 98 nvkm_timer_alarm(tmr, delay * 1000 * 1000, &fan->alarm);
99 } 99 }
100 100
101 return ret; 101 return ret;
@@ -139,7 +139,7 @@ nvkm_therm_fan_sense(struct nvkm_therm *therm)
139 * When the fan spins, it changes the value of GPIO FAN_SENSE. 139 * When the fan spins, it changes the value of GPIO FAN_SENSE.
140 * We get 4 changes (0 -> 1 -> 0 -> 1) per complete rotation. 140 * We get 4 changes (0 -> 1 -> 0 -> 1) per complete rotation.
141 */ 141 */
142 start = tmr->read(tmr); 142 start = nvkm_timer_read(tmr);
143 prev = nvkm_gpio_get(gpio, 0, therm->fan->tach.func, 143 prev = nvkm_gpio_get(gpio, 0, therm->fan->tach.func,
144 therm->fan->tach.line); 144 therm->fan->tach.line);
145 cycles = 0; 145 cycles = 0;
@@ -150,12 +150,12 @@ nvkm_therm_fan_sense(struct nvkm_therm *therm)
150 therm->fan->tach.line); 150 therm->fan->tach.line);
151 if (prev != cur) { 151 if (prev != cur) {
152 if (!start) 152 if (!start)
153 start = tmr->read(tmr); 153 start = nvkm_timer_read(tmr);
154 cycles++; 154 cycles++;
155 prev = cur; 155 prev = cur;
156 } 156 }
157 } while (cycles < 5 && tmr->read(tmr) - start < 250000000); 157 } while (cycles < 5 && nvkm_timer_read(tmr) - start < 250000000);
158 end = tmr->read(tmr); 158 end = nvkm_timer_read(tmr);
159 159
160 if (cycles == 5) { 160 if (cycles == 5) {
161 tach = (u64)60000000000ULL; 161 tach = (u64)60000000000ULL;
@@ -215,7 +215,7 @@ nvkm_therm_fan_fini(struct nvkm_therm *therm, bool suspend)
215{ 215{
216 struct nvkm_timer *tmr = therm->subdev.device->timer; 216 struct nvkm_timer *tmr = therm->subdev.device->timer;
217 if (suspend) 217 if (suspend)
218 tmr->alarm_cancel(tmr, &therm->fan->alarm); 218 nvkm_timer_alarm_cancel(tmr, &therm->fan->alarm);
219 return 0; 219 return 0;
220} 220}
221 221
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/fantog.c b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/fantog.c
index 64fe8f22336c..59701b7a6597 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/fantog.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/fantog.c
@@ -57,7 +57,7 @@ nvkm_fantog_update(struct nvkm_fantog *fan, int percent)
57 u64 next_change = (percent * fan->period_us) / 100; 57 u64 next_change = (percent * fan->period_us) / 100;
58 if (!duty) 58 if (!duty)
59 next_change = fan->period_us - next_change; 59 next_change = fan->period_us - next_change;
60 tmr->alarm(tmr, next_change * 1000, &fan->alarm); 60 nvkm_timer_alarm(tmr, next_change * 1000, &fan->alarm);
61 } 61 }
62 spin_unlock_irqrestore(&fan->lock, flags); 62 spin_unlock_irqrestore(&fan->lock, flags);
63} 63}
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/temp.c b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/temp.c
index 4ab7ef7da254..b9703c02d8ca 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/temp.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/temp.c
@@ -186,7 +186,7 @@ alarm_timer_callback(struct nvkm_alarm *alarm)
186 186
187 /* schedule the next poll in one second */ 187 /* schedule the next poll in one second */
188 if (therm->func->temp_get(therm) >= 0 && list_empty(&alarm->head)) 188 if (therm->func->temp_get(therm) >= 0 && list_empty(&alarm->head))
189 tmr->alarm(tmr, 1000000000ULL, alarm); 189 nvkm_timer_alarm(tmr, 1000000000ULL, alarm);
190} 190}
191 191
192void 192void
@@ -220,7 +220,7 @@ nvkm_therm_sensor_fini(struct nvkm_therm *therm, bool suspend)
220{ 220{
221 struct nvkm_timer *tmr = therm->subdev.device->timer; 221 struct nvkm_timer *tmr = therm->subdev.device->timer;
222 if (suspend) 222 if (suspend)
223 tmr->alarm_cancel(tmr, &therm->sensor.therm_poll_alarm); 223 nvkm_timer_alarm_cancel(tmr, &therm->sensor.therm_poll_alarm);
224 return 0; 224 return 0;
225} 225}
226 226
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/timer/Kbuild b/drivers/gpu/drm/nouveau/nvkm/subdev/timer/Kbuild
index d1d38b4ba30a..e436f0ffe3f4 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/timer/Kbuild
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/timer/Kbuild
@@ -1,3 +1,5 @@
1nvkm-y += nvkm/subdev/timer/base.o 1nvkm-y += nvkm/subdev/timer/base.o
2nvkm-y += nvkm/subdev/timer/nv04.o 2nvkm-y += nvkm/subdev/timer/nv04.o
3nvkm-y += nvkm/subdev/timer/nv40.o
4nvkm-y += nvkm/subdev/timer/nv41.o
3nvkm-y += nvkm/subdev/timer/gk20a.o 5nvkm-y += nvkm/subdev/timer/gk20a.o
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/timer/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/timer/base.c
index 4c34e2bd0487..d4dae1f12d62 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/timer/base.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/timer/base.c
@@ -21,18 +21,131 @@
21 * 21 *
22 * Authors: Ben Skeggs 22 * Authors: Ben Skeggs
23 */ 23 */
24#include <subdev/timer.h> 24#include "priv.h"
25
26u64
27nvkm_timer_read(struct nvkm_timer *tmr)
28{
29 return tmr->func->read(tmr);
30}
31
32void
33nvkm_timer_alarm_trigger(struct nvkm_timer *tmr)
34{
35 struct nvkm_alarm *alarm, *atemp;
36 unsigned long flags;
37 LIST_HEAD(exec);
38
39 /* move any due alarms off the pending list */
40 spin_lock_irqsave(&tmr->lock, flags);
41 list_for_each_entry_safe(alarm, atemp, &tmr->alarms, head) {
42 if (alarm->timestamp <= nvkm_timer_read(tmr))
43 list_move_tail(&alarm->head, &exec);
44 }
45
46 /* reschedule interrupt for next alarm time */
47 if (!list_empty(&tmr->alarms)) {
48 alarm = list_first_entry(&tmr->alarms, typeof(*alarm), head);
49 tmr->func->alarm_init(tmr, alarm->timestamp);
50 } else {
51 tmr->func->alarm_fini(tmr);
52 }
53 spin_unlock_irqrestore(&tmr->lock, flags);
54
55 /* execute any pending alarm handlers */
56 list_for_each_entry_safe(alarm, atemp, &exec, head) {
57 list_del_init(&alarm->head);
58 alarm->func(alarm);
59 }
60}
25 61
26void 62void
27nvkm_timer_alarm(void *obj, u32 nsec, struct nvkm_alarm *alarm) 63nvkm_timer_alarm(struct nvkm_timer *tmr, u32 nsec, struct nvkm_alarm *alarm)
28{ 64{
29 struct nvkm_timer *tmr = nvkm_timer(obj); 65 struct nvkm_alarm *list;
30 tmr->alarm(tmr, nsec, alarm); 66 unsigned long flags;
67
68 alarm->timestamp = nvkm_timer_read(tmr) + nsec;
69
70 /* append new alarm to list, in soonest-alarm-first order */
71 spin_lock_irqsave(&tmr->lock, flags);
72 if (!nsec) {
73 if (!list_empty(&alarm->head))
74 list_del(&alarm->head);
75 } else {
76 list_for_each_entry(list, &tmr->alarms, head) {
77 if (list->timestamp > alarm->timestamp)
78 break;
79 }
80 list_add_tail(&alarm->head, &list->head);
81 }
82 spin_unlock_irqrestore(&tmr->lock, flags);
83
84 /* process pending alarms */
85 nvkm_timer_alarm_trigger(tmr);
31} 86}
32 87
33void 88void
34nvkm_timer_alarm_cancel(void *obj, struct nvkm_alarm *alarm) 89nvkm_timer_alarm_cancel(struct nvkm_timer *tmr, struct nvkm_alarm *alarm)
90{
91 unsigned long flags;
92 spin_lock_irqsave(&tmr->lock, flags);
93 list_del_init(&alarm->head);
94 spin_unlock_irqrestore(&tmr->lock, flags);
95}
96
97static void
98nvkm_timer_intr(struct nvkm_subdev *subdev)
35{ 99{
36 struct nvkm_timer *tmr = nvkm_timer(obj); 100 struct nvkm_timer *tmr = nvkm_timer(subdev);
37 tmr->alarm_cancel(tmr, alarm); 101 tmr->func->intr(tmr);
102}
103
104static int
105nvkm_timer_fini(struct nvkm_subdev *subdev, bool suspend)
106{
107 struct nvkm_timer *tmr = nvkm_timer(subdev);
108 tmr->func->alarm_fini(tmr);
109 return 0;
110}
111
112static int
113nvkm_timer_init(struct nvkm_subdev *subdev)
114{
115 struct nvkm_timer *tmr = nvkm_timer(subdev);
116 if (tmr->func->init)
117 tmr->func->init(tmr);
118 tmr->func->time(tmr, ktime_to_ns(ktime_get()));
119 nvkm_timer_alarm_trigger(tmr);
120 return 0;
121}
122
123static void *
124nvkm_timer_dtor(struct nvkm_subdev *subdev)
125{
126 return nvkm_timer(subdev);
127}
128
129static const struct nvkm_subdev_func
130nvkm_timer = {
131 .dtor = nvkm_timer_dtor,
132 .init = nvkm_timer_init,
133 .fini = nvkm_timer_fini,
134 .intr = nvkm_timer_intr,
135};
136
137int
138nvkm_timer_new_(const struct nvkm_timer_func *func, struct nvkm_device *device,
139 int index, struct nvkm_timer **ptmr)
140{
141 struct nvkm_timer *tmr;
142
143 if (!(tmr = *ptmr = kzalloc(sizeof(*tmr), GFP_KERNEL)))
144 return -ENOMEM;
145
146 nvkm_subdev_ctor(&nvkm_timer, device, index, 0, &tmr->subdev);
147 tmr->func = func;
148 INIT_LIST_HEAD(&tmr->alarms);
149 spin_lock_init(&tmr->lock);
150 return 0;
38} 151}
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/timer/gk20a.c b/drivers/gpu/drm/nouveau/nvkm/subdev/timer/gk20a.c
index 46bfa10b5b97..9ed5f64912d0 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/timer/gk20a.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/timer/gk20a.c
@@ -21,38 +21,19 @@
21 * 21 *
22 * Authors: Ben Skeggs 22 * Authors: Ben Skeggs
23 */ 23 */
24#include "nv04.h" 24#include "priv.h"
25 25
26static int 26static const struct nvkm_timer_func
27gk20a_timer_init(struct nvkm_object *object) 27gk20a_timer = {
28{ 28 .intr = nv04_timer_intr,
29 struct nv04_timer *tmr = (void *)object; 29 .read = nv04_timer_read,
30 struct nvkm_subdev *subdev = &tmr->base.subdev; 30 .time = nv04_timer_time,
31 struct nvkm_device *device = subdev->device; 31 .alarm_init = nv04_timer_alarm_init,
32 u32 hi = upper_32_bits(tmr->suspend_time); 32 .alarm_fini = nv04_timer_alarm_fini,
33 u32 lo = lower_32_bits(tmr->suspend_time); 33};
34 int ret;
35
36 ret = nvkm_timer_init(&tmr->base);
37 if (ret)
38 return ret;
39
40 nvkm_debug(subdev, "time low : %08x\n", lo);
41 nvkm_debug(subdev, "time high : %08x\n", hi);
42 34
43 /* restore the time before suspend */ 35int
44 nvkm_wr32(device, NV04_PTIMER_TIME_1, hi); 36gk20a_timer_new(struct nvkm_device *device, int index, struct nvkm_timer **ptmr)
45 nvkm_wr32(device, NV04_PTIMER_TIME_0, lo); 37{
46 return 0; 38 return nvkm_timer_new_(&gk20a_timer, device, index, ptmr);
47} 39}
48
49struct nvkm_oclass
50gk20a_timer_oclass = {
51 .handle = NV_SUBDEV(TIMER, 0xff),
52 .ofuncs = &(struct nvkm_ofuncs) {
53 .ctor = nv04_timer_ctor,
54 .dtor = nv04_timer_dtor,
55 .init = gk20a_timer_init,
56 .fini = nv04_timer_fini,
57 }
58};
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/timer/nv04.c b/drivers/gpu/drm/nouveau/nvkm/subdev/timer/nv04.c
index 8d45753f65ac..7b9ce87f0617 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/timer/nv04.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/timer/nv04.c
@@ -21,9 +21,25 @@
21 * 21 *
22 * Authors: Ben Skeggs 22 * Authors: Ben Skeggs
23 */ 23 */
24#include "nv04.h" 24#include "priv.h"
25#include "regsnv04.h"
25 26
26static u64 27void
28nv04_timer_time(struct nvkm_timer *tmr, u64 time)
29{
30 struct nvkm_subdev *subdev = &tmr->subdev;
31 struct nvkm_device *device = subdev->device;
32 u32 hi = upper_32_bits(time);
33 u32 lo = lower_32_bits(time);
34
35 nvkm_debug(subdev, "time low : %08x\n", lo);
36 nvkm_debug(subdev, "time high : %08x\n", hi);
37
38 nvkm_wr32(device, NV04_PTIMER_TIME_1, hi);
39 nvkm_wr32(device, NV04_PTIMER_TIME_0, lo);
40}
41
42u64
27nv04_timer_read(struct nvkm_timer *tmr) 43nv04_timer_read(struct nvkm_timer *tmr)
28{ 44{
29 struct nvkm_device *device = tmr->subdev.device; 45 struct nvkm_device *device = tmr->subdev.device;
@@ -37,85 +53,30 @@ nv04_timer_read(struct nvkm_timer *tmr)
37 return ((u64)hi << 32 | lo); 53 return ((u64)hi << 32 | lo);
38} 54}
39 55
40static void 56void
41nv04_timer_alarm_trigger(struct nvkm_timer *obj) 57nv04_timer_alarm_fini(struct nvkm_timer *tmr)
42{
43 struct nv04_timer *tmr = container_of(obj, typeof(*tmr), base);
44 struct nvkm_device *device = tmr->base.subdev.device;
45 struct nvkm_alarm *alarm, *atemp;
46 unsigned long flags;
47 LIST_HEAD(exec);
48
49 /* move any due alarms off the pending list */
50 spin_lock_irqsave(&tmr->lock, flags);
51 list_for_each_entry_safe(alarm, atemp, &tmr->alarms, head) {
52 if (alarm->timestamp <= tmr->base.read(&tmr->base))
53 list_move_tail(&alarm->head, &exec);
54 }
55
56 /* reschedule interrupt for next alarm time */
57 if (!list_empty(&tmr->alarms)) {
58 alarm = list_first_entry(&tmr->alarms, typeof(*alarm), head);
59 nvkm_wr32(device, NV04_PTIMER_ALARM_0, alarm->timestamp);
60 nvkm_wr32(device, NV04_PTIMER_INTR_EN_0, 0x00000001);
61 } else {
62 nvkm_wr32(device, NV04_PTIMER_INTR_EN_0, 0x00000000);
63 }
64 spin_unlock_irqrestore(&tmr->lock, flags);
65
66 /* execute any pending alarm handlers */
67 list_for_each_entry_safe(alarm, atemp, &exec, head) {
68 list_del_init(&alarm->head);
69 alarm->func(alarm);
70 }
71}
72
73static void
74nv04_timer_alarm(struct nvkm_timer *obj, u64 time, struct nvkm_alarm *alarm)
75{ 58{
76 struct nv04_timer *tmr = container_of(obj, typeof(*tmr), base); 59 struct nvkm_device *device = tmr->subdev.device;
77 struct nvkm_alarm *list; 60 nvkm_wr32(device, NV04_PTIMER_INTR_EN_0, 0x00000000);
78 unsigned long flags;
79
80 alarm->timestamp = tmr->base.read(&tmr->base) + time;
81
82 /* append new alarm to list, in soonest-alarm-first order */
83 spin_lock_irqsave(&tmr->lock, flags);
84 if (!time) {
85 if (!list_empty(&alarm->head))
86 list_del(&alarm->head);
87 } else {
88 list_for_each_entry(list, &tmr->alarms, head) {
89 if (list->timestamp > alarm->timestamp)
90 break;
91 }
92 list_add_tail(&alarm->head, &list->head);
93 }
94 spin_unlock_irqrestore(&tmr->lock, flags);
95
96 /* process pending alarms */
97 nv04_timer_alarm_trigger(&tmr->base);
98} 61}
99 62
100static void 63void
101nv04_timer_alarm_cancel(struct nvkm_timer *obj, struct nvkm_alarm *alarm) 64nv04_timer_alarm_init(struct nvkm_timer *tmr, u32 time)
102{ 65{
103 struct nv04_timer *tmr = container_of(obj, typeof(*tmr), base); 66 struct nvkm_device *device = tmr->subdev.device;
104 unsigned long flags; 67 nvkm_wr32(device, NV04_PTIMER_ALARM_0, time);
105 spin_lock_irqsave(&tmr->lock, flags); 68 nvkm_wr32(device, NV04_PTIMER_INTR_EN_0, 0x00000001);
106 list_del_init(&alarm->head);
107 spin_unlock_irqrestore(&tmr->lock, flags);
108} 69}
109 70
110static void 71void
111nv04_timer_intr(struct nvkm_subdev *subdev) 72nv04_timer_intr(struct nvkm_timer *tmr)
112{ 73{
113 struct nv04_timer *tmr = (void *)subdev; 74 struct nvkm_subdev *subdev = &tmr->subdev;
114 struct nvkm_device *device = tmr->base.subdev.device; 75 struct nvkm_device *device = subdev->device;
115 u32 stat = nvkm_rd32(device, NV04_PTIMER_INTR_0); 76 u32 stat = nvkm_rd32(device, NV04_PTIMER_INTR_0);
116 77
117 if (stat & 0x00000001) { 78 if (stat & 0x00000001) {
118 nv04_timer_alarm_trigger(&tmr->base); 79 nvkm_timer_alarm_trigger(tmr);
119 nvkm_wr32(device, NV04_PTIMER_INTR_0, 0x00000001); 80 nvkm_wr32(device, NV04_PTIMER_INTR_0, 0x00000001);
120 stat &= ~0x00000001; 81 stat &= ~0x00000001;
121 } 82 }
@@ -126,62 +87,26 @@ nv04_timer_intr(struct nvkm_subdev *subdev)
126 } 87 }
127} 88}
128 89
129int 90static void
130nv04_timer_fini(struct nvkm_object *object, bool suspend) 91nv04_timer_init(struct nvkm_timer *tmr)
131{
132 struct nv04_timer *tmr = (void *)object;
133 struct nvkm_device *device = tmr->base.subdev.device;
134 if (suspend)
135 tmr->suspend_time = nv04_timer_read(&tmr->base);
136 nvkm_wr32(device, NV04_PTIMER_INTR_EN_0, 0x00000000);
137 return nvkm_timer_fini(&tmr->base, suspend);
138}
139
140static int
141nv04_timer_init(struct nvkm_object *object)
142{ 92{
143 struct nv04_timer *tmr = (void *)object; 93 struct nvkm_subdev *subdev = &tmr->subdev;
144 struct nvkm_subdev *subdev = &tmr->base.subdev;
145 struct nvkm_device *device = subdev->device; 94 struct nvkm_device *device = subdev->device;
146 u32 m = 1, f, n, d, lo, hi; 95 u32 f = 0; /*XXX: nvclk */
147 int ret; 96 u32 n, d;
148
149 ret = nvkm_timer_init(&tmr->base);
150 if (ret)
151 return ret;
152 97
153 /* aim for 31.25MHz, which gives us nanosecond timestamps */ 98 /* aim for 31.25MHz, which gives us nanosecond timestamps */
154 d = 1000000 / 32; 99 d = 1000000 / 32;
155 100 n = f;
156 /* determine base clock for timer source */ 101
157#if 0 /*XXX*/ 102 if (!f) {
158 if (device->chipset < 0x40) { 103 n = nvkm_rd32(device, NV04_PTIMER_NUMERATOR);
159 n = nvkm_hw_get_clock(device, PLL_CORE); 104 d = nvkm_rd32(device, NV04_PTIMER_DENOMINATOR);
160 } else 105 if (!n || !d) {
161#endif 106 n = 1;
162 if (device->chipset <= 0x40) { 107 d = 1;
163 /*XXX: figure this out */
164 f = -1;
165 n = 0;
166 } else {
167 f = device->crystal;
168 n = f;
169 while (n < (d * 2)) {
170 n += (n / m);
171 m++;
172 } 108 }
173
174 nvkm_wr32(device, 0x009220, m - 1);
175 }
176
177 if (!n) {
178 nvkm_warn(subdev, "unknown input clock freq\n"); 109 nvkm_warn(subdev, "unknown input clock freq\n");
179 if (!nvkm_rd32(device, NV04_PTIMER_NUMERATOR) ||
180 !nvkm_rd32(device, NV04_PTIMER_DENOMINATOR)) {
181 nvkm_wr32(device, NV04_PTIMER_NUMERATOR, 1);
182 nvkm_wr32(device, NV04_PTIMER_DENOMINATOR, 1);
183 }
184 return 0;
185 } 110 }
186 111
187 /* reduce ratio to acceptable values */ 112 /* reduce ratio to acceptable values */
@@ -200,65 +125,27 @@ nv04_timer_init(struct nvkm_object *object)
200 d >>= 1; 125 d >>= 1;
201 } 126 }
202 127
203 /* restore the time before suspend */
204 lo = tmr->suspend_time;
205 hi = (tmr->suspend_time >> 32);
206
207 nvkm_debug(subdev, "input frequency : %dHz\n", f); 128 nvkm_debug(subdev, "input frequency : %dHz\n", f);
208 nvkm_debug(subdev, "input multiplier: %d\n", m);
209 nvkm_debug(subdev, "numerator : %08x\n", n); 129 nvkm_debug(subdev, "numerator : %08x\n", n);
210 nvkm_debug(subdev, "denominator : %08x\n", d); 130 nvkm_debug(subdev, "denominator : %08x\n", d);
211 nvkm_debug(subdev, "timer frequency : %dHz\n", (f * m) * d / n); 131 nvkm_debug(subdev, "timer frequency : %dHz\n", f * d / n);
212 nvkm_debug(subdev, "time low : %08x\n", lo);
213 nvkm_debug(subdev, "time high : %08x\n", hi);
214 132
215 nvkm_wr32(device, NV04_PTIMER_NUMERATOR, n); 133 nvkm_wr32(device, NV04_PTIMER_NUMERATOR, n);
216 nvkm_wr32(device, NV04_PTIMER_DENOMINATOR, d); 134 nvkm_wr32(device, NV04_PTIMER_DENOMINATOR, d);
217 nvkm_wr32(device, NV04_PTIMER_INTR_0, 0xffffffff);
218 nvkm_wr32(device, NV04_PTIMER_INTR_EN_0, 0x00000000);
219 nvkm_wr32(device, NV04_PTIMER_TIME_1, hi);
220 nvkm_wr32(device, NV04_PTIMER_TIME_0, lo);
221 return 0;
222} 135}
223 136
224void 137static const struct nvkm_timer_func
225nv04_timer_dtor(struct nvkm_object *object) 138nv04_timer = {
226{ 139 .init = nv04_timer_init,
227 struct nv04_timer *tmr = (void *)object; 140 .intr = nv04_timer_intr,
228 return nvkm_timer_destroy(&tmr->base); 141 .read = nv04_timer_read,
229} 142 .time = nv04_timer_time,
143 .alarm_init = nv04_timer_alarm_init,
144 .alarm_fini = nv04_timer_alarm_fini,
145};
230 146
231int 147int
232nv04_timer_ctor(struct nvkm_object *parent, struct nvkm_object *engine, 148nv04_timer_new(struct nvkm_device *device, int index, struct nvkm_timer **ptmr)
233 struct nvkm_oclass *oclass, void *data, u32 size,
234 struct nvkm_object **pobject)
235{ 149{
236 struct nv04_timer *tmr; 150 return nvkm_timer_new_(&nv04_timer, device, index, ptmr);
237 int ret;
238
239 ret = nvkm_timer_create(parent, engine, oclass, &tmr);
240 *pobject = nv_object(tmr);
241 if (ret)
242 return ret;
243
244 tmr->base.subdev.intr = nv04_timer_intr;
245 tmr->base.read = nv04_timer_read;
246 tmr->base.alarm = nv04_timer_alarm;
247 tmr->base.alarm_cancel = nv04_timer_alarm_cancel;
248 tmr->suspend_time = 0;
249
250 INIT_LIST_HEAD(&tmr->alarms);
251 spin_lock_init(&tmr->lock);
252 return 0;
253} 151}
254
255struct nvkm_oclass
256nv04_timer_oclass = {
257 .handle = NV_SUBDEV(TIMER, 0x04),
258 .ofuncs = &(struct nvkm_ofuncs) {
259 .ctor = nv04_timer_ctor,
260 .dtor = nv04_timer_dtor,
261 .init = nv04_timer_init,
262 .fini = nv04_timer_fini,
263 }
264};
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/timer/nv04.h b/drivers/gpu/drm/nouveau/nvkm/subdev/timer/nv04.h
deleted file mode 100644
index 1bc0d7c073ef..000000000000
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/timer/nv04.h
+++ /dev/null
@@ -1,25 +0,0 @@
1#ifndef __NVKM_TIMER_NV04_H__
2#define __NVKM_TIMER_NV04_H__
3#include "priv.h"
4
5#define NV04_PTIMER_INTR_0 0x009100
6#define NV04_PTIMER_INTR_EN_0 0x009140
7#define NV04_PTIMER_NUMERATOR 0x009200
8#define NV04_PTIMER_DENOMINATOR 0x009210
9#define NV04_PTIMER_TIME_0 0x009400
10#define NV04_PTIMER_TIME_1 0x009410
11#define NV04_PTIMER_ALARM_0 0x009420
12
13struct nv04_timer {
14 struct nvkm_timer base;
15 struct list_head alarms;
16 spinlock_t lock;
17 u64 suspend_time;
18};
19
20int nv04_timer_ctor(struct nvkm_object *, struct nvkm_object *,
21 struct nvkm_oclass *, void *, u32,
22 struct nvkm_object **);
23void nv04_timer_dtor(struct nvkm_object *);
24int nv04_timer_fini(struct nvkm_object *, bool);
25#endif
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/timer/nv40.c b/drivers/gpu/drm/nouveau/nvkm/subdev/timer/nv40.c
new file mode 100644
index 000000000000..bb99a152f26e
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/timer/nv40.c
@@ -0,0 +1,88 @@
1/*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24#include "priv.h"
25#include "regsnv04.h"
26
27static void
28nv40_timer_init(struct nvkm_timer *tmr)
29{
30 struct nvkm_subdev *subdev = &tmr->subdev;
31 struct nvkm_device *device = subdev->device;
32 u32 f = 0; /*XXX: figure this out */
33 u32 n, d;
34
35 /* aim for 31.25MHz, which gives us nanosecond timestamps */
36 d = 1000000 / 32;
37 n = f;
38
39 if (!f) {
40 n = nvkm_rd32(device, NV04_PTIMER_NUMERATOR);
41 d = nvkm_rd32(device, NV04_PTIMER_DENOMINATOR);
42 if (!n || !d) {
43 n = 1;
44 d = 1;
45 }
46 nvkm_warn(subdev, "unknown input clock freq\n");
47 }
48
49 /* reduce ratio to acceptable values */
50 while (((n % 5) == 0) && ((d % 5) == 0)) {
51 n /= 5;
52 d /= 5;
53 }
54
55 while (((n % 2) == 0) && ((d % 2) == 0)) {
56 n /= 2;
57 d /= 2;
58 }
59
60 while (n > 0xffff || d > 0xffff) {
61 n >>= 1;
62 d >>= 1;
63 }
64
65 nvkm_debug(subdev, "input frequency : %dHz\n", f);
66 nvkm_debug(subdev, "numerator : %08x\n", n);
67 nvkm_debug(subdev, "denominator : %08x\n", d);
68 nvkm_debug(subdev, "timer frequency : %dHz\n", f * d / n);
69
70 nvkm_wr32(device, NV04_PTIMER_NUMERATOR, n);
71 nvkm_wr32(device, NV04_PTIMER_DENOMINATOR, d);
72}
73
74static const struct nvkm_timer_func
75nv40_timer = {
76 .init = nv40_timer_init,
77 .intr = nv04_timer_intr,
78 .read = nv04_timer_read,
79 .time = nv04_timer_time,
80 .alarm_init = nv04_timer_alarm_init,
81 .alarm_fini = nv04_timer_alarm_fini,
82};
83
84int
85nv40_timer_new(struct nvkm_device *device, int index, struct nvkm_timer **ptmr)
86{
87 return nvkm_timer_new_(&nv40_timer, device, index, ptmr);
88}
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/timer/nv41.c b/drivers/gpu/drm/nouveau/nvkm/subdev/timer/nv41.c
new file mode 100644
index 000000000000..3cf9ec1b1b57
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/timer/nv41.c
@@ -0,0 +1,85 @@
1/*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24#include "priv.h"
25#include "regsnv04.h"
26
27static void
28nv41_timer_init(struct nvkm_timer *tmr)
29{
30 struct nvkm_subdev *subdev = &tmr->subdev;
31 struct nvkm_device *device = subdev->device;
32 u32 f = device->crystal;
33 u32 m = 1, n, d;
34
35 /* aim for 31.25MHz, which gives us nanosecond timestamps */
36 d = 1000000 / 32;
37 n = f;
38
39 while (n < (d * 2)) {
40 n += (n / m);
41 m++;
42 }
43
44 /* reduce ratio to acceptable values */
45 while (((n % 5) == 0) && ((d % 5) == 0)) {
46 n /= 5;
47 d /= 5;
48 }
49
50 while (((n % 2) == 0) && ((d % 2) == 0)) {
51 n /= 2;
52 d /= 2;
53 }
54
55 while (n > 0xffff || d > 0xffff) {
56 n >>= 1;
57 d >>= 1;
58 }
59
60 nvkm_debug(subdev, "input frequency : %dHz\n", f);
61 nvkm_debug(subdev, "input multiplier: %d\n", m);
62 nvkm_debug(subdev, "numerator : %08x\n", n);
63 nvkm_debug(subdev, "denominator : %08x\n", d);
64 nvkm_debug(subdev, "timer frequency : %dHz\n", (f * m) * d / n);
65
66 nvkm_wr32(device, 0x009220, m - 1);
67 nvkm_wr32(device, NV04_PTIMER_NUMERATOR, n);
68 nvkm_wr32(device, NV04_PTIMER_DENOMINATOR, d);
69}
70
71static const struct nvkm_timer_func
72nv41_timer = {
73 .init = nv41_timer_init,
74 .intr = nv04_timer_intr,
75 .read = nv04_timer_read,
76 .time = nv04_timer_time,
77 .alarm_init = nv04_timer_alarm_init,
78 .alarm_fini = nv04_timer_alarm_fini,
79};
80
81int
82nv41_timer_new(struct nvkm_device *device, int index, struct nvkm_timer **ptmr)
83{
84 return nvkm_timer_new_(&nv41_timer, device, index, ptmr);
85}
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/timer/priv.h b/drivers/gpu/drm/nouveau/nvkm/subdev/timer/priv.h
index 08e29a3da188..f820ca2aeda4 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/timer/priv.h
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/timer/priv.h
@@ -1,4 +1,26 @@
1#ifndef __NVKM_TIMER_PRIV_H__ 1#ifndef __NVKM_TIMER_PRIV_H__
2#define __NVKM_TIMER_PRIV_H__ 2#define __NVKM_TIMER_PRIV_H__
3#define nvkm_timer(p) container_of((p), struct nvkm_timer, subdev)
3#include <subdev/timer.h> 4#include <subdev/timer.h>
5
6int nvkm_timer_new_(const struct nvkm_timer_func *, struct nvkm_device *,
7 int index, struct nvkm_timer **);
8
9struct nvkm_timer_func {
10 void (*init)(struct nvkm_timer *);
11 void (*intr)(struct nvkm_timer *);
12 u64 (*read)(struct nvkm_timer *);
13 void (*time)(struct nvkm_timer *, u64 time);
14 void (*alarm_init)(struct nvkm_timer *, u32 time);
15 void (*alarm_fini)(struct nvkm_timer *);
16};
17
18void nvkm_timer_alarm_trigger(struct nvkm_timer *);
19
20void nv04_timer_fini(struct nvkm_timer *);
21void nv04_timer_intr(struct nvkm_timer *);
22void nv04_timer_time(struct nvkm_timer *, u64);
23u64 nv04_timer_read(struct nvkm_timer *);
24void nv04_timer_alarm_init(struct nvkm_timer *, u32);
25void nv04_timer_alarm_fini(struct nvkm_timer *);
4#endif 26#endif
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/timer/regsnv04.h b/drivers/gpu/drm/nouveau/nvkm/subdev/timer/regsnv04.h
new file mode 100644
index 000000000000..10bef85b485e
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/timer/regsnv04.h
@@ -0,0 +1,7 @@
1#define NV04_PTIMER_INTR_0 0x009100
2#define NV04_PTIMER_INTR_EN_0 0x009140
3#define NV04_PTIMER_NUMERATOR 0x009200
4#define NV04_PTIMER_DENOMINATOR 0x009210
5#define NV04_PTIMER_TIME_0 0x009400
6#define NV04_PTIMER_TIME_1 0x009410
7#define NV04_PTIMER_ALARM_0 0x009420
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-15 02:05:53 -0400