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authorArnd Bergmann <arnd@arndb.de>2017-06-23 08:06:00 -0400
committerArnd Bergmann <arnd@arndb.de>2017-06-23 08:06:00 -0400
commit30edd98b3b0edd0715ef736fd54d08a15cbc9462 (patch)
tree32302c6cf6b0985a12b9546c8b12e8989d47c523
parentefd8b0ddafcc6ab010796d252ac54bb0515117fd (diff)
parent6ef84a827c37547504514a80bdb35f74a67df5a3 (diff)
Merge tag 'mvebu-dt64-4.13-2' of git://git.infradead.org/linux-mvebu into next/dt64
Pull "mvebu dt64 for 4.13 (part 2)" from Gregory CLEMENT: - use new clock binding for Armada 7K/8K - add pinctrl on Armada 7K/8K - add GPIO on Armada 7K/8K - switch from GIC to ICU on CP110 (Armada 7K/8K) - enable the mdio node on the mcbin (Armada 8K based board) * tag 'mvebu-dt64-4.13-2' of git://git.infradead.org/linux-mvebu: arm64: dts: marvell: enable GICP and ICU on Armada 7K/8K arm64: dts: marvell: add gpio support for Armada 7K/8K arm64: dts: marvell: add pinctrl support for Armada 7K/8K arm64: dts: marvell: use new binding for the system controller on cp110 arm64: dts: marvell: remove *-clock-output-names on cp110 arm64: dts: marvell: use new bindings for xor clocks on ap806 arm64: dts: marvell: mcbin: enable the mdio node
Diffstat
-rw-r--r--arch/arm64/boot/dts/marvell/armada-7020.dtsi2
-rw-r--r--arch/arm64/boot/dts/marvell/armada-7040.dtsi2
-rw-r--r--arch/arm64/boot/dts/marvell/armada-70x0.dtsi68
-rw-r--r--arch/arm64/boot/dts/marvell/armada-8020.dtsi3
-rw-r--r--arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts2
-rw-r--r--arch/arm64/boot/dts/marvell/armada-8040.dtsi3
-rw-r--r--arch/arm64/boot/dts/marvell/armada-80x0.dtsi76
-rw-r--r--arch/arm64/boot/dts/marvell/armada-ap806.dtsi29
-rw-r--r--arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi136
-rw-r--r--arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi131
10 files changed, 329 insertions, 123 deletions
diff --git a/arch/arm64/boot/dts/marvell/armada-7020.dtsi b/arch/arm64/boot/dts/marvell/armada-7020.dtsi
index 975e73302753..4ab012991d9d 100644
--- a/arch/arm64/boot/dts/marvell/armada-7020.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-7020.dtsi
@@ -46,7 +46,7 @@
46 */ 46 */
47 47
48#include "armada-ap806-dual.dtsi" 48#include "armada-ap806-dual.dtsi"
49#include "armada-cp110-master.dtsi" 49#include "armada-70x0.dtsi"
50 50
51/ { 51/ {
52 model = "Marvell Armada 7020"; 52 model = "Marvell Armada 7020";
diff --git a/arch/arm64/boot/dts/marvell/armada-7040.dtsi b/arch/arm64/boot/dts/marvell/armada-7040.dtsi
index 78d995d62707..cbe460b8fc00 100644
--- a/arch/arm64/boot/dts/marvell/armada-7040.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-7040.dtsi
@@ -46,7 +46,7 @@
46 */ 46 */
47 47
48#include "armada-ap806-quad.dtsi" 48#include "armada-ap806-quad.dtsi"
49#include "armada-cp110-master.dtsi" 49#include "armada-70x0.dtsi"
50 50
51/ { 51/ {
52 model = "Marvell Armada 7040"; 52 model = "Marvell Armada 7040";
diff --git a/arch/arm64/boot/dts/marvell/armada-70x0.dtsi b/arch/arm64/boot/dts/marvell/armada-70x0.dtsi
new file mode 100644
index 000000000000..860b6ae9dcc5
--- /dev/null
+++ b/arch/arm64/boot/dts/marvell/armada-70x0.dtsi
@@ -0,0 +1,68 @@
1/*
2 * Copyright (C) 2017 Marvell Technology Group Ltd.
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPLv2 or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
13 *
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * Or, alternatively,
20 *
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
28 * conditions:
29 *
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
32 *
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
41 */
42
43/*
44 * Device Tree file for the Armada 70x0 SoC
45 */
46
47#include "armada-cp110-master.dtsi"
48
49/ {
50 aliases {
51 gpio1 = &cpm_gpio1;
52 gpio2 = &cpm_gpio2;
53 };
54};
55
56&cpm_gpio1 {
57 status = "okay";
58};
59
60&cpm_gpio2 {
61 status = "okay";
62};
63
64&cpm_syscon0 {
65 cpm_pinctrl: pinctrl {
66 compatible = "marvell,armada-7k-pinctrl";
67 };
68};
diff --git a/arch/arm64/boot/dts/marvell/armada-8020.dtsi b/arch/arm64/boot/dts/marvell/armada-8020.dtsi
index 7c08f1f28d9e..0ba0bc942598 100644
--- a/arch/arm64/boot/dts/marvell/armada-8020.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-8020.dtsi
@@ -46,8 +46,7 @@
46 */ 46 */
47 47
48#include "armada-ap806-dual.dtsi" 48#include "armada-ap806-dual.dtsi"
49#include "armada-cp110-master.dtsi" 49#include "armada-80x0.dtsi"
50#include "armada-cp110-slave.dtsi"
51 50
52/ { 51/ {
53 model = "Marvell Armada 8020"; 52 model = "Marvell Armada 8020";
diff --git a/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts b/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts
index fe56efcfcefe..4968e731de61 100644
--- a/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts
+++ b/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts
@@ -116,6 +116,8 @@
116}; 116};
117 117
118&cpm_mdio { 118&cpm_mdio {
119 status = "okay";
120
119 ge_phy: ethernet-phy@0 { 121 ge_phy: ethernet-phy@0 {
120 reg = <0>; 122 reg = <0>;
121 }; 123 };
diff --git a/arch/arm64/boot/dts/marvell/armada-8040.dtsi b/arch/arm64/boot/dts/marvell/armada-8040.dtsi
index 33813a75bc30..60fe84f5cbcc 100644
--- a/arch/arm64/boot/dts/marvell/armada-8040.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-8040.dtsi
@@ -46,8 +46,7 @@
46 */ 46 */
47 47
48#include "armada-ap806-quad.dtsi" 48#include "armada-ap806-quad.dtsi"
49#include "armada-cp110-master.dtsi" 49#include "armada-80x0.dtsi"
50#include "armada-cp110-slave.dtsi"
51 50
52/ { 51/ {
53 model = "Marvell Armada 8040"; 52 model = "Marvell Armada 8040";
diff --git a/arch/arm64/boot/dts/marvell/armada-80x0.dtsi b/arch/arm64/boot/dts/marvell/armada-80x0.dtsi
new file mode 100644
index 000000000000..666ebe96ba0d
--- /dev/null
+++ b/arch/arm64/boot/dts/marvell/armada-80x0.dtsi
@@ -0,0 +1,76 @@
1/*
2 * Copyright (C) 2017 Marvell Technology Group Ltd.
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPLv2 or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
13 *
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * Or, alternatively,
20 *
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
28 * conditions:
29 *
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
32 *
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
41 */
42
43/*
44 * Device Tree file for the Armada 80x0 SoC family
45 */
46
47#include "armada-cp110-master.dtsi"
48#include "armada-cp110-slave.dtsi"
49
50/ {
51 aliases {
52 gpio1 = &cps_gpio1;
53 gpio2 = &cpm_gpio2;
54 };
55};
56
57/* The 80x0 has two CP blocks, but uses only one block from each. */
58&cps_gpio1 {
59 status = "okay";
60};
61
62&cpm_gpio2 {
63 status = "okay";
64};
65
66&cpm_syscon0 {
67 cpm_pinctrl: pinctrl {
68 compatible = "marvell,armada-8k-cpm-pinctrl";
69 };
70};
71
72&cps_syscon0 {
73 cps_pinctrl: pinctrl {
74 compatible = "marvell,armada-8k-cps-pinctrl";
75 };
76};
diff --git a/arch/arm64/boot/dts/marvell/armada-ap806.dtsi b/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
index ff1964d314de..1eb1f1e9aac4 100644
--- a/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
@@ -57,6 +57,7 @@
57 aliases { 57 aliases {
58 serial0 = &uart0; 58 serial0 = &uart0;
59 serial1 = &uart1; 59 serial1 = &uart1;
60 gpio0 = &ap_gpio;
60 }; 61 };
61 62
62 psci { 63 psci {
@@ -146,6 +147,13 @@
146 marvell,spi-base = <128>, <136>, <144>, <152>; 147 marvell,spi-base = <128>, <136>, <144>, <152>;
147 }; 148 };
148 149
150 gicp: gicp@3f0040 {
151 compatible = "marvell,ap806-gicp";
152 reg = <0x3f0040 0x10>;
153 marvell,spi-ranges = <64 64>, <288 64>;
154 msi-controller;
155 };
156
149 pic: interrupt-controller@3f0100 { 157 pic: interrupt-controller@3f0100 {
150 compatible = "marvell,armada-8k-pic"; 158 compatible = "marvell,armada-8k-pic";
151 reg = <0x3f0100 0x10>; 159 reg = <0x3f0100 0x10>;
@@ -159,7 +167,7 @@
159 reg = <0x400000 0x1000>, 167 reg = <0x400000 0x1000>,
160 <0x410000 0x1000>; 168 <0x410000 0x1000>;
161 msi-parent = <&gic_v2m0>; 169 msi-parent = <&gic_v2m0>;
162 clocks = <&ap_syscon 3>; 170 clocks = <&ap_clk 3>;
163 dma-coherent; 171 dma-coherent;
164 }; 172 };
165 173
@@ -168,7 +176,7 @@
168 reg = <0x420000 0x1000>, 176 reg = <0x420000 0x1000>,
169 <0x430000 0x1000>; 177 <0x430000 0x1000>;
170 msi-parent = <&gic_v2m0>; 178 msi-parent = <&gic_v2m0>;
171 clocks = <&ap_syscon 3>; 179 clocks = <&ap_clk 3>;
172 dma-coherent; 180 dma-coherent;
173 }; 181 };
174 182
@@ -177,7 +185,7 @@
177 reg = <0x440000 0x1000>, 185 reg = <0x440000 0x1000>,
178 <0x450000 0x1000>; 186 <0x450000 0x1000>;
179 msi-parent = <&gic_v2m0>; 187 msi-parent = <&gic_v2m0>;
180 clocks = <&ap_syscon 3>; 188 clocks = <&ap_clk 3>;
181 dma-coherent; 189 dma-coherent;
182 }; 190 };
183 191
@@ -186,7 +194,7 @@
186 reg = <0x460000 0x1000>, 194 reg = <0x460000 0x1000>,
187 <0x470000 0x1000>; 195 <0x470000 0x1000>;
188 msi-parent = <&gic_v2m0>; 196 msi-parent = <&gic_v2m0>;
189 clocks = <&ap_syscon 3>; 197 clocks = <&ap_clk 3>;
190 dma-coherent; 198 dma-coherent;
191 }; 199 };
192 200
@@ -252,6 +260,19 @@
252 compatible = "marvell,ap806-clock"; 260 compatible = "marvell,ap806-clock";
253 #clock-cells = <1>; 261 #clock-cells = <1>;
254 }; 262 };
263
264 ap_pinctrl: pinctrl {
265 compatible = "marvell,ap806-pinctrl";
266 };
267
268 ap_gpio: gpio {
269 compatible = "marvell,armada-8k-gpio";
270 offset = <0x1040>;
271 ngpios = <19>;
272 gpio-controller;
273 #gpio-cells = <2>;
274 gpio-ranges = <&ap_pinctrl 0 0 19>;
275 };
255 }; 276 };
256 }; 277 };
257 }; 278 };
diff --git a/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi b/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi
index d490a377d0c1..aec5f94423dd 100644
--- a/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi
@@ -44,45 +44,46 @@
44 * Device Tree file for Marvell Armada CP110 Master. 44 * Device Tree file for Marvell Armada CP110 Master.
45 */ 45 */
46 46
47#define ICU_GRP_NSR 0x0
48
47/ { 49/ {
48 cp110-master { 50 cp110-master {
49 #address-cells = <2>; 51 #address-cells = <2>;
50 #size-cells = <2>; 52 #size-cells = <2>;
51 compatible = "simple-bus"; 53 compatible = "simple-bus";
52 interrupt-parent = <&gic>; 54 interrupt-parent = <&cpm_icu>;
53 ranges; 55 ranges;
54 56
55 config-space@f2000000 { 57 config-space@f2000000 {
56 #address-cells = <1>; 58 #address-cells = <1>;
57 #size-cells = <1>; 59 #size-cells = <1>;
58 compatible = "simple-bus"; 60 compatible = "simple-bus";
59 interrupt-parent = <&gic>;
60 ranges = <0x0 0x0 0xf2000000 0x2000000>; 61 ranges = <0x0 0x0 0xf2000000 0x2000000>;
61 62
62 cpm_ethernet: ethernet@0 { 63 cpm_ethernet: ethernet@0 {
63 compatible = "marvell,armada-7k-pp22"; 64 compatible = "marvell,armada-7k-pp22";
64 reg = <0x0 0x100000>, <0x129000 0xb000>; 65 reg = <0x0 0x100000>, <0x129000 0xb000>;
65 clocks = <&cpm_syscon0 1 3>, <&cpm_syscon0 1 9>, <&cpm_syscon0 1 5>; 66 clocks = <&cpm_clk 1 3>, <&cpm_clk 1 9>, <&cpm_clk 1 5>;
66 clock-names = "pp_clk", "gop_clk", "mg_clk"; 67 clock-names = "pp_clk", "gop_clk", "mg_clk";
67 status = "disabled"; 68 status = "disabled";
68 dma-coherent; 69 dma-coherent;
69 70
70 cpm_eth0: eth0 { 71 cpm_eth0: eth0 {
71 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 72 interrupts = <ICU_GRP_NSR 39 IRQ_TYPE_LEVEL_HIGH>;
72 port-id = <0>; 73 port-id = <0>;
73 gop-port-id = <0>; 74 gop-port-id = <0>;
74 status = "disabled"; 75 status = "disabled";
75 }; 76 };
76 77
77 cpm_eth1: eth1 { 78 cpm_eth1: eth1 {
78 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 79 interrupts = <ICU_GRP_NSR 40 IRQ_TYPE_LEVEL_HIGH>;
79 port-id = <1>; 80 port-id = <1>;
80 gop-port-id = <2>; 81 gop-port-id = <2>;
81 status = "disabled"; 82 status = "disabled";
82 }; 83 };
83 84
84 cpm_eth2: eth2 { 85 cpm_eth2: eth2 {
85 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 86 interrupts = <ICU_GRP_NSR 41 IRQ_TYPE_LEVEL_HIGH>;
86 port-id = <2>; 87 port-id = <2>;
87 gop-port-id = <3>; 88 gop-port-id = <3>;
88 status = "disabled"; 89 status = "disabled";
@@ -94,7 +95,7 @@
94 #size-cells = <0>; 95 #size-cells = <0>;
95 compatible = "marvell,orion-mdio"; 96 compatible = "marvell,orion-mdio";
96 reg = <0x12a200 0x10>; 97 reg = <0x12a200 0x10>;
97 clocks = <&cpm_syscon0 1 9>, <&cpm_syscon0 1 5>; 98 clocks = <&cpm_clk 1 9>, <&cpm_clk 1 5>;
98 status = "disabled"; 99 status = "disabled";
99 }; 100 };
100 101
@@ -106,39 +107,58 @@
106 status = "disabled"; 107 status = "disabled";
107 }; 108 };
108 109
110 cpm_icu: interrupt-controller@1e0000 {
111 compatible = "marvell,cp110-icu";
112 reg = <0x1e0000 0x10>;
113 #interrupt-cells = <3>;
114 interrupt-controller;
115 msi-parent = <&gicp>;
116 };
117
109 cpm_syscon0: system-controller@440000 { 118 cpm_syscon0: system-controller@440000 {
110 compatible = "marvell,cp110-system-controller0", 119 compatible = "syscon", "simple-mfd";
111 "syscon";
112 reg = <0x440000 0x1000>; 120 reg = <0x440000 0x1000>;
113 #clock-cells = <2>; 121
114 core-clock-output-names = 122 cpm_clk: clock {
115 "cpm-apll", "cpm-ppv2-core", "cpm-eip", 123 compatible = "marvell,cp110-clock";
116 "cpm-core", "cpm-nand-core"; 124 #clock-cells = <2>;
117 gate-clock-output-names = 125 };
118 "cpm-audio", "cpm-communit", "cpm-nand", 126
119 "cpm-ppv2", "cpm-sdio", "cpm-mg-domain", 127 cpm_gpio1: gpio@100 {
120 "cpm-mg-core", "cpm-xor1", "cpm-xor0", 128 compatible = "marvell,armada-8k-gpio";
121 "cpm-gop-dp", "none", "cpm-pcie_x10", 129 offset = <0x100>;
122 "cpm-pcie_x11", "cpm-pcie_x4", "cpm-pcie-xor", 130 ngpios = <32>;
123 "cpm-sata", "cpm-sata-usb", "cpm-main", 131 gpio-controller;
124 "cpm-sd-mmc-gop", "none", "none", 132 #gpio-cells = <2>;
125 "cpm-slow-io", "cpm-usb3h0", "cpm-usb3h1", 133 gpio-ranges = <&cpm_pinctrl 0 0 32>;
126 "cpm-usb3dev", "cpm-eip150", "cpm-eip197"; 134 status = "disabled";
135
136 };
137
138 cpm_gpio2: gpio@140 {
139 compatible = "marvell,armada-8k-gpio";
140 offset = <0x140>;
141 ngpios = <31>;
142 gpio-controller;
143 #gpio-cells = <2>;
144 gpio-ranges = <&cpm_pinctrl 0 32 31>;
145 status = "disabled";
146 };
127 }; 147 };
128 148
129 cpm_rtc: rtc@284000 { 149 cpm_rtc: rtc@284000 {
130 compatible = "marvell,armada-8k-rtc"; 150 compatible = "marvell,armada-8k-rtc";
131 reg = <0x284000 0x20>, <0x284080 0x24>; 151 reg = <0x284000 0x20>, <0x284080 0x24>;
132 reg-names = "rtc", "rtc-soc"; 152 reg-names = "rtc", "rtc-soc";
133 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 153 interrupts = <ICU_GRP_NSR 77 IRQ_TYPE_LEVEL_HIGH>;
134 }; 154 };
135 155
136 cpm_sata0: sata@540000 { 156 cpm_sata0: sata@540000 {
137 compatible = "marvell,armada-8k-ahci", 157 compatible = "marvell,armada-8k-ahci",
138 "generic-ahci"; 158 "generic-ahci";
139 reg = <0x540000 0x30000>; 159 reg = <0x540000 0x30000>;
140 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 160 interrupts = <ICU_GRP_NSR 107 IRQ_TYPE_LEVEL_HIGH>;
141 clocks = <&cpm_syscon0 1 15>; 161 clocks = <&cpm_clk 1 15>;
142 status = "disabled"; 162 status = "disabled";
143 }; 163 };
144 164
@@ -147,8 +167,8 @@
147 "generic-xhci"; 167 "generic-xhci";
148 reg = <0x500000 0x4000>; 168 reg = <0x500000 0x4000>;
149 dma-coherent; 169 dma-coherent;
150 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 170 interrupts = <ICU_GRP_NSR 106 IRQ_TYPE_LEVEL_HIGH>;
151 clocks = <&cpm_syscon0 1 22>; 171 clocks = <&cpm_clk 1 22>;
152 status = "disabled"; 172 status = "disabled";
153 }; 173 };
154 174
@@ -157,8 +177,8 @@
157 "generic-xhci"; 177 "generic-xhci";
158 reg = <0x510000 0x4000>; 178 reg = <0x510000 0x4000>;
159 dma-coherent; 179 dma-coherent;
160 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 180 interrupts = <ICU_GRP_NSR 105 IRQ_TYPE_LEVEL_HIGH>;
161 clocks = <&cpm_syscon0 1 23>; 181 clocks = <&cpm_clk 1 23>;
162 status = "disabled"; 182 status = "disabled";
163 }; 183 };
164 184
@@ -168,7 +188,7 @@
168 <0x6b0000 0x1000>; 188 <0x6b0000 0x1000>;
169 dma-coherent; 189 dma-coherent;
170 msi-parent = <&gic_v2m0>; 190 msi-parent = <&gic_v2m0>;
171 clocks = <&cpm_syscon0 1 8>; 191 clocks = <&cpm_clk 1 8>;
172 }; 192 };
173 193
174 cpm_xor1: xor@6c0000 { 194 cpm_xor1: xor@6c0000 {
@@ -177,7 +197,7 @@
177 <0x6d0000 0x1000>; 197 <0x6d0000 0x1000>;
178 dma-coherent; 198 dma-coherent;
179 msi-parent = <&gic_v2m0>; 199 msi-parent = <&gic_v2m0>;
180 clocks = <&cpm_syscon0 1 7>; 200 clocks = <&cpm_clk 1 7>;
181 }; 201 };
182 202
183 cpm_spi0: spi@700600 { 203 cpm_spi0: spi@700600 {
@@ -186,7 +206,7 @@
186 #address-cells = <0x1>; 206 #address-cells = <0x1>;
187 #size-cells = <0x0>; 207 #size-cells = <0x0>;
188 cell-index = <1>; 208 cell-index = <1>;
189 clocks = <&cpm_syscon0 1 21>; 209 clocks = <&cpm_clk 1 21>;
190 status = "disabled"; 210 status = "disabled";
191 }; 211 };
192 212
@@ -196,7 +216,7 @@
196 #address-cells = <1>; 216 #address-cells = <1>;
197 #size-cells = <0>; 217 #size-cells = <0>;
198 cell-index = <2>; 218 cell-index = <2>;
199 clocks = <&cpm_syscon0 1 21>; 219 clocks = <&cpm_clk 1 21>;
200 status = "disabled"; 220 status = "disabled";
201 }; 221 };
202 222
@@ -205,8 +225,8 @@
205 reg = <0x701000 0x20>; 225 reg = <0x701000 0x20>;
206 #address-cells = <1>; 226 #address-cells = <1>;
207 #size-cells = <0>; 227 #size-cells = <0>;
208 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 228 interrupts = <ICU_GRP_NSR 120 IRQ_TYPE_LEVEL_HIGH>;
209 clocks = <&cpm_syscon0 1 21>; 229 clocks = <&cpm_clk 1 21>;
210 status = "disabled"; 230 status = "disabled";
211 }; 231 };
212 232
@@ -215,25 +235,25 @@
215 reg = <0x701100 0x20>; 235 reg = <0x701100 0x20>;
216 #address-cells = <1>; 236 #address-cells = <1>;
217 #size-cells = <0>; 237 #size-cells = <0>;
218 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 238 interrupts = <ICU_GRP_NSR 121 IRQ_TYPE_LEVEL_HIGH>;
219 clocks = <&cpm_syscon0 1 21>; 239 clocks = <&cpm_clk 1 21>;
220 status = "disabled"; 240 status = "disabled";
221 }; 241 };
222 242
223 cpm_trng: trng@760000 { 243 cpm_trng: trng@760000 {
224 compatible = "marvell,armada-8k-rng", "inside-secure,safexcel-eip76"; 244 compatible = "marvell,armada-8k-rng", "inside-secure,safexcel-eip76";
225 reg = <0x760000 0x7d>; 245 reg = <0x760000 0x7d>;
226 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 246 interrupts = <ICU_GRP_NSR 95 IRQ_TYPE_LEVEL_HIGH>;
227 clocks = <&cpm_syscon0 1 25>; 247 clocks = <&cpm_clk 1 25>;
228 status = "okay"; 248 status = "okay";
229 }; 249 };
230 250
231 cpm_sdhci0: sdhci@780000 { 251 cpm_sdhci0: sdhci@780000 {
232 compatible = "marvell,armada-cp110-sdhci"; 252 compatible = "marvell,armada-cp110-sdhci";
233 reg = <0x780000 0x300>; 253 reg = <0x780000 0x300>;
234 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 254 interrupts = <ICU_GRP_NSR 27 IRQ_TYPE_LEVEL_HIGH>;
235 clock-names = "core"; 255 clock-names = "core";
236 clocks = <&cpm_syscon0 1 4>; 256 clocks = <&cpm_clk 1 4>;
237 dma-coherent; 257 dma-coherent;
238 status = "disabled"; 258 status = "disabled";
239 }; 259 };
@@ -241,16 +261,16 @@
241 cpm_crypto: crypto@800000 { 261 cpm_crypto: crypto@800000 {
242 compatible = "inside-secure,safexcel-eip197"; 262 compatible = "inside-secure,safexcel-eip197";
243 reg = <0x800000 0x200000>; 263 reg = <0x800000 0x200000>;
244 interrupts = <GIC_SPI 34 (IRQ_TYPE_EDGE_RISING 264 interrupts = <ICU_GRP_NSR 87 (IRQ_TYPE_EDGE_RISING
245 | IRQ_TYPE_LEVEL_HIGH)>, 265 | IRQ_TYPE_LEVEL_HIGH)>,
246 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 266 <ICU_GRP_NSR 88 IRQ_TYPE_LEVEL_HIGH>,
247 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 267 <ICU_GRP_NSR 89 IRQ_TYPE_LEVEL_HIGH>,
248 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 268 <ICU_GRP_NSR 90 IRQ_TYPE_LEVEL_HIGH>,
249 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 269 <ICU_GRP_NSR 91 IRQ_TYPE_LEVEL_HIGH>,
250 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 270 <ICU_GRP_NSR 92 IRQ_TYPE_LEVEL_HIGH>;
251 interrupt-names = "mem", "ring0", "ring1", 271 interrupt-names = "mem", "ring0", "ring1",
252 "ring2", "ring3", "eip"; 272 "ring2", "ring3", "eip";
253 clocks = <&cpm_syscon0 1 26>; 273 clocks = <&cpm_clk 1 26>;
254 dma-mask = <0xff 0xffffffff>; 274 dma-mask = <0xff 0xffffffff>;
255 }; 275 };
256 }; 276 };
@@ -274,10 +294,10 @@
274 /* non-prefetchable memory */ 294 /* non-prefetchable memory */
275 0x82000000 0 0xf6000000 0 0xf6000000 0 0xf00000>; 295 0x82000000 0 0xf6000000 0 0xf6000000 0 0xf00000>;
276 interrupt-map-mask = <0 0 0 0>; 296 interrupt-map-mask = <0 0 0 0>;
277 interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 297 interrupt-map = <0 0 0 0 &cpm_icu 0 ICU_GRP_NSR 22 IRQ_TYPE_LEVEL_HIGH>;
278 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 298 interrupts = <ICU_GRP_NSR 22 IRQ_TYPE_LEVEL_HIGH>;
279 num-lanes = <1>; 299 num-lanes = <1>;
280 clocks = <&cpm_syscon0 1 13>; 300 clocks = <&cpm_clk 1 13>;
281 status = "disabled"; 301 status = "disabled";
282 }; 302 };
283 303
@@ -300,11 +320,11 @@
300 /* non-prefetchable memory */ 320 /* non-prefetchable memory */
301 0x82000000 0 0xf7000000 0 0xf7000000 0 0xf00000>; 321 0x82000000 0 0xf7000000 0 0xf7000000 0 0xf00000>;
302 interrupt-map-mask = <0 0 0 0>; 322 interrupt-map-mask = <0 0 0 0>;
303 interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 323 interrupt-map = <0 0 0 0 &cpm_icu 0 ICU_GRP_NSR 24 IRQ_TYPE_LEVEL_HIGH>;
304 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 324 interrupts = <ICU_GRP_NSR 24 IRQ_TYPE_LEVEL_HIGH>;
305 325
306 num-lanes = <1>; 326 num-lanes = <1>;
307 clocks = <&cpm_syscon0 1 11>; 327 clocks = <&cpm_clk 1 11>;
308 status = "disabled"; 328 status = "disabled";
309 }; 329 };
310 330
@@ -327,11 +347,11 @@
327 /* non-prefetchable memory */ 347 /* non-prefetchable memory */
328 0x82000000 0 0xf8000000 0 0xf8000000 0 0xf00000>; 348 0x82000000 0 0xf8000000 0 0xf8000000 0 0xf00000>;
329 interrupt-map-mask = <0 0 0 0>; 349 interrupt-map-mask = <0 0 0 0>;
330 interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 350 interrupt-map = <0 0 0 0 &cpm_icu 0 ICU_GRP_NSR 23 IRQ_TYPE_LEVEL_HIGH>;
331 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 351 interrupts = <ICU_GRP_NSR 23 IRQ_TYPE_LEVEL_HIGH>;
332 352
333 num-lanes = <1>; 353 num-lanes = <1>;
334 clocks = <&cpm_syscon0 1 12>; 354 clocks = <&cpm_clk 1 12>;
335 status = "disabled"; 355 status = "disabled";
336 }; 356 };
337 }; 357 };
diff --git a/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi b/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi
index dc4673dcf81b..9daf1e17bdfe 100644
--- a/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi
@@ -44,19 +44,20 @@
44 * Device Tree file for Marvell Armada CP110 Slave. 44 * Device Tree file for Marvell Armada CP110 Slave.
45 */ 45 */
46 46
47#define ICU_GRP_NSR 0x0
48
47/ { 49/ {
48 cp110-slave { 50 cp110-slave {
49 #address-cells = <2>; 51 #address-cells = <2>;
50 #size-cells = <2>; 52 #size-cells = <2>;
51 compatible = "simple-bus"; 53 compatible = "simple-bus";
52 interrupt-parent = <&gic>; 54 interrupt-parent = <&cps_icu>;
53 ranges; 55 ranges;
54 56
55 config-space@f4000000 { 57 config-space@f4000000 {
56 #address-cells = <1>; 58 #address-cells = <1>;
57 #size-cells = <1>; 59 #size-cells = <1>;
58 compatible = "simple-bus"; 60 compatible = "simple-bus";
59 interrupt-parent = <&gic>;
60 ranges = <0x0 0x0 0xf4000000 0x2000000>; 61 ranges = <0x0 0x0 0xf4000000 0x2000000>;
61 62
62 cps_rtc: rtc@284000 { 63 cps_rtc: rtc@284000 {
@@ -69,27 +70,27 @@
69 cps_ethernet: ethernet@0 { 70 cps_ethernet: ethernet@0 {
70 compatible = "marvell,armada-7k-pp22"; 71 compatible = "marvell,armada-7k-pp22";
71 reg = <0x0 0x100000>, <0x129000 0xb000>; 72 reg = <0x0 0x100000>, <0x129000 0xb000>;
72 clocks = <&cps_syscon0 1 3>, <&cps_syscon0 1 9>, <&cps_syscon0 1 5>; 73 clocks = <&cps_clk 1 3>, <&cps_clk 1 9>, <&cps_clk 1 5>;
73 clock-names = "pp_clk", "gop_clk", "mg_clk"; 74 clock-names = "pp_clk", "gop_clk", "mg_clk";
74 status = "disabled"; 75 status = "disabled";
75 dma-coherent; 76 dma-coherent;
76 77
77 cps_eth0: eth0 { 78 cps_eth0: eth0 {
78 interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>; 79 interrupts = <ICU_GRP_NSR 39 IRQ_TYPE_LEVEL_HIGH>;
79 port-id = <0>; 80 port-id = <0>;
80 gop-port-id = <0>; 81 gop-port-id = <0>;
81 status = "disabled"; 82 status = "disabled";
82 }; 83 };
83 84
84 cps_eth1: eth1 { 85 cps_eth1: eth1 {
85 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>; 86 interrupts = <ICU_GRP_NSR 40 IRQ_TYPE_LEVEL_HIGH>;
86 port-id = <1>; 87 port-id = <1>;
87 gop-port-id = <2>; 88 gop-port-id = <2>;
88 status = "disabled"; 89 status = "disabled";
89 }; 90 };
90 91
91 cps_eth2: eth2 { 92 cps_eth2: eth2 {
92 interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 93 interrupts = <ICU_GRP_NSR 41 IRQ_TYPE_LEVEL_HIGH>;
93 port-id = <2>; 94 port-id = <2>;
94 gop-port-id = <3>; 95 gop-port-id = <3>;
95 status = "disabled"; 96 status = "disabled";
@@ -101,7 +102,7 @@
101 #size-cells = <0>; 102 #size-cells = <0>;
102 compatible = "marvell,orion-mdio"; 103 compatible = "marvell,orion-mdio";
103 reg = <0x12a200 0x10>; 104 reg = <0x12a200 0x10>;
104 clocks = <&cps_syscon0 1 9>, <&cps_syscon0 1 5>; 105 clocks = <&cps_clk 1 9>, <&cps_clk 1 5>;
105 status = "disabled"; 106 status = "disabled";
106 }; 107 };
107 108
@@ -113,32 +114,52 @@
113 status = "disabled"; 114 status = "disabled";
114 }; 115 };
115 116
117 cps_icu: interrupt-controller@1e0000 {
118 compatible = "marvell,cp110-icu";
119 reg = <0x1e0000 0x10>;
120 #interrupt-cells = <3>;
121 interrupt-controller;
122 msi-parent = <&gicp>;
123 };
124
116 cps_syscon0: system-controller@440000 { 125 cps_syscon0: system-controller@440000 {
117 compatible = "marvell,cp110-system-controller0", 126 compatible = "syscon", "simple-mfd";
118 "syscon";
119 reg = <0x440000 0x1000>; 127 reg = <0x440000 0x1000>;
120 #clock-cells = <2>; 128
121 core-clock-output-names = 129 cps_clk: clock {
122 "cps-apll", "cps-ppv2-core", "cps-eip", 130 compatible = "marvell,cp110-clock";
123 "cps-core", "cps-nand-core"; 131 #clock-cells = <2>;
124 gate-clock-output-names = 132 };
125 "cps-audio", "cps-communit", "cps-nand", 133
126 "cps-ppv2", "cps-sdio", "cps-mg-domain", 134 cps_gpio1: gpio@100 {
127 "cps-mg-core", "cps-xor1", "cps-xor0", 135 compatible = "marvell,armada-8k-gpio";
128 "cps-gop-dp", "none", "cps-pcie_x10", 136 offset = <0x100>;
129 "cps-pcie_x11", "cps-pcie_x4", "cps-pcie-xor", 137 ngpios = <32>;
130 "cps-sata", "cps-sata-usb", "cps-main", 138 gpio-controller;
131 "cps-sd-mmc-gop", "none", "none", 139 #gpio-cells = <2>;
132 "cps-slow-io", "cps-usb3h0", "cps-usb3h1", 140 gpio-ranges = <&cps_pinctrl 0 0 32>;
133 "cps-usb3dev", "cps-eip150", "cps-eip197"; 141 status = "disabled";
142
143 };
144
145 cps_gpio2: gpio@140 {
146 compatible = "marvell,armada-8k-gpio";
147 offset = <0x140>;
148 ngpios = <31>;
149 gpio-controller;
150 #gpio-cells = <2>;
151 gpio-ranges = <&cps_pinctrl 0 32 31>;
152 status = "disabled";
153 };
154
134 }; 155 };
135 156
136 cps_sata0: sata@540000 { 157 cps_sata0: sata@540000 {
137 compatible = "marvell,armada-8k-ahci", 158 compatible = "marvell,armada-8k-ahci",
138 "generic-ahci"; 159 "generic-ahci";
139 reg = <0x540000 0x30000>; 160 reg = <0x540000 0x30000>;
140 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; 161 interrupts = <ICU_GRP_NSR 107 IRQ_TYPE_LEVEL_HIGH>;
141 clocks = <&cps_syscon0 1 15>; 162 clocks = <&cps_clk 1 15>;
142 status = "disabled"; 163 status = "disabled";
143 }; 164 };
144 165
@@ -147,8 +168,8 @@
147 "generic-xhci"; 168 "generic-xhci";
148 reg = <0x500000 0x4000>; 169 reg = <0x500000 0x4000>;
149 dma-coherent; 170 dma-coherent;
150 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; 171 interrupts = <ICU_GRP_NSR 106 IRQ_TYPE_LEVEL_HIGH>;
151 clocks = <&cps_syscon0 1 22>; 172 clocks = <&cps_clk 1 22>;
152 status = "disabled"; 173 status = "disabled";
153 }; 174 };
154 175
@@ -157,8 +178,8 @@
157 "generic-xhci"; 178 "generic-xhci";
158 reg = <0x510000 0x4000>; 179 reg = <0x510000 0x4000>;
159 dma-coherent; 180 dma-coherent;
160 interrupts = <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>; 181 interrupts = <ICU_GRP_NSR 105 IRQ_TYPE_LEVEL_HIGH>;
161 clocks = <&cps_syscon0 1 23>; 182 clocks = <&cps_clk 1 23>;
162 status = "disabled"; 183 status = "disabled";
163 }; 184 };
164 185
@@ -168,7 +189,7 @@
168 <0x6b0000 0x1000>; 189 <0x6b0000 0x1000>;
169 dma-coherent; 190 dma-coherent;
170 msi-parent = <&gic_v2m0>; 191 msi-parent = <&gic_v2m0>;
171 clocks = <&cps_syscon0 1 8>; 192 clocks = <&cps_clk 1 8>;
172 }; 193 };
173 194
174 cps_xor1: xor@6c0000 { 195 cps_xor1: xor@6c0000 {
@@ -177,7 +198,7 @@
177 <0x6d0000 0x1000>; 198 <0x6d0000 0x1000>;
178 dma-coherent; 199 dma-coherent;
179 msi-parent = <&gic_v2m0>; 200 msi-parent = <&gic_v2m0>;
180 clocks = <&cps_syscon0 1 7>; 201 clocks = <&cps_clk 1 7>;
181 }; 202 };
182 203
183 cps_spi0: spi@700600 { 204 cps_spi0: spi@700600 {
@@ -186,7 +207,7 @@
186 #address-cells = <0x1>; 207 #address-cells = <0x1>;
187 #size-cells = <0x0>; 208 #size-cells = <0x0>;
188 cell-index = <3>; 209 cell-index = <3>;
189 clocks = <&cps_syscon0 1 21>; 210 clocks = <&cps_clk 1 21>;
190 status = "disabled"; 211 status = "disabled";
191 }; 212 };
192 213
@@ -196,7 +217,7 @@
196 #address-cells = <1>; 217 #address-cells = <1>;
197 #size-cells = <0>; 218 #size-cells = <0>;
198 cell-index = <4>; 219 cell-index = <4>;
199 clocks = <&cps_syscon0 1 21>; 220 clocks = <&cps_clk 1 21>;
200 status = "disabled"; 221 status = "disabled";
201 }; 222 };
202 223
@@ -205,8 +226,8 @@
205 reg = <0x701000 0x20>; 226 reg = <0x701000 0x20>;
206 #address-cells = <1>; 227 #address-cells = <1>;
207 #size-cells = <0>; 228 #size-cells = <0>;
208 interrupts = <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>; 229 interrupts = <ICU_GRP_NSR 120 IRQ_TYPE_LEVEL_HIGH>;
209 clocks = <&cps_syscon0 1 21>; 230 clocks = <&cps_clk 1 21>;
210 status = "disabled"; 231 status = "disabled";
211 }; 232 };
212 233
@@ -215,32 +236,32 @@
215 reg = <0x701100 0x20>; 236 reg = <0x701100 0x20>;
216 #address-cells = <1>; 237 #address-cells = <1>;
217 #size-cells = <0>; 238 #size-cells = <0>;
218 interrupts = <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>; 239 interrupts = <ICU_GRP_NSR 121 IRQ_TYPE_LEVEL_HIGH>;
219 clocks = <&cps_syscon0 1 21>; 240 clocks = <&cps_clk 1 21>;
220 status = "disabled"; 241 status = "disabled";
221 }; 242 };
222 243
223 cps_trng: trng@760000 { 244 cps_trng: trng@760000 {
224 compatible = "marvell,armada-8k-rng", "inside-secure,safexcel-eip76"; 245 compatible = "marvell,armada-8k-rng", "inside-secure,safexcel-eip76";
225 reg = <0x760000 0x7d>; 246 reg = <0x760000 0x7d>;
226 interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>; 247 interrupts = <ICU_GRP_NSR 95 IRQ_TYPE_LEVEL_HIGH>;
227 clocks = <&cps_syscon0 1 25>; 248 clocks = <&cps_clk 1 25>;
228 status = "okay"; 249 status = "okay";
229 }; 250 };
230 251
231 cps_crypto: crypto@800000 { 252 cps_crypto: crypto@800000 {
232 compatible = "inside-secure,safexcel-eip197"; 253 compatible = "inside-secure,safexcel-eip197";
233 reg = <0x800000 0x200000>; 254 reg = <0x800000 0x200000>;
234 interrupts = <GIC_SPI 34 (IRQ_TYPE_EDGE_RISING 255 interrupts = <ICU_GRP_NSR 87 (IRQ_TYPE_EDGE_RISING
235 | IRQ_TYPE_LEVEL_HIGH)>, 256 | IRQ_TYPE_LEVEL_HIGH)>,
236 <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>, 257 <ICU_GRP_NSR 88 IRQ_TYPE_LEVEL_HIGH>,
237 <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 258 <ICU_GRP_NSR 89 IRQ_TYPE_LEVEL_HIGH>,
238 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 259 <ICU_GRP_NSR 90 IRQ_TYPE_LEVEL_HIGH>,
239 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 260 <ICU_GRP_NSR 91 IRQ_TYPE_LEVEL_HIGH>,
240 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>; 261 <ICU_GRP_NSR 92 IRQ_TYPE_LEVEL_HIGH>;
241 interrupt-names = "mem", "ring0", "ring1", 262 interrupt-names = "mem", "ring0", "ring1",
242 "ring2", "ring3", "eip"; 263 "ring2", "ring3", "eip";
243 clocks = <&cps_syscon0 1 26>; 264 clocks = <&cps_clk 1 26>;
244 dma-mask = <0xff 0xffffffff>; 265 dma-mask = <0xff 0xffffffff>;
245 /* 266 /*
246 * The cryptographic engine found on the cp110 267 * The cryptographic engine found on the cp110
@@ -272,10 +293,10 @@
272 /* non-prefetchable memory */ 293 /* non-prefetchable memory */
273 0x82000000 0 0xfa000000 0 0xfa000000 0 0xf00000>; 294 0x82000000 0 0xfa000000 0 0xfa000000 0 0xf00000>;
274 interrupt-map-mask = <0 0 0 0>; 295 interrupt-map-mask = <0 0 0 0>;
275 interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>; 296 interrupt-map = <0 0 0 0 &cps_icu 0 ICU_GRP_NSR 22 IRQ_TYPE_LEVEL_HIGH>;
276 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>; 297 interrupts = <ICU_GRP_NSR 22 IRQ_TYPE_LEVEL_HIGH>;
277 num-lanes = <1>; 298 num-lanes = <1>;
278 clocks = <&cps_syscon0 1 13>; 299 clocks = <&cps_clk 1 13>;
279 status = "disabled"; 300 status = "disabled";
280 }; 301 };
281 302
@@ -298,11 +319,11 @@
298 /* non-prefetchable memory */ 319 /* non-prefetchable memory */
299 0x82000000 0 0xfb000000 0 0xfb000000 0 0xf00000>; 320 0x82000000 0 0xfb000000 0 0xfb000000 0 0xf00000>;
300 interrupt-map-mask = <0 0 0 0>; 321 interrupt-map-mask = <0 0 0 0>;
301 interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>; 322 interrupt-map = <0 0 0 0 &cps_icu 0 ICU_GRP_NSR 24 IRQ_TYPE_LEVEL_HIGH>;
302 interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>; 323 interrupts = <ICU_GRP_NSR 24 IRQ_TYPE_LEVEL_HIGH>;
303 324
304 num-lanes = <1>; 325 num-lanes = <1>;
305 clocks = <&cps_syscon0 1 11>; 326 clocks = <&cps_clk 1 11>;
306 status = "disabled"; 327 status = "disabled";
307 }; 328 };
308 329
@@ -325,11 +346,11 @@
325 /* non-prefetchable memory */ 346 /* non-prefetchable memory */
326 0x82000000 0 0xfc000000 0 0xfc000000 0 0xf00000>; 347 0x82000000 0 0xfc000000 0 0xfc000000 0 0xf00000>;
327 interrupt-map-mask = <0 0 0 0>; 348 interrupt-map-mask = <0 0 0 0>;
328 interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>; 349 interrupt-map = <0 0 0 0 &cps_icu 0 ICU_GRP_NSR 23 IRQ_TYPE_LEVEL_HIGH>;
329 interrupts = <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>; 350 interrupts = <ICU_GRP_NSR 23 IRQ_TYPE_LEVEL_HIGH>;
330 351
331 num-lanes = <1>; 352 num-lanes = <1>;
332 clocks = <&cps_syscon0 1 12>; 353 clocks = <&cps_clk 1 12>;
333 status = "disabled"; 354 status = "disabled";
334 }; 355 };
335 }; 356 };
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-23 14:30:21 -0400