drm: sti: add bindings for DRM driver

Add DRM/KMS driver bindings documentation. Describe the required properties for each of the hardware IPs drivers. Signed-off-by: Benjamin Gaignard <benjamin.gaignard@linaro.org> Reviewed-by: Rob Clark <robdclark@gmail.com>
author: Benjamin Gaignard <benjamin.gaignard@linaro.org> 2014-07-28 04:23:12 -0400
committer: Benjamin Gaignard <benjamin.gaignard@linaro.org> 2014-07-30 12:11:53 -0400
commit: 30ebb9088c50181e0f8a2013f7d7579aa3480833 (patch)
tree: 72d7a99d9ecaafeaa4ebbfe6332c04d043316e33
parent: e05444be705b5c7c7f85d7722b6f97f3a6732d54 (diff)
2 files changed, 247 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/gpu/st,stih4xx.txt b/Documentation/devicetree/bindings/gpu/st,stih4xx.txt
new file mode 100644
index 000000000000..2d150c311a05
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpu/st,stih4xx.txt
@@ -0,0 +1,189 @@
+STMicroelectronics stih4xx platforms
+- sti-vtg: video timing generator
+  Required properties:
+  - compatible: "st,vtg"
+  - reg: Physical base address of the IP registers and length of memory mapped region.
+  Optional properties:
+  - interrupts : VTG interrupt number to the CPU.
+  - st,slave: phandle on a slave vtg
+- sti-vtac: video timing advanced inter dye communication Rx and TX
+  Required properties:
+  - compatible: "st,vtac-main" or "st,vtac-aux"
+  - reg: Physical base address of the IP registers and length of memory mapped region.
+  - clocks: from common clock binding: handle hardware IP needed clocks, the
+    number of clocks may depend of the SoC type.
+    See ../clocks/clock-bindings.txt for details.
+  - clock-names: names of the clocks listed in clocks property in the same
+    order.
+- sti-display-subsystem: Master device for DRM sub-components
+  This device must be the parent of all the sub-components and is responsible
+  of bind them.
+  Required properties:
+  - compatible: "st,sti-display-subsystem"
+  - ranges: to allow probing of subdevices
+- sti-compositor: frame compositor engine
+  must be a child of sti-display-subsystem
+  Required properties:
+  - compatible: "st,stih<chip>-compositor"
+  - reg: Physical base address of the IP registers and length of memory mapped region.
+  - clocks: from common clock binding: handle hardware IP needed clocks, the
+    number of clocks may depend of the SoC type.
+    See ../clocks/clock-bindings.txt for details.
+  - clock-names: names of the clocks listed in clocks property in the same
+    order.
+  - resets: resets to be used by the device
+    See ../reset/reset.txt for details.
+  - reset-names: names of the resets listed in resets property in the same
+    order.
+  - st,vtg: phandle(s) on vtg device (main and aux) nodes.
+- sti-tvout: video out hardware block
+  must be a child of sti-display-subsystem
+  Required properties:
+  - compatible: "st,stih<chip>-tvout"
+  - reg: Physical base address of the IP registers and length of memory mapped region.
+  - reg-names: names of the mapped memory regions listed in regs property in
+    the same order.
+  - resets: resets to be used by the device
+    See ../reset/reset.txt for details.
+  - reset-names: names of the resets listed in resets property in the same
+    order.
+  - ranges: to allow probing of subdevices
+- sti-hdmi: hdmi output block
+  must be a child of sti-tvout
+  Required properties:
+  - compatible: "st,stih<chip>-hdmi";
+  - reg: Physical base address of the IP registers and length of memory mapped region.
+  - reg-names: names of the mapped memory regions listed in regs property in
+    the same order.
+  - interrupts : HDMI interrupt number to the CPU.
+  - interrupt-names: name of the interrupts listed in interrupts property in
+    the same order
+  - clocks: from common clock binding: handle hardware IP needed clocks, the
+    number of clocks may depend of the SoC type.
+  - clock-names: names of the clocks listed in clocks property in the same
+    order.
+  - hdmi,hpd-gpio: gpio id to detect if an hdmi cable is plugged or not.
+sti-hda:
+  Required properties:
+  must be a child of sti-tvout
+  - compatible: "st,stih<chip>-hda"
+  - reg: Physical base address of the IP registers and length of memory mapped region.
+  - reg-names: names of the mapped memory regions listed in regs property in
+    the same order.
+  - clocks: from common clock binding: handle hardware IP needed clocks, the
+    number of clocks may depend of the SoC type.
+    See ../clocks/clock-bindings.txt for details.
+  - clock-names: names of the clocks listed in clocks property in the same
+    order.
+Example:
+/ {
+        ...
+        vtg_main_slave: sti-vtg-main-slave@fe85A800 {
+                compatible      = "st,vtg";
+                reg             = <0xfe85A800 0x300>;
+                interrupts      = <GIC_SPI 175 IRQ_TYPE_NONE>;
+        };
+        vtg_main: sti-vtg-main-master@fd348000 {
+                compatible      = "st,vtg";
+                reg             = <0xfd348000 0x400>;
+                st,slave        = <&vtg_main_slave>;
+        };
+        vtg_aux_slave: sti-vtg-aux-slave@fd348400 {
+                compatible      = "st,vtg";
+                reg             = <0xfe858200 0x300>;
+                interrupts      = <GIC_SPI 176 IRQ_TYPE_NONE>;
+        };
+        vtg_aux: sti-vtg-aux-master@fd348400 {
+                compatible      = "st,vtg";
+                reg             = <0xfd348400 0x400>;
+                st,slave        = <&vtg_aux_slave>;
+        };
+        sti-vtac-rx-main@fee82800 {
+                compatible      = "st,vtac-main";
+                reg             = <0xfee82800 0x200>;
+                clock-names     = "vtac";
+                clocks          = <&clk_m_a2_div0 CLK_M_VTAC_MAIN_PHY>;
+        };
+        sti-vtac-rx-aux@fee82a00 {
+                compatible      = "st,vtac-aux";
+                reg             = <0xfee82a00 0x200>;
+                clock-names     = "vtac";
+                clocks          = <&clk_m_a2_div0 CLK_M_VTAC_AUX_PHY>;
+        };
+        sti-vtac-tx-main@fd349000 {
+                compatible      = "st,vtac-main";
+                reg             = <0xfd349000 0x200>, <0xfd320000 0x10000>;
+                clock-names     = "vtac";
+                clocks           = <&clk_s_a1_hs CLK_S_VTAC_TX_PHY>;
+        };
+        sti-vtac-tx-aux@fd349200 {
+                compatible      = "st,vtac-aux";
+                reg             = <0xfd349200 0x200>, <0xfd320000 0x10000>;
+                clock-names     = "vtac";
+                clocks          = <&clk_s_a1_hs CLK_S_VTAC_TX_PHY>;
+        };
+        sti-display-subsystem {
+                compatible = "st,sti-display-subsystem";
+                ranges;
+                sti-compositor@fd340000 {
+                        compatible      = "st,stih416-compositor";
+                        reg             = <0xfd340000 0x1000>;
+                        clock-names     = "compo_main", "compo_aux",
+                                          "pix_main", "pix_aux";
+                        clocks          = <&clk_m_a2_div1 CLK_M_COMPO_MAIN>, <&clk_m_a2_div1 CLK_M_COMPO_AUX>,
+                                          <&clockgen_c_vcc CLK_S_PIX_MAIN>, <&clockgen_c_vcc CLK_S_PIX_AUX>;
+                        reset-names     = "compo-main", "compo-aux";
+                        resets          = <&softreset STIH416_COMPO_M_SOFTRESET>, <&softreset STIH416_COMPO_A_SOFTRESET>;
+                        st,vtg          = <&vtg_main>, <&vtg_aux>;
+                };
+                sti-tvout@fe000000 {
+                        compatible      = "st,stih416-tvout";
+                        reg             = <0xfe000000 0x1000>, <0xfe85a000 0x400>, <0xfe830000 0x10000>;
+                        reg-names       = "tvout-reg", "hda-reg", "syscfg";
+                        reset-names     = "tvout";
+                        resets          = <&softreset STIH416_HDTVOUT_SOFTRESET>;
+                        ranges;
+                        sti-hdmi@fe85c000 {
+                                compatible      = "st,stih416-hdmi";
+                                reg             = <0xfe85c000 0x1000>, <0xfe830000 0x10000>;
+                                reg-names       = "hdmi-reg", "syscfg";
+                                interrupts      = <GIC_SPI 173 IRQ_TYPE_NONE>;
+                                interrupt-names = "irq";
+                                clock-names     = "pix", "tmds", "phy", "audio";
+                                clocks          = <&clockgen_c_vcc CLK_S_PIX_HDMI>, <&clockgen_c_vcc CLK_S_TMDS_HDMI>, <&clockgen_c_vcc CLK_S_HDMI_REJECT_PLL>, <&clockgen_b1 CLK_S_PCM_0>;
+                                hdmi,hpd-gpio   = <&PIO2 5>;
+                        };
+                        sti-hda@fe85a000 {
+                                compatible      = "st,stih416-hda";
+                                reg             = <0xfe85a000 0x400>, <0xfe83085c 0x4>;
+                                reg-names       = "hda-reg", "video-dacs-ctrl";
+                                clock-names     = "pix", "hddac";
+                                clocks          = <&clockgen_c_vcc CLK_S_PIX_HD>, <&clockgen_c_vcc CLK_S_HDDAC>;
+                        };
+                };
+        };
+        ...
+};
diff --git a/drivers/gpu/drm/sti/NOTES b/drivers/gpu/drm/sti/NOTES
new file mode 100644
index 000000000000..57e257969198
--- /dev/null
+++ b/drivers/gpu/drm/sti/NOTES
@@ -0,0 +1,58 @@
+1. stiH display hardware IP
+---------------------------
+The STMicroelectronics stiH SoCs use a common chain of HW display IP blocks:
+- The High Quality Video Display Processor (HQVDP) gets video frames from a
+  video decoder and does high quality video processing, including scaling.
+- The Compositor is a multiplane, dual-mixer (Main & Aux) digital processor. It
+  has several inputs:
+  - The graphics planes are internally processed by the Generic Display
+    Pipeline (GDP).
+  - The video plug (VID) connects to the HQVDP output.
+  - The cursor handles ... a cursor.
+- The TV OUT pre-formats (convert, clip, round) the compositor output data
+- The HDMI / DVO / HD Analog / SD analog IP builds the video signals
+  - DVO (Digital Video Output) handles a 24bits parallel signal
+  - The HD analog signal is typically driven by a YCbCr cable, supporting up to
+    1080i mode.
+  - The SD analog signal is typically used for legacy TV
+- The VTG (Video Timing Generators) build Vsync signals used by the other HW IP
+Note that some stiH drivers support only a subset of thee HW IP.
+                  .-------------.   .-----------.   .-----------.
+GPU >-------------+GDP     Main |   |           +---+    HDMI   +--> HDMI
+GPU >-------------+GDP     mixer+---+           |   :===========:
+GPU >-------------+Cursor       |   |           +---+    DVO    +--> 24b//
+        -------   |  COMPOSITOR |   |  TV OUT   |   :===========:
+       |       |  |             |   |           +---+ HD analog +--> YCbCr
+Vid >--+ HQVDP +--+VID     Aux  +---+           |   :===========:
+dec    |       |  |        mixer|   |           +---+ SD analog +--> CVBS
+       '-------'  '-------------'   '-----------'   '-----------'
+                   .-----------.
+                   |       main+--> Vsync
+                   | VTG       |
+                   |        aux+--> Vsync
+                   '-----------'
+2. DRM / HW mapping
+-------------------
+These IP are mapped to the DRM objects as following:
+- The CRTCs are mapped to the Compositor Main and Aux Mixers
+- The Framebuffers and planes are mapped to the Compositor GDP (non video
+  buffers) and to HQVDP+VID (video buffers)
+- The Cursor is mapped to the Compositor Cursor
+- The Encoders are mapped to the TVOut
+- The Bridges/Connectors are mapped to the HDMI / DVO / HD Analog / SD analog
+FB & planes         Cursor      CRTC     Encoders    Bridges/Connectors
+   |                   |          |         |                       |
+   |                   |          |         |                       |
+   |              .-------------. | .-----------.   .-----------.   |
+   +------------> |GDP |   Main | | |       +-> |   |    HDMI   | <-+
+   +------------> |GDP v   mixer|<+ |       |   |   :===========:   |
+   |              |Cursor       | | |       +-> |   |    DVO    | <-+
+   |    -------   |  COMPOSITOR | | |TV OUT |   |   :===========:   |
+   |   |       |  |             | | |       +-> |   | HD analog | <-+
+   +-> | HQVDP |  |VID     Aux  |<+ |       |   |   :===========:   |
+       |       |  |        mixer|   |       +-> |   | SD analog | <-+
+       '-------'  '-------------'   '-----------'   '-----------'
author	Benjamin Gaignard <benjamin.gaignard@linaro.org>	2014-07-28 04:23:12 -0400
committer	Benjamin Gaignard <benjamin.gaignard@linaro.org>	2014-07-30 12:11:53 -0400
commit	30ebb9088c50181e0f8a2013f7d7579aa3480833 (patch)
tree	72d7a99d9ecaafeaa4ebbfe6332c04d043316e33
parent	e05444be705b5c7c7f85d7722b6f97f3a6732d54 (diff)

diff --git a/Documentation/devicetree/bindings/gpu/st,stih4xx.txt b/Documentation/devicetree/bindings/gpu/st,stih4xx.txt new file mode 100644 index 000000000000..2d150c311a05 --- /dev/null +++ b/Documentation/devicetree/bindings/gpu/st,stih4xx.txt
@@ -0,0 +1,189 @@
	1	STMicroelectronics stih4xx platforms
	2
	3	- sti-vtg: video timing generator
	4	Required properties:
	5	- compatible: "st,vtg"
	6	- reg: Physical base address of the IP registers and length of memory mapped region.
	7	Optional properties:
	8	- interrupts : VTG interrupt number to the CPU.
	9	- st,slave: phandle on a slave vtg
	10
	11	- sti-vtac: video timing advanced inter dye communication Rx and TX
	12	Required properties:
	13	- compatible: "st,vtac-main" or "st,vtac-aux"
	14	- reg: Physical base address of the IP registers and length of memory mapped region.
	15	- clocks: from common clock binding: handle hardware IP needed clocks, the
	16	number of clocks may depend of the SoC type.
	17	See ../clocks/clock-bindings.txt for details.
	18	- clock-names: names of the clocks listed in clocks property in the same
	19	order.
	20
	21	- sti-display-subsystem: Master device for DRM sub-components
	22	This device must be the parent of all the sub-components and is responsible
	23	of bind them.
	24	Required properties:
	25	- compatible: "st,sti-display-subsystem"
	26	- ranges: to allow probing of subdevices
	27
	28	- sti-compositor: frame compositor engine
	29	must be a child of sti-display-subsystem
	30	Required properties:
	31	- compatible: "st,stih<chip>-compositor"
	32	- reg: Physical base address of the IP registers and length of memory mapped region.
	33	- clocks: from common clock binding: handle hardware IP needed clocks, the
	34	number of clocks may depend of the SoC type.
	35	See ../clocks/clock-bindings.txt for details.
	36	- clock-names: names of the clocks listed in clocks property in the same
	37	order.
	38	- resets: resets to be used by the device
	39	See ../reset/reset.txt for details.
	40	- reset-names: names of the resets listed in resets property in the same
	41	order.
	42	- st,vtg: phandle(s) on vtg device (main and aux) nodes.
	43
	44	- sti-tvout: video out hardware block
	45	must be a child of sti-display-subsystem
	46	Required properties:
	47	- compatible: "st,stih<chip>-tvout"
	48	- reg: Physical base address of the IP registers and length of memory mapped region.
	49	- reg-names: names of the mapped memory regions listed in regs property in
	50	the same order.
	51	- resets: resets to be used by the device
	52	See ../reset/reset.txt for details.
	53	- reset-names: names of the resets listed in resets property in the same
	54	order.
	55	- ranges: to allow probing of subdevices
	56
	57	- sti-hdmi: hdmi output block
	58	must be a child of sti-tvout
	59	Required properties:
	60	- compatible: "st,stih<chip>-hdmi";
	61	- reg: Physical base address of the IP registers and length of memory mapped region.
	62	- reg-names: names of the mapped memory regions listed in regs property in
	63	the same order.
	64	- interrupts : HDMI interrupt number to the CPU.
	65	- interrupt-names: name of the interrupts listed in interrupts property in
	66	the same order
	67	- clocks: from common clock binding: handle hardware IP needed clocks, the
	68	number of clocks may depend of the SoC type.
	69	- clock-names: names of the clocks listed in clocks property in the same
	70	order.
	71	- hdmi,hpd-gpio: gpio id to detect if an hdmi cable is plugged or not.
	72
	73	sti-hda:
	74	Required properties:
	75	must be a child of sti-tvout
	76	- compatible: "st,stih<chip>-hda"
	77	- reg: Physical base address of the IP registers and length of memory mapped region.
	78	- reg-names: names of the mapped memory regions listed in regs property in
	79	the same order.
	80	- clocks: from common clock binding: handle hardware IP needed clocks, the
	81	number of clocks may depend of the SoC type.
	82	See ../clocks/clock-bindings.txt for details.
	83	- clock-names: names of the clocks listed in clocks property in the same
	84	order.
	85
	86	Example:
	87
	88	/ {
	89	...
	90
	91	vtg_main_slave: sti-vtg-main-slave@fe85A800 {
	92	compatible = "st,vtg";
	93	reg = <0xfe85A800 0x300>;
	94	interrupts = <GIC_SPI 175 IRQ_TYPE_NONE>;
	95	};
	96
	97	vtg_main: sti-vtg-main-master@fd348000 {
	98	compatible = "st,vtg";
	99	reg = <0xfd348000 0x400>;
	100	st,slave = <&vtg_main_slave>;
	101	};
	102
	103	vtg_aux_slave: sti-vtg-aux-slave@fd348400 {
	104	compatible = "st,vtg";
	105	reg = <0xfe858200 0x300>;
	106	interrupts = <GIC_SPI 176 IRQ_TYPE_NONE>;
	107	};
	108
	109	vtg_aux: sti-vtg-aux-master@fd348400 {
	110	compatible = "st,vtg";
	111	reg = <0xfd348400 0x400>;
	112	st,slave = <&vtg_aux_slave>;
	113	};
	114
	115
	116	sti-vtac-rx-main@fee82800 {
	117	compatible = "st,vtac-main";
	118	reg = <0xfee82800 0x200>;
	119	clock-names = "vtac";
	120	clocks = <&clk_m_a2_div0 CLK_M_VTAC_MAIN_PHY>;
	121	};
	122
	123	sti-vtac-rx-aux@fee82a00 {
	124	compatible = "st,vtac-aux";
	125	reg = <0xfee82a00 0x200>;
	126	clock-names = "vtac";
	127	clocks = <&clk_m_a2_div0 CLK_M_VTAC_AUX_PHY>;
	128	};
	129
	130	sti-vtac-tx-main@fd349000 {
	131	compatible = "st,vtac-main";
	132	reg = <0xfd349000 0x200>, <0xfd320000 0x10000>;
	133	clock-names = "vtac";
	134	clocks = <&clk_s_a1_hs CLK_S_VTAC_TX_PHY>;
	135	};
	136
	137	sti-vtac-tx-aux@fd349200 {
	138	compatible = "st,vtac-aux";
	139	reg = <0xfd349200 0x200>, <0xfd320000 0x10000>;
	140	clock-names = "vtac";
	141	clocks = <&clk_s_a1_hs CLK_S_VTAC_TX_PHY>;
	142	};
	143
	144	sti-display-subsystem {
	145	compatible = "st,sti-display-subsystem";
	146	ranges;
	147
	148	sti-compositor@fd340000 {
	149	compatible = "st,stih416-compositor";
	150	reg = <0xfd340000 0x1000>;
	151	clock-names = "compo_main", "compo_aux",
	152	"pix_main", "pix_aux";
	153	clocks = <&clk_m_a2_div1 CLK_M_COMPO_MAIN>, <&clk_m_a2_div1 CLK_M_COMPO_AUX>,
	154	<&clockgen_c_vcc CLK_S_PIX_MAIN>, <&clockgen_c_vcc CLK_S_PIX_AUX>;
	155	reset-names = "compo-main", "compo-aux";
	156	resets = <&softreset STIH416_COMPO_M_SOFTRESET>, <&softreset STIH416_COMPO_A_SOFTRESET>;
	157	st,vtg = <&vtg_main>, <&vtg_aux>;
	158	};
	159
	160	sti-tvout@fe000000 {
	161	compatible = "st,stih416-tvout";
	162	reg = <0xfe000000 0x1000>, <0xfe85a000 0x400>, <0xfe830000 0x10000>;
	163	reg-names = "tvout-reg", "hda-reg", "syscfg";
	164	reset-names = "tvout";
	165	resets = <&softreset STIH416_HDTVOUT_SOFTRESET>;
	166	ranges;
	167
	168	sti-hdmi@fe85c000 {
	169	compatible = "st,stih416-hdmi";
	170	reg = <0xfe85c000 0x1000>, <0xfe830000 0x10000>;
	171	reg-names = "hdmi-reg", "syscfg";
	172	interrupts = <GIC_SPI 173 IRQ_TYPE_NONE>;
	173	interrupt-names = "irq";
	174	clock-names = "pix", "tmds", "phy", "audio";
	175	clocks = <&clockgen_c_vcc CLK_S_PIX_HDMI>, <&clockgen_c_vcc CLK_S_TMDS_HDMI>, <&clockgen_c_vcc CLK_S_HDMI_REJECT_PLL>, <&clockgen_b1 CLK_S_PCM_0>;
	176	hdmi,hpd-gpio = <&PIO2 5>;
	177	};
	178
	179	sti-hda@fe85a000 {
	180	compatible = "st,stih416-hda";
	181	reg = <0xfe85a000 0x400>, <0xfe83085c 0x4>;
	182	reg-names = "hda-reg", "video-dacs-ctrl";
	183	clock-names = "pix", "hddac";
	184	clocks = <&clockgen_c_vcc CLK_S_PIX_HD>, <&clockgen_c_vcc CLK_S_HDDAC>;
	185	};
	186	};
	187	};
	188	...
	189	};


diff --git a/drivers/gpu/drm/sti/NOTES b/drivers/gpu/drm/sti/NOTES new file mode 100644 index 000000000000..57e257969198 --- /dev/null +++ b/drivers/gpu/drm/sti/NOTES
@@ -0,0 +1,58 @@
	1	1. stiH display hardware IP
	2	---------------------------
	3	The STMicroelectronics stiH SoCs use a common chain of HW display IP blocks:
	4	- The High Quality Video Display Processor (HQVDP) gets video frames from a
	5	video decoder and does high quality video processing, including scaling.
	6
	7	- The Compositor is a multiplane, dual-mixer (Main & Aux) digital processor. It
	8	has several inputs:
	9	- The graphics planes are internally processed by the Generic Display
	10	Pipeline (GDP).
	11	- The video plug (VID) connects to the HQVDP output.
	12	- The cursor handles ... a cursor.
	13	- The TV OUT pre-formats (convert, clip, round) the compositor output data
	14	- The HDMI / DVO / HD Analog / SD analog IP builds the video signals
	15	- DVO (Digital Video Output) handles a 24bits parallel signal
	16	- The HD analog signal is typically driven by a YCbCr cable, supporting up to
	17	1080i mode.
	18	- The SD analog signal is typically used for legacy TV
	19	- The VTG (Video Timing Generators) build Vsync signals used by the other HW IP
	20	Note that some stiH drivers support only a subset of thee HW IP.
	21
	22	.-------------. .-----------. .-----------.
	23	GPU >-------------+GDP Main \| \| +---+ HDMI +--> HDMI
	24	GPU >-------------+GDP mixer+---+ \| :===========:
	25	GPU >-------------+Cursor \| \| +---+ DVO +--> 24b//
	26	------- \| COMPOSITOR \| \| TV OUT \| :===========:
	27	\| \| \| \| \| +---+ HD analog +--> YCbCr
	28	Vid >--+ HQVDP +--+VID Aux +---+ \| :===========:
	29	dec \| \| \| mixer\| \| +---+ SD analog +--> CVBS
	30	'-------' '-------------' '-----------' '-----------'
	31	.-----------.
	32	\| main+--> Vsync
	33	\| VTG \|
	34	\| aux+--> Vsync
	35	'-----------'
	36
	37	2. DRM / HW mapping
	38	-------------------
	39	These IP are mapped to the DRM objects as following:
	40	- The CRTCs are mapped to the Compositor Main and Aux Mixers
	41	- The Framebuffers and planes are mapped to the Compositor GDP (non video
	42	buffers) and to HQVDP+VID (video buffers)
	43	- The Cursor is mapped to the Compositor Cursor
	44	- The Encoders are mapped to the TVOut
	45	- The Bridges/Connectors are mapped to the HDMI / DVO / HD Analog / SD analog
	46
	47	FB & planes Cursor CRTC Encoders Bridges/Connectors
	48	\| \| \| \| \|
	49	\| \| \| \| \|
	50	\| .-------------. \| .-----------. .-----------. \|
	51	+------------> \|GDP \| Main \| \| \| +-> \| \| HDMI \| <-+
	52	+------------> \|GDP v mixer\|<+ \| \| \| :===========: \|
	53	\| \|Cursor \| \| \| +-> \| \| DVO \| <-+
	54	\| ------- \| COMPOSITOR \| \| \|TV OUT \| \| :===========: \|
	55	\| \| \| \| \| \| \| +-> \| \| HD analog \| <-+
	56	+-> \| HQVDP \| \|VID Aux \|<+ \| \| \| :===========: \|
	57	\| \| \| mixer\| \| +-> \| \| SD analog \| <-+
	58	'-------' '-------------' '-----------' '-----------'