aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorBen Shelton <benjamin.h.shelton@intel.com>2018-04-11 15:21:33 -0400
committerJeff Kirsher <jeffrey.t.kirsher@intel.com>2018-04-24 12:03:23 -0400
commit30d84397affb0fcb11beaf049caabfcb1dac65a6 (patch)
treef544c946b10f1731cda6c3723bd3b38a12d25f49
parent34357a90d5ca8228df4f88b21197f970285b209b (diff)
ice: Do not check INTEVENT bit for OICR interrupts
According to the hardware spec, checking the INTEVENT bit isn't a reliable way to detect if an OICR interrupt has occurred. This is because this bit can be cleared by the hardware/firmware before the interrupt service routine has run. So instead, just check for OICR events every time. Fixes: 940b61af02f4 ("ice: Initialize PF and setup miscellaneous interrupt") Signed-off-by: Ben Shelton <benjamin.h.shelton@intel.com> Signed-off-by: Anirudh Venkataramanan <anirudh.venkataramanan@intel.com> Tested-by: Tony Brelinski <tonyx.brelinski@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
-rw-r--r--drivers/net/ethernet/intel/ice/ice_hw_autogen.h2
-rw-r--r--drivers/net/ethernet/intel/ice/ice_main.c4
2 files changed, 0 insertions, 6 deletions
diff --git a/drivers/net/ethernet/intel/ice/ice_hw_autogen.h b/drivers/net/ethernet/intel/ice/ice_hw_autogen.h
index 1b9e2ef48a9d..499904874b3f 100644
--- a/drivers/net/ethernet/intel/ice/ice_hw_autogen.h
+++ b/drivers/net/ethernet/intel/ice/ice_hw_autogen.h
@@ -121,8 +121,6 @@
121#define PFINT_FW_CTL_CAUSE_ENA_S 30 121#define PFINT_FW_CTL_CAUSE_ENA_S 30
122#define PFINT_FW_CTL_CAUSE_ENA_M BIT(PFINT_FW_CTL_CAUSE_ENA_S) 122#define PFINT_FW_CTL_CAUSE_ENA_M BIT(PFINT_FW_CTL_CAUSE_ENA_S)
123#define PFINT_OICR 0x0016CA00 123#define PFINT_OICR 0x0016CA00
124#define PFINT_OICR_INTEVENT_S 0
125#define PFINT_OICR_INTEVENT_M BIT(PFINT_OICR_INTEVENT_S)
126#define PFINT_OICR_HLP_RDY_S 14 124#define PFINT_OICR_HLP_RDY_S 14
127#define PFINT_OICR_HLP_RDY_M BIT(PFINT_OICR_HLP_RDY_S) 125#define PFINT_OICR_HLP_RDY_M BIT(PFINT_OICR_HLP_RDY_S)
128#define PFINT_OICR_CPM_RDY_S 15 126#define PFINT_OICR_CPM_RDY_S 15
diff --git a/drivers/net/ethernet/intel/ice/ice_main.c b/drivers/net/ethernet/intel/ice/ice_main.c
index 210b7910f1cd..5299caf55a7f 100644
--- a/drivers/net/ethernet/intel/ice/ice_main.c
+++ b/drivers/net/ethernet/intel/ice/ice_main.c
@@ -1722,9 +1722,6 @@ static irqreturn_t ice_misc_intr(int __always_unused irq, void *data)
1722 oicr = rd32(hw, PFINT_OICR); 1722 oicr = rd32(hw, PFINT_OICR);
1723 ena_mask = rd32(hw, PFINT_OICR_ENA); 1723 ena_mask = rd32(hw, PFINT_OICR_ENA);
1724 1724
1725 if (!(oicr & PFINT_OICR_INTEVENT_M))
1726 goto ena_intr;
1727
1728 if (oicr & PFINT_OICR_GRST_M) { 1725 if (oicr & PFINT_OICR_GRST_M) {
1729 u32 reset; 1726 u32 reset;
1730 /* we have a reset warning */ 1727 /* we have a reset warning */
@@ -1782,7 +1779,6 @@ static irqreturn_t ice_misc_intr(int __always_unused irq, void *data)
1782 } 1779 }
1783 ret = IRQ_HANDLED; 1780 ret = IRQ_HANDLED;
1784 1781
1785ena_intr:
1786 /* re-enable interrupt causes that are not handled during this pass */ 1782 /* re-enable interrupt causes that are not handled during this pass */
1787 wr32(hw, PFINT_OICR_ENA, ena_mask); 1783 wr32(hw, PFINT_OICR_ENA, ena_mask);
1788 if (!test_bit(__ICE_DOWN, pf->state)) { 1784 if (!test_bit(__ICE_DOWN, pf->state)) {