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authorJeffy Chen <jeffy.chen@rock-chips.com>2015-12-10 20:30:50 -0500
committerHeiko Stuebner <heiko@sntech.de>2015-12-12 14:04:54 -0500
commit307a2e9ac524bbec707c0e2b47ca50adaecc23f2 (patch)
tree39420e03b8c079069f98d7d42fa6d8fd234ffe17
parent80afed275da42635abd888c0a68b529e88853b04 (diff)
clk: rockchip: add clock controller for rk3228
Add the clock tree definition for the new rk3228 SoC. Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Diffstat
-rw-r--r--drivers/clk/rockchip/Makefile1
-rw-r--r--drivers/clk/rockchip/clk-rk3228.c678
-rw-r--r--drivers/clk/rockchip/clk.h11
3 files changed, 689 insertions, 1 deletions
diff --git a/drivers/clk/rockchip/Makefile b/drivers/clk/rockchip/Makefile
index d599829a021a..80b9a379beb4 100644
--- a/drivers/clk/rockchip/Makefile
+++ b/drivers/clk/rockchip/Makefile
@@ -12,5 +12,6 @@ obj-$(CONFIG_RESET_CONTROLLER) += softrst.o
12 12
13obj-y += clk-rk3036.o 13obj-y += clk-rk3036.o
14obj-y += clk-rk3188.o 14obj-y += clk-rk3188.o
15obj-y += clk-rk3228.o
15obj-y += clk-rk3288.o 16obj-y += clk-rk3288.o
16obj-y += clk-rk3368.o 17obj-y += clk-rk3368.o
diff --git a/drivers/clk/rockchip/clk-rk3228.c b/drivers/clk/rockchip/clk-rk3228.c
new file mode 100644
index 000000000000..87a7e5930f64
--- /dev/null
+++ b/drivers/clk/rockchip/clk-rk3228.c
@@ -0,0 +1,678 @@
1/*
2 * Copyright (c) 2015 Rockchip Electronics Co. Ltd.
3 * Author: Xing Zheng <zhengxing@rock-chips.com>
4 * Jeffy Chen <jeffy.chen@rock-chips.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17#include <linux/clk-provider.h>
18#include <linux/of.h>
19#include <linux/of_address.h>
20#include <linux/syscore_ops.h>
21#include <dt-bindings/clock/rk3228-cru.h>
22#include "clk.h"
23
24#define RK3228_GRF_SOC_STATUS0 0x480
25
26enum rk3228_plls {
27 apll, dpll, cpll, gpll,
28};
29
30static struct rockchip_pll_rate_table rk3228_pll_rates[] = {
31 /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */
32 RK3036_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0),
33 RK3036_PLL_RATE(1584000000, 1, 66, 1, 1, 1, 0),
34 RK3036_PLL_RATE(1560000000, 1, 65, 1, 1, 1, 0),
35 RK3036_PLL_RATE(1536000000, 1, 64, 1, 1, 1, 0),
36 RK3036_PLL_RATE(1512000000, 1, 63, 1, 1, 1, 0),
37 RK3036_PLL_RATE(1488000000, 1, 62, 1, 1, 1, 0),
38 RK3036_PLL_RATE(1464000000, 1, 61, 1, 1, 1, 0),
39 RK3036_PLL_RATE(1440000000, 1, 60, 1, 1, 1, 0),
40 RK3036_PLL_RATE(1416000000, 1, 59, 1, 1, 1, 0),
41 RK3036_PLL_RATE(1392000000, 1, 58, 1, 1, 1, 0),
42 RK3036_PLL_RATE(1368000000, 1, 57, 1, 1, 1, 0),
43 RK3036_PLL_RATE(1344000000, 1, 56, 1, 1, 1, 0),
44 RK3036_PLL_RATE(1320000000, 1, 55, 1, 1, 1, 0),
45 RK3036_PLL_RATE(1296000000, 1, 54, 1, 1, 1, 0),
46 RK3036_PLL_RATE(1272000000, 1, 53, 1, 1, 1, 0),
47 RK3036_PLL_RATE(1248000000, 1, 52, 1, 1, 1, 0),
48 RK3036_PLL_RATE(1200000000, 1, 50, 1, 1, 1, 0),
49 RK3036_PLL_RATE(1188000000, 2, 99, 1, 1, 1, 0),
50 RK3036_PLL_RATE(1104000000, 1, 46, 1, 1, 1, 0),
51 RK3036_PLL_RATE(1100000000, 12, 550, 1, 1, 1, 0),
52 RK3036_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0),
53 RK3036_PLL_RATE(1000000000, 6, 500, 2, 1, 1, 0),
54 RK3036_PLL_RATE( 984000000, 1, 82, 2, 1, 1, 0),
55 RK3036_PLL_RATE( 960000000, 1, 80, 2, 1, 1, 0),
56 RK3036_PLL_RATE( 936000000, 1, 78, 2, 1, 1, 0),
57 RK3036_PLL_RATE( 912000000, 1, 76, 2, 1, 1, 0),
58 RK3036_PLL_RATE( 900000000, 4, 300, 2, 1, 1, 0),
59 RK3036_PLL_RATE( 888000000, 1, 74, 2, 1, 1, 0),
60 RK3036_PLL_RATE( 864000000, 1, 72, 2, 1, 1, 0),
61 RK3036_PLL_RATE( 840000000, 1, 70, 2, 1, 1, 0),
62 RK3036_PLL_RATE( 816000000, 1, 68, 2, 1, 1, 0),
63 RK3036_PLL_RATE( 800000000, 6, 400, 2, 1, 1, 0),
64 RK3036_PLL_RATE( 700000000, 6, 350, 2, 1, 1, 0),
65 RK3036_PLL_RATE( 696000000, 1, 58, 2, 1, 1, 0),
66 RK3036_PLL_RATE( 600000000, 1, 75, 3, 1, 1, 0),
67 RK3036_PLL_RATE( 594000000, 2, 99, 2, 1, 1, 0),
68 RK3036_PLL_RATE( 504000000, 1, 63, 3, 1, 1, 0),
69 RK3036_PLL_RATE( 500000000, 6, 250, 2, 1, 1, 0),
70 RK3036_PLL_RATE( 408000000, 1, 68, 2, 2, 1, 0),
71 RK3036_PLL_RATE( 312000000, 1, 52, 2, 2, 1, 0),
72 RK3036_PLL_RATE( 216000000, 1, 72, 4, 2, 1, 0),
73 RK3036_PLL_RATE( 96000000, 1, 64, 4, 4, 1, 0),
74 { /* sentinel */ },
75};
76
77#define RK3228_DIV_CPU_MASK 0x1f
78#define RK3228_DIV_CPU_SHIFT 8
79
80#define RK3228_DIV_PERI_MASK 0xf
81#define RK3228_DIV_PERI_SHIFT 0
82#define RK3228_DIV_ACLK_MASK 0x7
83#define RK3228_DIV_ACLK_SHIFT 4
84#define RK3228_DIV_HCLK_MASK 0x3
85#define RK3228_DIV_HCLK_SHIFT 8
86#define RK3228_DIV_PCLK_MASK 0x7
87#define RK3228_DIV_PCLK_SHIFT 12
88
89#define RK3228_CLKSEL1(_core_peri_div) \
90 { \
91 .reg = RK2928_CLKSEL_CON(1), \
92 .val = HIWORD_UPDATE(_core_peri_div, RK3228_DIV_PERI_MASK, \
93 RK3228_DIV_PERI_SHIFT) \
94 }
95
96#define RK3228_CPUCLK_RATE(_prate, _core_peri_div) \
97 { \
98 .prate = _prate, \
99 .divs = { \
100 RK3228_CLKSEL1(_core_peri_div), \
101 }, \
102 }
103
104static struct rockchip_cpuclk_rate_table rk3228_cpuclk_rates[] __initdata = {
105 RK3228_CPUCLK_RATE(816000000, 4),
106 RK3228_CPUCLK_RATE(600000000, 4),
107 RK3228_CPUCLK_RATE(312000000, 4),
108};
109
110static const struct rockchip_cpuclk_reg_data rk3228_cpuclk_data = {
111 .core_reg = RK2928_CLKSEL_CON(0),
112 .div_core_shift = 0,
113 .div_core_mask = 0x1f,
114 .mux_core_shift = 6,
115};
116
117PNAME(mux_pll_p) = { "clk_24m", "xin24m" };
118
119PNAME(mux_ddrphy_p) = { "dpll_ddr", "gpll_ddr", "apll_ddr" };
120PNAME(mux_armclk_p) = { "apll_core", "gpll_core", "dpll_core" };
121PNAME(mux_usb480m_phy_p) = { "usb480m_phy0", "usb480m_phy1" };
122PNAME(mux_usb480m_p) = { "usb480m_phy", "xin24m" };
123PNAME(mux_hdmiphy_p) = { "hdmiphy_phy", "xin24m" };
124PNAME(mux_aclk_cpu_src_p) = { "cpll_aclk_cpu", "gpll_aclk_cpu", "hdmiphy_aclk_cpu" };
125
126PNAME(mux_pll_src_4plls_p) = { "cpll", "gpll", "hdmiphy" "usb480m" };
127PNAME(mux_pll_src_3plls_p) = { "cpll", "gpll", "hdmiphy" };
128PNAME(mux_pll_src_2plls_p) = { "cpll", "gpll" };
129PNAME(mux_sclk_hdmi_cec_p) = { "cpll", "gpll", "xin24m" };
130PNAME(mux_aclk_peri_src_p) = { "cpll_peri", "gpll_peri", "hdmiphy_peri" };
131PNAME(mux_mmc_src_p) = { "cpll", "gpll", "xin24m", "usb480m" };
132PNAME(mux_pll_src_cpll_gpll_usb480m_p) = { "cpll", "gpll", "usb480m" };
133
134PNAME(mux_sclk_rga_p) = { "gpll", "cpll", "sclk_rga_src" };
135
136PNAME(mux_sclk_vop_src_p) = { "gpll_vop", "cpll_vop" };
137PNAME(mux_dclk_vop_p) = { "hdmiphy", "sclk_vop_pre" };
138
139PNAME(mux_i2s0_p) = { "i2s0_src", "i2s0_frac", "ext_i2s", "xin12m" };
140PNAME(mux_i2s1_pre_p) = { "i2s1_src", "i2s1_frac", "ext_i2s", "xin12m" };
141PNAME(mux_i2s_out_p) = { "i2s1_pre", "xin12m" };
142PNAME(mux_i2s2_p) = { "i2s2_src", "i2s2_frac", "xin12m" };
143PNAME(mux_sclk_spdif_p) = { "sclk_spdif_src", "spdif_frac", "xin12m" };
144
145PNAME(mux_aclk_gpu_pre_p) = { "cpll_gpu", "gpll_gpu", "hdmiphy_gpu", "usb480m_gpu" };
146
147PNAME(mux_uart0_p) = { "uart0_src", "uart0_frac", "xin24m" };
148PNAME(mux_uart1_p) = { "uart1_src", "uart1_frac", "xin24m" };
149PNAME(mux_uart2_p) = { "uart2_src", "uart2_frac", "xin24m" };
150
151PNAME(mux_sclk_macphy_50m_p) = { "ext_gmac", "phy_50m_out" };
152PNAME(mux_sclk_gmac_pre_p) = { "sclk_gmac_src", "sclk_macphy_50m" };
153PNAME(mux_sclk_macphy_p) = { "sclk_gmac_src", "ext_gmac" };
154
155static struct rockchip_pll_clock rk3228_pll_clks[] __initdata = {
156 [apll] = PLL(pll_rk3036, PLL_APLL, "apll", mux_pll_p, 0, RK2928_PLL_CON(0),
157 RK2928_MODE_CON, 0, 7, 0, rk3228_pll_rates),
158 [dpll] = PLL(pll_rk3036, PLL_DPLL, "dpll", mux_pll_p, 0, RK2928_PLL_CON(3),
159 RK2928_MODE_CON, 4, 6, 0, NULL),
160 [cpll] = PLL(pll_rk3036, PLL_CPLL, "cpll", mux_pll_p, 0, RK2928_PLL_CON(6),
161 RK2928_MODE_CON, 8, 8, 0, NULL),
162 [gpll] = PLL(pll_rk3036, PLL_GPLL, "gpll", mux_pll_p, 0, RK2928_PLL_CON(9),
163 RK2928_MODE_CON, 12, 9, ROCKCHIP_PLL_SYNC_RATE, rk3228_pll_rates),
164};
165
166#define MFLAGS CLK_MUX_HIWORD_MASK
167#define DFLAGS CLK_DIVIDER_HIWORD_MASK
168#define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE)
169
170static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = {
171 /*
172 * Clock-Architecture Diagram 1
173 */
174
175 DIV(0, "clk_24m", "xin24m", CLK_IGNORE_UNUSED,
176 RK2928_CLKSEL_CON(4), 8, 5, DFLAGS),
177
178 /* PD_DDR */
179 GATE(0, "apll_ddr", "apll", CLK_IGNORE_UNUSED,
180 RK2928_CLKGATE_CON(0), 2, GFLAGS),
181 GATE(0, "dpll_ddr", "dpll", CLK_IGNORE_UNUSED,
182 RK2928_CLKGATE_CON(0), 2, GFLAGS),
183 GATE(0, "gpll_ddr", "gpll", CLK_IGNORE_UNUSED,
184 RK2928_CLKGATE_CON(0), 2, GFLAGS),
185 COMPOSITE(0, "ddrphy4x", mux_ddrphy_p, CLK_IGNORE_UNUSED,
186 RK2928_CLKSEL_CON(26), 8, 2, MFLAGS, 0, 3, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
187 RK2928_CLKGATE_CON(7), 1, GFLAGS),
188 GATE(0, "ddrc", "ddrphy_pre", CLK_IGNORE_UNUSED,
189 RK2928_CLKGATE_CON(8), 5, GFLAGS),
190 GATE(0, "ddrphy", "ddrphy_pre", CLK_IGNORE_UNUSED,
191 RK2928_CLKGATE_CON(7), 0, GFLAGS),
192
193 /* PD_CORE */
194 GATE(0, "dpll_core", "dpll", CLK_IGNORE_UNUSED,
195 RK2928_CLKGATE_CON(0), 6, GFLAGS),
196 GATE(0, "apll_core", "apll", CLK_IGNORE_UNUSED,
197 RK2928_CLKGATE_CON(0), 6, GFLAGS),
198 GATE(0, "gpll_core", "gpll", CLK_IGNORE_UNUSED,
199 RK2928_CLKGATE_CON(0), 6, GFLAGS),
200 COMPOSITE_NOMUX(0, "pclk_dbg", "armclk", CLK_IGNORE_UNUSED,
201 RK2928_CLKSEL_CON(1), 0, 4, DFLAGS | CLK_DIVIDER_READ_ONLY,
202 RK2928_CLKGATE_CON(4), 1, GFLAGS),
203 COMPOSITE_NOMUX(0, "armcore", "armclk", CLK_IGNORE_UNUSED,
204 RK2928_CLKSEL_CON(1), 4, 3, DFLAGS | CLK_DIVIDER_READ_ONLY,
205 RK2928_CLKGATE_CON(4), 0, GFLAGS),
206
207 /* PD_MISC */
208 MUX(0, "hdmiphy", mux_hdmiphy_p, CLK_SET_RATE_PARENT,
209 RK2928_MISC_CON, 13, 1, MFLAGS),
210 MUX(0, "usb480m_phy", mux_usb480m_phy_p, CLK_SET_RATE_PARENT,
211 RK2928_MISC_CON, 14, 1, MFLAGS),
212 MUX(0, "usb480m", mux_usb480m_p, CLK_SET_RATE_PARENT,
213 RK2928_MISC_CON, 15, 1, MFLAGS),
214
215 /* PD_BUS */
216 GATE(0, "hdmiphy_aclk_cpu", "hdmiphy", CLK_IGNORE_UNUSED,
217 RK2928_CLKGATE_CON(0), 1, GFLAGS),
218 GATE(0, "gpll_aclk_cpu", "gpll", CLK_IGNORE_UNUSED,
219 RK2928_CLKGATE_CON(0), 1, GFLAGS),
220 GATE(0, "cpll_aclk_cpu", "cpll", CLK_IGNORE_UNUSED,
221 RK2928_CLKGATE_CON(0), 1, GFLAGS),
222 COMPOSITE_NOGATE(0, "aclk_cpu_src", mux_aclk_cpu_src_p, 0,
223 RK2928_CLKSEL_CON(0), 13, 2, MFLAGS, 8, 5, DFLAGS),
224 GATE(ARMCLK, "aclk_cpu", "aclk_cpu_src", 0,
225 RK2928_CLKGATE_CON(6), 0, GFLAGS),
226 COMPOSITE_NOMUX(0, "hclk_cpu", "aclk_cpu_src", 0,
227 RK2928_CLKSEL_CON(1), 8, 2, DFLAGS,
228 RK2928_CLKGATE_CON(6), 1, GFLAGS),
229 COMPOSITE_NOMUX(0, "pclk_bus_src", "aclk_cpu_src", 0,
230 RK2928_CLKSEL_CON(1), 12, 3, DFLAGS,
231 RK2928_CLKGATE_CON(6), 2, GFLAGS),
232 GATE(0, "pclk_cpu", "pclk_bus_src", 0,
233 RK2928_CLKGATE_CON(6), 3, GFLAGS),
234 GATE(0, "pclk_phy_pre", "pclk_bus_src", 0,
235 RK2928_CLKGATE_CON(6), 4, GFLAGS),
236 GATE(0, "pclk_ddr_pre", "pclk_bus_src", 0,
237 RK2928_CLKGATE_CON(6), 13, GFLAGS),
238
239 /* PD_VIDEO */
240 COMPOSITE(0, "aclk_vpu_pre", mux_pll_src_4plls_p, 0,
241 RK2928_CLKSEL_CON(32), 5, 2, MFLAGS, 0, 5, DFLAGS,
242 RK2928_CLKGATE_CON(3), 11, GFLAGS),
243 GATE(0, "hclk_vpu_src", "aclk_vpu_pre", 0,
244 RK2928_CLKGATE_CON(4), 4, GFLAGS),
245
246 COMPOSITE(0, "aclk_rkvdec_pre", mux_pll_src_4plls_p, 0,
247 RK2928_CLKSEL_CON(28), 6, 2, MFLAGS, 0, 5, DFLAGS,
248 RK2928_CLKGATE_CON(3), 2, GFLAGS),
249 GATE(0, "hclk_rkvdec_src", "aclk_rkvdec_pre", 0,
250 RK2928_CLKGATE_CON(4), 5, GFLAGS),
251
252 COMPOSITE(0, "sclk_vdec_cabac", mux_pll_src_4plls_p, 0,
253 RK2928_CLKSEL_CON(28), 14, 2, MFLAGS, 8, 5, DFLAGS,
254 RK2928_CLKGATE_CON(3), 3, GFLAGS),
255
256 COMPOSITE(0, "sclk_vdec_core", mux_pll_src_4plls_p, 0,
257 RK2928_CLKSEL_CON(34), 13, 2, MFLAGS, 8, 5, DFLAGS,
258 RK2928_CLKGATE_CON(3), 4, GFLAGS),
259
260 /* PD_VIO */
261 COMPOSITE(0, "aclk_iep_pre", mux_pll_src_4plls_p, 0,
262 RK2928_CLKSEL_CON(31), 5, 2, MFLAGS, 0, 5, DFLAGS,
263 RK2928_CLKGATE_CON(3), 0, GFLAGS),
264 DIV(0, "hclk_vio_pre", "aclk_iep_pre", 0,
265 RK2928_CLKSEL_CON(2), 0, 5, DFLAGS),
266
267 COMPOSITE(0, "aclk_hdcp_pre", mux_pll_src_4plls_p, 0,
268 RK2928_CLKSEL_CON(31), 13, 2, MFLAGS, 8, 5, DFLAGS,
269 RK2928_CLKGATE_CON(1), 4, GFLAGS),
270
271 MUX(0, "sclk_rga_src", mux_pll_src_4plls_p, 0,
272 RK2928_CLKSEL_CON(33), 13, 2, MFLAGS),
273 COMPOSITE_NOMUX(0, "aclk_rga_pre", "sclk_rga_src", 0,
274 RK2928_CLKSEL_CON(33), 8, 5, DFLAGS,
275 RK2928_CLKGATE_CON(1), 2, GFLAGS),
276 COMPOSITE(0, "sclk_rga", mux_sclk_rga_p, 0,
277 RK2928_CLKSEL_CON(22), 5, 2, MFLAGS, 0, 5, DFLAGS,
278 RK2928_CLKGATE_CON(3), 6, GFLAGS),
279
280 COMPOSITE(0, "aclk_vop_pre", mux_pll_src_4plls_p, 0,
281 RK2928_CLKSEL_CON(33), 5, 2, MFLAGS, 0, 5, DFLAGS,
282 RK2928_CLKGATE_CON(1), 1, GFLAGS),
283
284 COMPOSITE(0, "sclk_hdcp", mux_pll_src_3plls_p, 0,
285 RK2928_CLKSEL_CON(23), 14, 2, MFLAGS, 8, 6, DFLAGS,
286 RK2928_CLKGATE_CON(3), 5, GFLAGS),
287
288 GATE(0, "sclk_hdmi_hdcp", "xin24m", 0,
289 RK2928_CLKGATE_CON(3), 7, GFLAGS),
290
291 COMPOSITE(0, "sclk_hdmi_cec", mux_sclk_hdmi_cec_p, 0,
292 RK2928_CLKSEL_CON(21), 14, 2, MFLAGS, 0, 14, DFLAGS,
293 RK2928_CLKGATE_CON(3), 8, GFLAGS),
294
295 /* PD_PERI */
296 GATE(0, "cpll_peri", "cpll", CLK_IGNORE_UNUSED,
297 RK2928_CLKGATE_CON(2), 0, GFLAGS),
298 GATE(0, "gpll_peri", "gpll", CLK_IGNORE_UNUSED,
299 RK2928_CLKGATE_CON(2), 0, GFLAGS),
300 GATE(0, "hdmiphy_peri", "hdmiphy", CLK_IGNORE_UNUSED,
301 RK2928_CLKGATE_CON(2), 0, GFLAGS),
302 COMPOSITE_NOGATE(0, "aclk_peri_src", mux_aclk_peri_src_p, 0,
303 RK2928_CLKSEL_CON(10), 10, 2, MFLAGS, 0, 5, DFLAGS),
304 COMPOSITE_NOMUX(PCLK_PERI, "pclk_peri", "aclk_peri_src", 0,
305 RK2928_CLKSEL_CON(10), 12, 3, DFLAGS,
306 RK2928_CLKGATE_CON(5), 2, GFLAGS),
307 COMPOSITE_NOMUX(HCLK_PERI, "hclk_peri", "aclk_peri_src", 0,
308 RK2928_CLKSEL_CON(10), 8, 2, DFLAGS,
309 RK2928_CLKGATE_CON(5), 1, GFLAGS),
310 GATE(ACLK_PERI, "aclk_peri", "aclk_peri_src", 0,
311 RK2928_CLKGATE_CON(5), 0, GFLAGS),
312
313 GATE(SCLK_TIMER0, "sclk_timer0", "xin24m", 0,
314 RK2928_CLKGATE_CON(6), 5, GFLAGS),
315 GATE(SCLK_TIMER1, "sclk_timer1", "xin24m", 0,
316 RK2928_CLKGATE_CON(6), 6, GFLAGS),
317 GATE(SCLK_TIMER2, "sclk_timer2", "xin24m", 0,
318 RK2928_CLKGATE_CON(6), 7, GFLAGS),
319 GATE(SCLK_TIMER3, "sclk_timer3", "xin24m", 0,
320 RK2928_CLKGATE_CON(6), 8, GFLAGS),
321 GATE(SCLK_TIMER4, "sclk_timer4", "xin24m", 0,
322 RK2928_CLKGATE_CON(6), 9, GFLAGS),
323 GATE(SCLK_TIMER5, "sclk_timer5", "xin24m", 0,
324 RK2928_CLKGATE_CON(6), 10, GFLAGS),
325
326 COMPOSITE(0, "sclk_crypto", mux_pll_src_2plls_p, 0,
327 RK2928_CLKSEL_CON(24), 5, 1, MFLAGS, 0, 5, DFLAGS,
328 RK2928_CLKGATE_CON(2), 7, GFLAGS),
329
330 COMPOSITE(0, "sclk_tsp", mux_pll_src_2plls_p, 0,
331 RK2928_CLKSEL_CON(22), 15, 1, MFLAGS, 8, 5, DFLAGS,
332 RK2928_CLKGATE_CON(2), 6, GFLAGS),
333
334 GATE(0, "sclk_hsadc", "ext_hsadc", 0,
335 RK3288_CLKGATE_CON(10), 12, GFLAGS),
336
337 COMPOSITE(0, "sclk_wifi", mux_pll_src_cpll_gpll_usb480m_p, 0,
338 RK2928_CLKSEL_CON(23), 5, 2, MFLAGS, 0, 6, DFLAGS,
339 RK2928_CLKGATE_CON(2), 15, GFLAGS),
340
341 COMPOSITE(SCLK_SDMMC, "sclk_sdmmc0", mux_mmc_src_p, 0,
342 RK2928_CLKSEL_CON(11), 8, 2, MFLAGS, 0, 8, DFLAGS,
343 RK2928_CLKGATE_CON(2), 11, GFLAGS),
344
345 COMPOSITE_NODIV(0, "sclk_sdio_src", mux_mmc_src_p, 0,
346 RK2928_CLKSEL_CON(11), 10, 2, MFLAGS,
347 RK2928_CLKGATE_CON(2), 13, GFLAGS),
348 DIV(SCLK_SDIO, "sclk_sdio", "sclk_sdio_src", 0,
349 RK2928_CLKSEL_CON(12), 0, 8, DFLAGS),
350
351 COMPOSITE_NODIV(0, "sclk_emmc_src", mux_mmc_src_p, 0,
352 RK2928_CLKSEL_CON(11), 12, 2, MFLAGS,
353 RK2928_CLKGATE_CON(2), 14, GFLAGS),
354 DIV(SCLK_EMMC, "sclk_emmc", "sclk_emmc_src", 0,
355 RK2928_CLKSEL_CON(12), 8, 8, DFLAGS),
356
357 /*
358 * Clock-Architecture Diagram 2
359 */
360
361 GATE(0, "gpll_vop", "gpll", 0,
362 RK2928_CLKGATE_CON(3), 1, GFLAGS),
363 GATE(0, "cpll_vop", "cpll", 0,
364 RK2928_CLKGATE_CON(3), 1, GFLAGS),
365 MUX(0, "sclk_vop_src", mux_sclk_vop_src_p, 0,
366 RK2928_CLKSEL_CON(27), 0, 1, MFLAGS),
367 DIV(0, "dclk_hdmiphy", "sclk_vop_src", 0,
368 RK2928_CLKSEL_CON(29), 0, 3, DFLAGS),
369 DIV(0, "sclk_vop_pre", "sclk_vop_src", 0,
370 RK2928_CLKSEL_CON(27), 8, 8, DFLAGS),
371 MUX(0, "dclk_vop", mux_dclk_vop_p, 0,
372 RK2928_CLKSEL_CON(27), 1, 1, MFLAGS),
373
374 COMPOSITE(0, "i2s0_src", mux_pll_src_2plls_p, 0,
375 RK2928_CLKSEL_CON(9), 15, 1, MFLAGS, 0, 7, DFLAGS,
376 RK2928_CLKGATE_CON(0), 3, GFLAGS),
377 COMPOSITE_FRAC(0, "i2s0_frac", "i2s0_src", CLK_SET_RATE_PARENT,
378 RK3288_CLKSEL_CON(8), 0,
379 RK3288_CLKGATE_CON(0), 4, GFLAGS),
380 COMPOSITE_NODIV(SCLK_I2S0, "sclk_i2s0", mux_i2s0_p, 0,
381 RK2928_CLKSEL_CON(9), 8, 2, MFLAGS,
382 RK2928_CLKGATE_CON(0), 5, GFLAGS),
383
384 COMPOSITE(0, "i2s1_src", mux_pll_src_2plls_p, 0,
385 RK2928_CLKSEL_CON(3), 15, 1, MFLAGS, 0, 7, DFLAGS,
386 RK2928_CLKGATE_CON(0), 10, GFLAGS),
387 COMPOSITE_FRAC(0, "i2s1_frac", "i2s1_src", CLK_SET_RATE_PARENT,
388 RK3288_CLKSEL_CON(7), 0,
389 RK3288_CLKGATE_CON(0), 11, GFLAGS),
390 MUX(0, "i2s1_pre", mux_i2s1_pre_p, 0,
391 RK2928_CLKSEL_CON(3), 8, 2, MFLAGS),
392 GATE(SCLK_I2S1, "sclk_i2s1", "i2s1_pre", 0,
393 RK2928_CLKGATE_CON(0), 14, GFLAGS),
394 COMPOSITE_NODIV(SCLK_I2S_OUT, "i2s_out", mux_i2s_out_p, 0,
395 RK2928_CLKSEL_CON(3), 12, 1, MFLAGS,
396 RK2928_CLKGATE_CON(0), 13, GFLAGS),
397
398 COMPOSITE(0, "i2s2_src", mux_pll_src_2plls_p, 0,
399 RK2928_CLKSEL_CON(16), 15, 1, MFLAGS, 0, 7, DFLAGS,
400 RK2928_CLKGATE_CON(0), 7, GFLAGS),
401 COMPOSITE_FRAC(0, "i2s2_frac", "i2s2_src", CLK_SET_RATE_PARENT,
402 RK3288_CLKSEL_CON(30), 0,
403 RK3288_CLKGATE_CON(0), 8, GFLAGS),
404 COMPOSITE_NODIV(SCLK_I2S2, "sclk_i2s2", mux_i2s2_p, 0,
405 RK2928_CLKSEL_CON(16), 8, 2, MFLAGS,
406 RK2928_CLKGATE_CON(0), 9, GFLAGS),
407
408 COMPOSITE(0, "sclk_spdif_src", mux_pll_src_2plls_p, 0,
409 RK2928_CLKSEL_CON(6), 15, 1, MFLAGS, 0, 7, DFLAGS,
410 RK2928_CLKGATE_CON(2), 10, GFLAGS),
411 COMPOSITE_FRAC(0, "spdif_frac", "sclk_spdif_src", CLK_SET_RATE_PARENT,
412 RK3288_CLKSEL_CON(20), 0,
413 RK3288_CLKGATE_CON(2), 12, GFLAGS),
414 MUX(SCLK_SPDIF, "sclk_spdif", mux_sclk_spdif_p, 0,
415 RK2928_CLKSEL_CON(6), 8, 2, MFLAGS),
416
417 GATE(0, "jtag", "ext_jtag", 0,
418 RK2928_CLKGATE_CON(1), 3, GFLAGS),
419
420 GATE(0, "sclk_otgphy0", "xin24m", 0,
421 RK2928_CLKGATE_CON(1), 5, GFLAGS),
422 GATE(0, "sclk_otgphy1", "xin24m", 0,
423 RK2928_CLKGATE_CON(1), 6, GFLAGS),
424
425 COMPOSITE_NOMUX(0, "sclk_tsadc", "xin24m", 0,
426 RK2928_CLKSEL_CON(24), 6, 10, DFLAGS,
427 RK2928_CLKGATE_CON(2), 8, GFLAGS),
428
429 GATE(0, "cpll_gpu", "cpll", 0,
430 RK2928_CLKGATE_CON(3), 13, GFLAGS),
431 GATE(0, "gpll_gpu", "gpll", 0,
432 RK2928_CLKGATE_CON(3), 13, GFLAGS),
433 GATE(0, "hdmiphy_gpu", "hdmiphy", 0,
434 RK2928_CLKGATE_CON(3), 13, GFLAGS),
435 GATE(0, "usb480m_gpu", "usb480m", 0,
436 RK2928_CLKGATE_CON(3), 13, GFLAGS),
437 COMPOSITE_NOGATE(0, "aclk_gpu_pre", mux_aclk_gpu_pre_p, 0,
438 RK2928_CLKSEL_CON(34), 5, 2, MFLAGS, 0, 5, DFLAGS),
439
440 COMPOSITE(SCLK_SPI0, "sclk_spi0", mux_pll_src_2plls_p, 0,
441 RK2928_CLKSEL_CON(25), 8, 1, MFLAGS, 0, 7, DFLAGS,
442 RK2928_CLKGATE_CON(2), 9, GFLAGS),
443
444 /* PD_UART */
445 COMPOSITE(0, "uart0_src", mux_pll_src_cpll_gpll_usb480m_p, 0,
446 RK2928_CLKSEL_CON(13), 12, 2, MFLAGS, 0, 7, DFLAGS,
447 RK2928_CLKGATE_CON(1), 8, GFLAGS),
448 COMPOSITE(0, "uart1_src", mux_pll_src_cpll_gpll_usb480m_p, 0,
449 RK2928_CLKSEL_CON(14), 12, 2, MFLAGS, 0, 7, DFLAGS,
450 RK2928_CLKGATE_CON(1), 10, GFLAGS),
451 COMPOSITE(0, "uart2_src", mux_pll_src_cpll_gpll_usb480m_p,
452 0, RK2928_CLKSEL_CON(15), 12, 2,
453 MFLAGS, 0, 7, DFLAGS, RK2928_CLKGATE_CON(1), 12, GFLAGS),
454 COMPOSITE_FRAC(0, "uart0_frac", "uart0_src", CLK_SET_RATE_PARENT,
455 RK2928_CLKSEL_CON(17), 0,
456 RK2928_CLKGATE_CON(1), 9, GFLAGS),
457 COMPOSITE_FRAC(0, "uart1_frac", "uart1_src", CLK_SET_RATE_PARENT,
458 RK2928_CLKSEL_CON(18), 0,
459 RK2928_CLKGATE_CON(1), 11, GFLAGS),
460 COMPOSITE_FRAC(0, "uart2_frac", "uart2_src", CLK_SET_RATE_PARENT,
461 RK2928_CLKSEL_CON(19), 0,
462 RK2928_CLKGATE_CON(1), 13, GFLAGS),
463 MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT,
464 RK2928_CLKSEL_CON(13), 8, 2, MFLAGS),
465 MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT,
466 RK2928_CLKSEL_CON(14), 8, 2, MFLAGS),
467 MUX(SCLK_UART2, "sclk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT,
468 RK2928_CLKSEL_CON(15), 8, 2, MFLAGS),
469
470 COMPOSITE(SCLK_NANDC, "sclk_nandc", mux_pll_src_2plls_p, 0,
471 RK2928_CLKSEL_CON(2), 14, 1, MFLAGS, 8, 5, DFLAGS,
472 RK2928_CLKGATE_CON(1), 0, GFLAGS),
473
474 COMPOSITE(0, "sclk_gmac_src", mux_pll_src_2plls_p, 0,
475 RK2928_CLKSEL_CON(5), 7, 1, MFLAGS, 0, 5, DFLAGS,
476 RK2928_CLKGATE_CON(1), 7, GFLAGS),
477 MUX(0, "sclk_macphy_50m", mux_sclk_macphy_50m_p, 0,
478 RK2928_CLKSEL_CON(29), 10, 1, MFLAGS),
479 MUX(0, "sclk_gmac_pre", mux_sclk_gmac_pre_p, 0,
480 RK2928_CLKSEL_CON(5), 5, 1, MFLAGS),
481 GATE(0, "sclk_mac_refout", "sclk_gmac_pre", 0,
482 RK2928_CLKGATE_CON(5), 4, GFLAGS),
483 GATE(0, "sclk_mac_ref", "sclk_gmac_pre", 0,
484 RK2928_CLKGATE_CON(5), 3, GFLAGS),
485 GATE(0, "sclk_mac_rx", "sclk_gmac_pre", 0,
486 RK2928_CLKGATE_CON(5), 5, GFLAGS),
487 GATE(0, "sclk_mac_tx", "sclk_gmac_pre", 0,
488 RK2928_CLKGATE_CON(5), 6, GFLAGS),
489 COMPOSITE(0, "sclk_macphy", mux_sclk_macphy_p, 0,
490 RK2928_CLKSEL_CON(29), 12, 1, MFLAGS, 8, 2, DFLAGS,
491 RK2928_CLKGATE_CON(5), 7, GFLAGS),
492 COMPOSITE(0, "sclk_gmac_out", mux_pll_src_2plls_p, 0,
493 RK2928_CLKSEL_CON(5), 15, 1, MFLAGS, 8, 5, DFLAGS,
494 RK2928_CLKGATE_CON(2), 2, GFLAGS),
495
496 /*
497 * Clock-Architecture Diagram 3
498 */
499
500 /* PD_VOP */
501 GATE(0, "aclk_rga", "aclk_rga_pre", 0, RK2928_CLKGATE_CON(13), 0, GFLAGS),
502 GATE(0, "aclk_rga_noc", "aclk_rga_pre", 0, RK2928_CLKGATE_CON(13), 11, GFLAGS),
503 GATE(0, "aclk_iep", "aclk_iep_pre", 0, RK2928_CLKGATE_CON(13), 2, GFLAGS),
504 GATE(0, "aclk_iep_noc", "aclk_iep_pre", 0, RK2928_CLKGATE_CON(13), 9, GFLAGS),
505
506 GATE(0, "aclk_vop", "aclk_vop_pre", 0, RK2928_CLKGATE_CON(13), 5, GFLAGS),
507 GATE(0, "aclk_vop_noc", "aclk_vop_pre", 0, RK2928_CLKGATE_CON(13), 12, GFLAGS),
508
509 GATE(0, "aclk_hdcp", "aclk_hdcp_pre", 0, RK2928_CLKGATE_CON(14), 10, GFLAGS),
510 GATE(0, "aclk_hdcp_noc", "aclk_hdcp_pre", 0, RK2928_CLKGATE_CON(13), 10, GFLAGS),
511
512 GATE(0, "hclk_rga", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(13), 1, GFLAGS),
513 GATE(0, "hclk_iep", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(13), 3, GFLAGS),
514 GATE(0, "hclk_vop", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(13), 6, GFLAGS),
515 GATE(0, "hclk_vio_ahb_arbi", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(13), 7, GFLAGS),
516 GATE(0, "hclk_vio_noc", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(13), 8, GFLAGS),
517 GATE(0, "hclk_vop_noc", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(13), 13, GFLAGS),
518 GATE(0, "hclk_vio_h2p", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(14), 7, GFLAGS),
519 GATE(0, "hclk_hdcp_mmu", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(14), 12, GFLAGS),
520 GATE(0, "pclk_hdmi_ctrl", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(14), 6, GFLAGS),
521 GATE(0, "pclk_vio_h2p", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(14), 8, GFLAGS),
522 GATE(0, "pclk_hdcp", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(14), 11, GFLAGS),
523
524 /* PD_PERI */
525 GATE(0, "aclk_peri_noc", "aclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(12), 0, GFLAGS),
526 GATE(0, "aclk_gmac", "aclk_peri", 0, RK2928_CLKGATE_CON(11), 4, GFLAGS),
527
528 GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 0, GFLAGS),
529 GATE(HCLK_SDIO, "hclk_sdio", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 1, GFLAGS),
530 GATE(HCLK_EMMC, "hclk_emmc", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 2, GFLAGS),
531 GATE(HCLK_NANDC, "hclk_nandc", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 3, GFLAGS),
532 GATE(0, "hclk_host0", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 6, GFLAGS),
533 GATE(0, "hclk_host0_arb", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 7, GFLAGS),
534 GATE(0, "hclk_host1", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 8, GFLAGS),
535 GATE(0, "hclk_host1_arb", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 9, GFLAGS),
536 GATE(0, "hclk_host2", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 10, GFLAGS),
537 GATE(0, "hclk_otg", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 12, GFLAGS),
538 GATE(0, "hclk_otg_pmu", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 13, GFLAGS),
539 GATE(0, "hclk_host2_arb", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 14, GFLAGS),
540 GATE(0, "hclk_peri_noc", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(12), 1, GFLAGS),
541
542 GATE(0, "pclk_gmac", "pclk_peri", 0, RK2928_CLKGATE_CON(11), 5, GFLAGS),
543 GATE(0, "pclk_peri_noc", "pclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(12), 2, GFLAGS),
544
545 /* PD_GPU */
546 GATE(0, "aclk_gpu", "aclk_gpu_pre", 0, RK2928_CLKGATE_CON(13), 14, GFLAGS),
547 GATE(0, "aclk_gpu_noc", "aclk_gpu_pre", 0, RK2928_CLKGATE_CON(13), 15, GFLAGS),
548
549 /* PD_BUS */
550 GATE(0, "sclk_initmem_mbist", "aclk_cpu", 0, RK2928_CLKGATE_CON(8), 1, GFLAGS),
551 GATE(0, "aclk_initmem", "aclk_cpu", 0, RK2928_CLKGATE_CON(8), 0, GFLAGS),
552 GATE(ACLK_DMAC, "aclk_dmac_bus", "aclk_cpu", 0, RK2928_CLKGATE_CON(8), 2, GFLAGS),
553 GATE(0, "aclk_bus_noc", "aclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(10), 1, GFLAGS),
554
555 GATE(0, "hclk_rom", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 3, GFLAGS),
556 GATE(0, "hclk_i2s0_8ch", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 7, GFLAGS),
557 GATE(0, "hclk_i2s1_8ch", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 8, GFLAGS),
558 GATE(0, "hclk_i2s2_2ch", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 9, GFLAGS),
559 GATE(0, "hclk_spdif_8ch", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 10, GFLAGS),
560 GATE(0, "hclk_tsp", "hclk_cpu", 0, RK2928_CLKGATE_CON(10), 11, GFLAGS),
561 GATE(0, "hclk_crypto_mst", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 11, GFLAGS),
562 GATE(0, "hclk_crypto_slv", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 12, GFLAGS),
563
564 GATE(0, "pclk_ddrupctl", "pclk_ddr_pre", 0, RK2928_CLKGATE_CON(8), 4, GFLAGS),
565 GATE(0, "pclk_ddrmon", "pclk_ddr_pre", 0, RK2928_CLKGATE_CON(8), 6, GFLAGS),
566 GATE(0, "pclk_msch_noc", "pclk_ddr_pre", 0, RK2928_CLKGATE_CON(10), 2, GFLAGS),
567
568 GATE(0, "pclk_efuse_1024", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 13, GFLAGS),
569 GATE(0, "pclk_efuse_256", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 14, GFLAGS),
570 GATE(PCLK_I2C0, "pclk_i2c0", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 15, GFLAGS),
571 GATE(PCLK_I2C1, "pclk_i2c1", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 0, GFLAGS),
572 GATE(PCLK_I2C2, "pclk_i2c2", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 1, GFLAGS),
573 GATE(PCLK_I2C3, "pclk_i2c3", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 2, GFLAGS),
574 GATE(PCLK_TIMER, "pclk_timer0", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 4, GFLAGS),
575 GATE(0, "pclk_stimer", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 5, GFLAGS),
576 GATE(PCLK_SPI0, "pclk_spi0", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 6, GFLAGS),
577 GATE(PCLK_PWM, "pclk_rk_pwm", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 7, GFLAGS),
578 GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 8, GFLAGS),
579 GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 9, GFLAGS),
580 GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 10, GFLAGS),
581 GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 11, GFLAGS),
582 GATE(PCLK_UART0, "pclk_uart0", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 12, GFLAGS),
583 GATE(PCLK_UART1, "pclk_uart1", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 13, GFLAGS),
584 GATE(PCLK_UART2, "pclk_uart2", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 14, GFLAGS),
585 GATE(0, "pclk_tsadc", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 15, GFLAGS),
586 GATE(PCLK_GRF, "pclk_grf", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(10), 0, GFLAGS),
587 GATE(0, "pclk_cru", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(10), 1, GFLAGS),
588 GATE(0, "pclk_sgrf", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(10), 2, GFLAGS),
589 GATE(0, "pclk_sim", "pclk_cpu", 0, RK2928_CLKGATE_CON(10), 3, GFLAGS),
590
591 GATE(0, "pclk_ddrphy", "pclk_phy_pre", 0, RK2928_CLKGATE_CON(10), 3, GFLAGS),
592 GATE(0, "pclk_acodecphy", "pclk_phy_pre", 0, RK2928_CLKGATE_CON(10), 5, GFLAGS),
593 GATE(0, "pclk_hdmiphy", "pclk_phy_pre", 0, RK2928_CLKGATE_CON(10), 7, GFLAGS),
594 GATE(0, "pclk_vdacphy", "pclk_phy_pre", 0, RK2928_CLKGATE_CON(10), 8, GFLAGS),
595 GATE(0, "pclk_phy_noc", "pclk_phy_pre", 0, RK2928_CLKGATE_CON(10), 9, GFLAGS),
596
597 GATE(0, "aclk_vpu", "aclk_vpu_pre", 0, RK2928_CLKGATE_CON(15), 0, GFLAGS),
598 GATE(0, "aclk_vpu_noc", "aclk_vpu_pre", 0, RK2928_CLKGATE_CON(15), 4, GFLAGS),
599 GATE(0, "aclk_rkvdec", "aclk_rkvdec_pre", 0, RK2928_CLKGATE_CON(15), 2, GFLAGS),
600 GATE(0, "aclk_rkvdec_noc", "aclk_rkvdec_pre", 0, RK2928_CLKGATE_CON(15), 6, GFLAGS),
601 GATE(0, "hclk_vpu", "hclk_vpu_pre", 0, RK2928_CLKGATE_CON(15), 1, GFLAGS),
602 GATE(0, "hclk_vpu_noc", "hclk_vpu_pre", 0, RK2928_CLKGATE_CON(15), 5, GFLAGS),
603 GATE(0, "hclk_rkvdec", "hclk_rkvdec_pre", 0, RK2928_CLKGATE_CON(15), 3, GFLAGS),
604 GATE(0, "hclk_rkvdec_noc", "hclk_rkvdec_pre", 0, RK2928_CLKGATE_CON(15), 7, GFLAGS),
605
606 /* PD_MMC */
607 MMC(SCLK_SDMMC_DRV, "sdmmc_drv", "sclk_sdmmc", RK3228_SDMMC_CON0, 1),
608 MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "sclk_sdmmc", RK3228_SDMMC_CON1, 1),
609
610 MMC(SCLK_SDIO_DRV, "sdio_drv", "sclk_sdio", RK3228_SDIO_CON0, 1),
611 MMC(SCLK_SDIO_SAMPLE, "sdio_sample", "sclk_sdio", RK3228_SDIO_CON1, 1),
612
613 MMC(SCLK_EMMC_DRV, "emmc_drv", "sclk_emmc", RK3228_EMMC_CON0, 1),
614 MMC(SCLK_EMMC_SAMPLE, "emmc_sample", "sclk_emmc", RK3228_EMMC_CON1, 1),
615};
616
617static const char *const rk3228_critical_clocks[] __initconst = {
618 "aclk_cpu",
619 "aclk_peri",
620 "hclk_peri",
621 "pclk_peri",
622};
623
624static void __init rk3228_clk_init(struct device_node *np)
625{
626 void __iomem *reg_base;
627 struct clk *clk;
628
629 reg_base = of_iomap(np, 0);
630 if (!reg_base) {
631 pr_err("%s: could not map cru region\n", __func__);
632 return;
633 }
634
635 rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
636
637 /* xin12m is created by an cru-internal divider */
638 clk = clk_register_fixed_factor(NULL, "xin12m", "xin24m", 0, 1, 2);
639 if (IS_ERR(clk))
640 pr_warn("%s: could not register clock xin12m: %ld\n",
641 __func__, PTR_ERR(clk));
642
643 clk = clk_register_fixed_factor(NULL, "ddrphy_pre", "ddrphy4x", 0, 1, 4);
644 if (IS_ERR(clk))
645 pr_warn("%s: could not register clock ddrphy_pre: %ld\n",
646 __func__, PTR_ERR(clk));
647
648 clk = clk_register_fixed_factor(NULL, "hclk_vpu_pre",
649 "hclk_vpu_src", 0, 1, 4);
650 if (IS_ERR(clk))
651 pr_warn("%s: could not register clock hclk_vpu_pre: %ld\n",
652 __func__, PTR_ERR(clk));
653
654 clk = clk_register_fixed_factor(NULL, "hclk_rkvdec_pre",
655 "hclk_rkvdec_src", 0, 1, 4);
656 if (IS_ERR(clk))
657 pr_warn("%s: could not register clock hclk_rkvdec_pre: %ld\n",
658 __func__, PTR_ERR(clk));
659
660 rockchip_clk_register_plls(rk3228_pll_clks,
661 ARRAY_SIZE(rk3228_pll_clks),
662 RK3228_GRF_SOC_STATUS0);
663 rockchip_clk_register_branches(rk3228_clk_branches,
664 ARRAY_SIZE(rk3228_clk_branches));
665 rockchip_clk_protect_critical(rk3228_critical_clocks,
666 ARRAY_SIZE(rk3228_critical_clocks));
667
668 rockchip_clk_register_armclk(ARMCLK, "armclk",
669 mux_armclk_p, ARRAY_SIZE(mux_armclk_p),
670 &rk3228_cpuclk_data, rk3228_cpuclk_rates,
671 ARRAY_SIZE(rk3228_cpuclk_rates));
672
673 rockchip_register_softrst(np, 9, reg_base + RK2928_SOFTRST_CON(0),
674 ROCKCHIP_SOFTRST_HIWORD_MASK);
675
676 rockchip_register_restart_notifier(RK3228_GLB_SRST_FST);
677}
678CLK_OF_DECLARE(rk3228_cru, "rockchip,rk3228-cru", rk3228_clk_init);
diff --git a/drivers/clk/rockchip/clk.h b/drivers/clk/rockchip/clk.h
index 8d8f942ae7fc..01bc372bb048 100644
--- a/drivers/clk/rockchip/clk.h
+++ b/drivers/clk/rockchip/clk.h
@@ -33,7 +33,7 @@ struct clk;
33#define HIWORD_UPDATE(val, mask, shift) \ 33#define HIWORD_UPDATE(val, mask, shift) \
34 ((val) << (shift) | (mask) << ((shift) + 16)) 34 ((val) << (shift) | (mask) << ((shift) + 16))
35 35
36/* register positions shared by RK2928, RK3036, RK3066 and RK3188 */ 36/* register positions shared by RK2928, RK3036, RK3066, RK3188 and RK3228 */
37#define RK2928_PLL_CON(x) ((x) * 0x4) 37#define RK2928_PLL_CON(x) ((x) * 0x4)
38#define RK2928_MODE_CON 0x40 38#define RK2928_MODE_CON 0x40
39#define RK2928_CLKSEL_CON(x) ((x) * 0x4 + 0x44) 39#define RK2928_CLKSEL_CON(x) ((x) * 0x4 + 0x44)
@@ -50,6 +50,15 @@ struct clk;
50#define RK3036_EMMC_CON0 0x154 50#define RK3036_EMMC_CON0 0x154
51#define RK3036_EMMC_CON1 0x158 51#define RK3036_EMMC_CON1 0x158
52 52
53#define RK3228_GLB_SRST_FST 0x1f0
54#define RK3228_GLB_SRST_SND 0x1f4
55#define RK3228_SDMMC_CON0 0x1c0
56#define RK3228_SDMMC_CON1 0x1c4
57#define RK3228_SDIO_CON0 0x1c8
58#define RK3228_SDIO_CON1 0x1cc
59#define RK3228_EMMC_CON0 0x1d8
60#define RK3228_EMMC_CON1 0x1dc
61
53#define RK3288_PLL_CON(x) RK2928_PLL_CON(x) 62#define RK3288_PLL_CON(x) RK2928_PLL_CON(x)
54#define RK3288_MODE_CON 0x50 63#define RK3288_MODE_CON 0x50
55#define RK3288_CLKSEL_CON(x) ((x) * 0x4 + 0x60) 64#define RK3288_CLKSEL_CON(x) ((x) * 0x4 + 0x60)
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-26 22:49:24 -0400