diff options
author | Ralf Baechle <ralf@linux-mips.org> | 2016-09-20 08:33:01 -0400 |
---|---|---|
committer | Ralf Baechle <ralf@linux-mips.org> | 2016-09-29 12:59:49 -0400 |
commit | 3021773c7c3e75e20b693931a19362681e744ea9 (patch) | |
tree | 1d261df1423b1216268f7de2e4c61bc9952322ae | |
parent | 0a900553715c39cfb6170ccc9846b194a4c13ceb (diff) |
MIPS: DEC: Avoid la pseudo-instruction in delay slots
When expanding the la or dla pseudo-instruction in a delay slot the GNU
assembler will complain should the pseudo-instruction expand to multiple
actual instructions, since only the first of them will be in the delay
slot leading to the pseudo-instruction being only partially executed if
the branch is taken. Use of PTR_LA in the dec int-handler.S leads to
such warnings:
arch/mips/dec/int-handler.S: Assembler messages:
arch/mips/dec/int-handler.S:149: Warning: macro instruction expanded into multiple instructions in a branch delay slot
arch/mips/dec/int-handler.S:198: Warning: macro instruction expanded into multiple instructions in a branch delay slot
Avoid this by open coding the PTR_LA macros.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
-rw-r--r-- | arch/mips/dec/int-handler.S | 40 |
1 files changed, 38 insertions, 2 deletions
diff --git a/arch/mips/dec/int-handler.S b/arch/mips/dec/int-handler.S index d7b99180c6e1..1910223a9c02 100644 --- a/arch/mips/dec/int-handler.S +++ b/arch/mips/dec/int-handler.S | |||
@@ -146,7 +146,25 @@ | |||
146 | /* | 146 | /* |
147 | * Find irq with highest priority | 147 | * Find irq with highest priority |
148 | */ | 148 | */ |
149 | PTR_LA t1,cpu_mask_nr_tbl | 149 | # open coded PTR_LA t1, cpu_mask_nr_tbl |
150 | #if (_MIPS_SZPTR == 32) | ||
151 | # open coded la t1, cpu_mask_nr_tbl | ||
152 | lui t1, %hi(cpu_mask_nr_tbl) | ||
153 | addiu t1, %lo(cpu_mask_nr_tbl) | ||
154 | |||
155 | #endif | ||
156 | #if (_MIPS_SZPTR == 64) | ||
157 | # open coded dla t1, cpu_mask_nr_tbl | ||
158 | .set push | ||
159 | .set noat | ||
160 | lui t1, %highest(cpu_mask_nr_tbl) | ||
161 | lui AT, %hi(cpu_mask_nr_tbl) | ||
162 | daddiu t1, t1, %higher(cpu_mask_nr_tbl) | ||
163 | daddiu AT, AT, %lo(cpu_mask_nr_tbl) | ||
164 | dsll t1, 32 | ||
165 | daddu t1, t1, AT | ||
166 | .set pop | ||
167 | #endif | ||
150 | 1: lw t2,(t1) | 168 | 1: lw t2,(t1) |
151 | nop | 169 | nop |
152 | and t2,t0 | 170 | and t2,t0 |
@@ -195,7 +213,25 @@ | |||
195 | /* | 213 | /* |
196 | * Find irq with highest priority | 214 | * Find irq with highest priority |
197 | */ | 215 | */ |
198 | PTR_LA t1,asic_mask_nr_tbl | 216 | # open coded PTR_LA t1,asic_mask_nr_tbl |
217 | #if (_MIPS_SZPTR == 32) | ||
218 | # open coded la t1, asic_mask_nr_tbl | ||
219 | lui t1, %hi(asic_mask_nr_tbl) | ||
220 | addiu t1, %lo(asic_mask_nr_tbl) | ||
221 | |||
222 | #endif | ||
223 | #if (_MIPS_SZPTR == 64) | ||
224 | # open coded dla t1, asic_mask_nr_tbl | ||
225 | .set push | ||
226 | .set noat | ||
227 | lui t1, %highest(asic_mask_nr_tbl) | ||
228 | lui AT, %hi(asic_mask_nr_tbl) | ||
229 | daddiu t1, t1, %higher(asic_mask_nr_tbl) | ||
230 | daddiu AT, AT, %lo(asic_mask_nr_tbl) | ||
231 | dsll t1, 32 | ||
232 | daddu t1, t1, AT | ||
233 | .set pop | ||
234 | #endif | ||
199 | 2: lw t2,(t1) | 235 | 2: lw t2,(t1) |
200 | nop | 236 | nop |
201 | and t2,t0 | 237 | and t2,t0 |