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authorLen Brown <len.brown@intel.com>2017-04-29 00:11:46 -0400
committerLen Brown <len.brown@intel.com>2017-04-29 00:11:46 -0400
commit2fc49cb0b508947bf048ecb0f5710169e62ce68e (patch)
tree0cf27e1a00912ff4eba997deb032fba250608ab9
parent8d84e906f5db80540510e448226f2718a686eb2a (diff)
x86: msr-index.h: fix shifts to ULL results in HWP macros.
x = 1 ulong_long = x << 32; results in: warning: left shift count >= width of type x = 8 ulong_long = x << 24; results in a sign extended ulong_long Cast x to unsigned long long in these macros to prevent these errors. Signed-off-by: Len Brown <len.brown@intel.com>
-rw-r--r--arch/x86/include/asm/msr-index.h6
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index 50c0c3204a92..6da2b30781ff 100644
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -238,13 +238,13 @@
238#define HWP_MIN_PERF(x) (x & 0xff) 238#define HWP_MIN_PERF(x) (x & 0xff)
239#define HWP_MAX_PERF(x) ((x & 0xff) << 8) 239#define HWP_MAX_PERF(x) ((x & 0xff) << 8)
240#define HWP_DESIRED_PERF(x) ((x & 0xff) << 16) 240#define HWP_DESIRED_PERF(x) ((x & 0xff) << 16)
241#define HWP_ENERGY_PERF_PREFERENCE(x) ((x & 0xff) << 24) 241#define HWP_ENERGY_PERF_PREFERENCE(x) (((unsigned long long) x & 0xff) << 24)
242#define HWP_EPP_PERFORMANCE 0x00 242#define HWP_EPP_PERFORMANCE 0x00
243#define HWP_EPP_BALANCE_PERFORMANCE 0x80 243#define HWP_EPP_BALANCE_PERFORMANCE 0x80
244#define HWP_EPP_BALANCE_POWERSAVE 0xC0 244#define HWP_EPP_BALANCE_POWERSAVE 0xC0
245#define HWP_EPP_POWERSAVE 0xFF 245#define HWP_EPP_POWERSAVE 0xFF
246#define HWP_ACTIVITY_WINDOW(x) ((x & 0xff3) << 32) 246#define HWP_ACTIVITY_WINDOW(x) ((unsigned long long)(x & 0xff3) << 32)
247#define HWP_PACKAGE_CONTROL(x) ((x & 0x1) << 42) 247#define HWP_PACKAGE_CONTROL(x) ((unsigned long long)(x & 0x1) << 42)
248 248
249/* IA32_HWP_STATUS */ 249/* IA32_HWP_STATUS */
250#define HWP_GUARANTEED_CHANGE(x) (x & 0x1) 250#define HWP_GUARANTEED_CHANGE(x) (x & 0x1)