diff options
| author | Masahiro Yamada <yamada.masahiro@socionext.com> | 2016-10-16 10:59:16 -0400 |
|---|---|---|
| committer | Masahiro Yamada <yamada.masahiro@socionext.com> | 2016-11-05 00:24:57 -0400 |
| commit | 2f81137f034765078399354ef6e9659259a77ae2 (patch) | |
| tree | 6e1afac467ddb96b37d12cec89c67dcdc9ede54a | |
| parent | a909d3e636995ba7c349e2ca5dbb528154d4ac30 (diff) | |
arm64: dts: uniphier: switch over to PSCI enable method
At the first system bring-up, I chose to use spin-table because ARM
Trusted Firmware was not ready for this platform at that moment.
Actually, these SoCs are equipped with EL3 and able to provide PSCI.
Now I finished porting the ATF BL31 for the UniPhier platform, so it
is ready to migrate to PSCI enable method.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| -rw-r--r-- | arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi | 13 | ||||
| -rw-r--r-- | arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi | 19 |
2 files changed, 18 insertions, 14 deletions
diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi index 3eb4c42ce7b9..17bc4b359912 100644 --- a/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi +++ b/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi | |||
| @@ -43,7 +43,7 @@ | |||
| 43 | * OTHER DEALINGS IN THE SOFTWARE. | 43 | * OTHER DEALINGS IN THE SOFTWARE. |
| 44 | */ | 44 | */ |
| 45 | 45 | ||
| 46 | /memreserve/ 0x80000000 0x00000008; /* cpu-release-addr */ | 46 | /memreserve/ 0x80000000 0x00080000; |
| 47 | 47 | ||
| 48 | / { | 48 | / { |
| 49 | compatible = "socionext,uniphier-ld11"; | 49 | compatible = "socionext,uniphier-ld11"; |
| @@ -70,19 +70,22 @@ | |||
| 70 | device_type = "cpu"; | 70 | device_type = "cpu"; |
| 71 | compatible = "arm,cortex-a53", "arm,armv8"; | 71 | compatible = "arm,cortex-a53", "arm,armv8"; |
| 72 | reg = <0 0x000>; | 72 | reg = <0 0x000>; |
| 73 | enable-method = "spin-table"; | 73 | enable-method = "psci"; |
| 74 | cpu-release-addr = <0 0x80000000>; | ||
| 75 | }; | 74 | }; |
| 76 | 75 | ||
| 77 | cpu1: cpu@1 { | 76 | cpu1: cpu@1 { |
| 78 | device_type = "cpu"; | 77 | device_type = "cpu"; |
| 79 | compatible = "arm,cortex-a53", "arm,armv8"; | 78 | compatible = "arm,cortex-a53", "arm,armv8"; |
| 80 | reg = <0 0x001>; | 79 | reg = <0 0x001>; |
| 81 | enable-method = "spin-table"; | 80 | enable-method = "psci"; |
| 82 | cpu-release-addr = <0 0x80000000>; | ||
| 83 | }; | 81 | }; |
| 84 | }; | 82 | }; |
| 85 | 83 | ||
| 84 | psci { | ||
| 85 | compatible = "arm,psci-1.0"; | ||
| 86 | method = "smc"; | ||
| 87 | }; | ||
| 88 | |||
| 86 | clocks { | 89 | clocks { |
| 87 | refclk: ref { | 90 | refclk: ref { |
| 88 | compatible = "fixed-clock"; | 91 | compatible = "fixed-clock"; |
diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi index 56a1b2e92cf3..c8ebe7e52809 100644 --- a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi +++ b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi | |||
| @@ -43,7 +43,7 @@ | |||
| 43 | * OTHER DEALINGS IN THE SOFTWARE. | 43 | * OTHER DEALINGS IN THE SOFTWARE. |
| 44 | */ | 44 | */ |
| 45 | 45 | ||
| 46 | /memreserve/ 0x80000000 0x00000008; /* cpu-release-addr */ | 46 | /memreserve/ 0x80000000 0x00080000; |
| 47 | 47 | ||
| 48 | / { | 48 | / { |
| 49 | compatible = "socionext,uniphier-ld20"; | 49 | compatible = "socionext,uniphier-ld20"; |
| @@ -79,35 +79,36 @@ | |||
| 79 | device_type = "cpu"; | 79 | device_type = "cpu"; |
| 80 | compatible = "arm,cortex-a72", "arm,armv8"; | 80 | compatible = "arm,cortex-a72", "arm,armv8"; |
| 81 | reg = <0 0x000>; | 81 | reg = <0 0x000>; |
| 82 | enable-method = "spin-table"; | 82 | enable-method = "psci"; |
| 83 | cpu-release-addr = <0 0x80000000>; | ||
| 84 | }; | 83 | }; |
| 85 | 84 | ||
| 86 | cpu1: cpu@1 { | 85 | cpu1: cpu@1 { |
| 87 | device_type = "cpu"; | 86 | device_type = "cpu"; |
| 88 | compatible = "arm,cortex-a72", "arm,armv8"; | 87 | compatible = "arm,cortex-a72", "arm,armv8"; |
| 89 | reg = <0 0x001>; | 88 | reg = <0 0x001>; |
| 90 | enable-method = "spin-table"; | 89 | enable-method = "psci"; |
| 91 | cpu-release-addr = <0 0x80000000>; | ||
| 92 | }; | 90 | }; |
| 93 | 91 | ||
| 94 | cpu2: cpu@100 { | 92 | cpu2: cpu@100 { |
| 95 | device_type = "cpu"; | 93 | device_type = "cpu"; |
| 96 | compatible = "arm,cortex-a53", "arm,armv8"; | 94 | compatible = "arm,cortex-a53", "arm,armv8"; |
| 97 | reg = <0 0x100>; | 95 | reg = <0 0x100>; |
| 98 | enable-method = "spin-table"; | 96 | enable-method = "psci"; |
| 99 | cpu-release-addr = <0 0x80000000>; | ||
| 100 | }; | 97 | }; |
| 101 | 98 | ||
| 102 | cpu3: cpu@101 { | 99 | cpu3: cpu@101 { |
| 103 | device_type = "cpu"; | 100 | device_type = "cpu"; |
| 104 | compatible = "arm,cortex-a53", "arm,armv8"; | 101 | compatible = "arm,cortex-a53", "arm,armv8"; |
| 105 | reg = <0 0x101>; | 102 | reg = <0 0x101>; |
| 106 | enable-method = "spin-table"; | 103 | enable-method = "psci"; |
| 107 | cpu-release-addr = <0 0x80000000>; | ||
| 108 | }; | 104 | }; |
| 109 | }; | 105 | }; |
| 110 | 106 | ||
| 107 | psci { | ||
| 108 | compatible = "arm,psci-1.0"; | ||
| 109 | method = "smc"; | ||
| 110 | }; | ||
| 111 | |||
| 111 | clocks { | 112 | clocks { |
| 112 | refclk: ref { | 113 | refclk: ref { |
| 113 | compatible = "fixed-clock"; | 114 | compatible = "fixed-clock"; |