diff options
author | Jayachandran B <jayachandran.b@intel.com> | 2016-06-13 08:29:03 -0400 |
---|---|---|
committer | Mark Brown <broonie@kernel.org> | 2016-06-14 09:59:33 -0400 |
commit | 2f74053bead3f47ddee219f521562db941ce0ae1 (patch) | |
tree | fe1c92fedab7dde41ed86991f7b022e230f91e2a | |
parent | 2023576dd74c9afdb25692f7e9ac9a837e8cf3bd (diff) |
ASoC: Intel: Skylake: Update DSP stall bits
The stall bits needs to comprehend the number of DSP cores
running, so update the stall and unstall register writes to
comprehend SKL_DSP_CORES_MASK values as well.
Signed-off-by: Jayachandran B <jayachandran.b@intel.com>
Signed-off-by: Ramesh Babu <ramesh.babu@intel.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
-rw-r--r-- | sound/soc/intel/skylake/skl-sst-dsp.c | 11 |
1 files changed, 5 insertions, 6 deletions
diff --git a/sound/soc/intel/skylake/skl-sst-dsp.c b/sound/soc/intel/skylake/skl-sst-dsp.c index 37b1d24a9a9d..33c45aa53532 100644 --- a/sound/soc/intel/skylake/skl-sst-dsp.c +++ b/sound/soc/intel/skylake/skl-sst-dsp.c | |||
@@ -106,9 +106,9 @@ static bool is_skl_dsp_core_enable(struct sst_dsp *ctx) | |||
106 | static int skl_dsp_reset_core(struct sst_dsp *ctx) | 106 | static int skl_dsp_reset_core(struct sst_dsp *ctx) |
107 | { | 107 | { |
108 | /* stall core */ | 108 | /* stall core */ |
109 | sst_dsp_shim_write_unlocked(ctx, SKL_ADSP_REG_ADSPCS, | 109 | sst_dsp_shim_update_bits_unlocked(ctx, SKL_ADSP_REG_ADSPCS, |
110 | sst_dsp_shim_read_unlocked(ctx, SKL_ADSP_REG_ADSPCS) & | 110 | SKL_ADSPCS_CSTALL_MASK, |
111 | SKL_ADSPCS_CSTALL(SKL_DSP_CORES_MASK)); | 111 | SKL_ADSPCS_CSTALL(SKL_DSP_CORES_MASK)); |
112 | 112 | ||
113 | /* set reset state */ | 113 | /* set reset state */ |
114 | return skl_dsp_core_set_reset_state(ctx); | 114 | return skl_dsp_core_set_reset_state(ctx); |
@@ -127,9 +127,8 @@ int skl_dsp_start_core(struct sst_dsp *ctx) | |||
127 | 127 | ||
128 | /* run core */ | 128 | /* run core */ |
129 | dev_dbg(ctx->dev, "run core...\n"); | 129 | dev_dbg(ctx->dev, "run core...\n"); |
130 | sst_dsp_shim_write_unlocked(ctx, SKL_ADSP_REG_ADSPCS, | 130 | sst_dsp_shim_update_bits_unlocked(ctx, SKL_ADSP_REG_ADSPCS, |
131 | sst_dsp_shim_read_unlocked(ctx, SKL_ADSP_REG_ADSPCS) & | 131 | SKL_ADSPCS_CSTALL_MASK, 0); |
132 | ~SKL_ADSPCS_CSTALL(SKL_DSP_CORES_MASK)); | ||
133 | 132 | ||
134 | if (!is_skl_dsp_core_enable(ctx)) { | 133 | if (!is_skl_dsp_core_enable(ctx)) { |
135 | skl_dsp_reset_core(ctx); | 134 | skl_dsp_reset_core(ctx); |