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authorBard Liao <bardliao@realtek.com>2015-11-10 01:40:55 -0500
committerMark Brown <broonie@kernel.org>2015-11-10 13:58:19 -0500
commit2f64b6ed44c26eeb3d1bf5428936629cf552eda7 (patch)
treeb04ad87ce6b7b8259ee047945b20f81e243b640c
parent6ff33f3902c3b1c5d0db6b1e2c70b6d76fba357f (diff)
ASoC: rl6231: avoid using divisible by 3 for DMIC clk
Few codecs will meet no DMIC clock output issue when select a divided number which is divisible by 3. To prevent this issue, the patch ignore the numbers when calculating the DMIC clock divider. Signed-off-by: Bard Liao <bardliao@realtek.com> Signed-off-by: Mark Brown <broonie@kernel.org>
-rw-r--r--sound/soc/codecs/rl6231.c2
1 files changed, 2 insertions, 0 deletions
diff --git a/sound/soc/codecs/rl6231.c b/sound/soc/codecs/rl6231.c
index aca479fa7670..18b42925314e 100644
--- a/sound/soc/codecs/rl6231.c
+++ b/sound/soc/codecs/rl6231.c
@@ -80,6 +80,8 @@ int rl6231_calc_dmic_clk(int rate)
80 } 80 }
81 81
82 for (i = 0; i < ARRAY_SIZE(div); i++) { 82 for (i = 0; i < ARRAY_SIZE(div); i++) {
83 if ((div[i] % 3) == 0)
84 continue;
83 /* find divider that gives DMIC frequency below 3MHz */ 85 /* find divider that gives DMIC frequency below 3MHz */
84 if (3000000 * div[i] >= rate) 86 if (3000000 * div[i] >= rate)
85 return i; 87 return i;