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author | Jia-Ju Bai <baijiaju1990@gmail.com> | 2018-08-03 20:33:44 -0400 |
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committer | Alex Deucher <alexander.deucher@amd.com> | 2018-08-27 12:10:02 -0400 |
commit | 2f2debb5a162ea9aeb03ad2532827631e3a68b1a (patch) | |
tree | 20653695ed9e1119952accba6ca919a589f3c1a2 | |
parent | c51cebb890dc76260c02354882cf333c8207dd19 (diff) |
gpu: drm: radeon: si: Replace mdelay() with msleep() in si_pcie_gen3_enable()
si_pcie_gen3_enable() is never called in atomic context.
It calls mdelay() to busily wait, which is not necessary.
mdelay() can be replaced with msleep().
This is found by a static analysis tool named DCNS written by myself
Signed-off-by: Jia-Ju Bai <baijiaju1990@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-rw-r--r-- | drivers/gpu/drm/radeon/si.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c index 85c604d29235..841bc8bc333d 100644 --- a/drivers/gpu/drm/radeon/si.c +++ b/drivers/gpu/drm/radeon/si.c | |||
@@ -7183,7 +7183,7 @@ static void si_pcie_gen3_enable(struct radeon_device *rdev) | |||
7183 | tmp |= LC_REDO_EQ; | 7183 | tmp |= LC_REDO_EQ; |
7184 | WREG32_PCIE_PORT(PCIE_LC_CNTL4, tmp); | 7184 | WREG32_PCIE_PORT(PCIE_LC_CNTL4, tmp); |
7185 | 7185 | ||
7186 | mdelay(100); | 7186 | msleep(100); |
7187 | 7187 | ||
7188 | /* linkctl */ | 7188 | /* linkctl */ |
7189 | pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &tmp16); | 7189 | pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &tmp16); |