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authorMaarten Lankhorst <maarten.lankhorst@linux.intel.com>2016-05-17 09:07:57 -0400
committerMaarten Lankhorst <maarten.lankhorst@linux.intel.com>2016-05-19 08:38:40 -0400
commit2ee004f7c59b2e642f0bb2834f847d756f2dd7b7 (patch)
tree39bf4f28e53e3dfd54387d39813ab9d0056ceea6
parentb8d2afae557dbb9b9c7bc6f6ec4f5278f3c4c34e (diff)
drm/i915: Remove queue_flip pointer.
With the removal of cs support this is no longer reachable. Can be revived if needed. Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1463490484-19540-15-git-send-email-maarten.lankhorst@linux.intel.com Reviewed-by: Patrik Jakobsson <patrik.jakobsson@linux.intel.com>
Diffstat
-rw-r--r--drivers/gpu/drm/i915/i915_drv.h5
-rw-r--r--drivers/gpu/drm/i915/intel_display.c259
2 files changed, 0 insertions, 264 deletions
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 26c0525fc546..ea35a432bb68 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -618,11 +618,6 @@ struct drm_i915_display_funcs {
618 void (*audio_codec_disable)(struct intel_encoder *encoder); 618 void (*audio_codec_disable)(struct intel_encoder *encoder);
619 void (*fdi_link_train)(struct drm_crtc *crtc); 619 void (*fdi_link_train)(struct drm_crtc *crtc);
620 void (*init_clock_gating)(struct drm_device *dev); 620 void (*init_clock_gating)(struct drm_device *dev);
621 int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
622 struct drm_framebuffer *fb,
623 struct drm_i915_gem_object *obj,
624 struct drm_i915_gem_request *req,
625 uint64_t gtt_offset);
626 void (*hpd_irq_setup)(struct drm_i915_private *dev_priv); 621 void (*hpd_irq_setup)(struct drm_i915_private *dev_priv);
627 /* clock updates for mode set */ 622 /* clock updates for mode set */
628 /* cursor updates */ 623 /* cursor updates */
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 090ddf9c6d6c..fbcc569b4c05 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -10964,237 +10964,6 @@ void intel_finish_page_flip_mmio(struct drm_i915_private *dev_priv, int pipe)
10964 spin_unlock_irqrestore(&dev->event_lock, flags); 10964 spin_unlock_irqrestore(&dev->event_lock, flags);
10965} 10965}
10966 10966
10967static int intel_gen2_queue_flip(struct drm_device *dev,
10968 struct drm_crtc *crtc,
10969 struct drm_framebuffer *fb,
10970 struct drm_i915_gem_object *obj,
10971 struct drm_i915_gem_request *req,
10972 uint64_t gtt_offset)
10973{
10974 struct intel_engine_cs *engine = req->engine;
10975 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10976 u32 flip_mask;
10977 int ret;
10978
10979 ret = intel_ring_begin(req, 6);
10980 if (ret)
10981 return ret;
10982
10983 /* Can't queue multiple flips, so wait for the previous
10984 * one to finish before executing the next.
10985 */
10986 if (intel_crtc->plane)
10987 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10988 else
10989 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
10990 intel_ring_emit(engine, MI_WAIT_FOR_EVENT | flip_mask);
10991 intel_ring_emit(engine, MI_NOOP);
10992 intel_ring_emit(engine, MI_DISPLAY_FLIP |
10993 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10994 intel_ring_emit(engine, fb->pitches[0]);
10995 intel_ring_emit(engine, gtt_offset);
10996 intel_ring_emit(engine, 0); /* aux display base address, unused */
10997
10998 return 0;
10999}
11000
11001static int intel_gen3_queue_flip(struct drm_device *dev,
11002 struct drm_crtc *crtc,
11003 struct drm_framebuffer *fb,
11004 struct drm_i915_gem_object *obj,
11005 struct drm_i915_gem_request *req,
11006 uint64_t gtt_offset)
11007{
11008 struct intel_engine_cs *engine = req->engine;
11009 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11010 u32 flip_mask;
11011 int ret;
11012
11013 ret = intel_ring_begin(req, 6);
11014 if (ret)
11015 return ret;
11016
11017 if (intel_crtc->plane)
11018 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
11019 else
11020 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
11021 intel_ring_emit(engine, MI_WAIT_FOR_EVENT | flip_mask);
11022 intel_ring_emit(engine, MI_NOOP);
11023 intel_ring_emit(engine, MI_DISPLAY_FLIP_I915 |
11024 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11025 intel_ring_emit(engine, fb->pitches[0]);
11026 intel_ring_emit(engine, gtt_offset);
11027 intel_ring_emit(engine, MI_NOOP);
11028
11029 return 0;
11030}
11031
11032static int intel_gen4_queue_flip(struct drm_device *dev,
11033 struct drm_crtc *crtc,
11034 struct drm_framebuffer *fb,
11035 struct drm_i915_gem_object *obj,
11036 struct drm_i915_gem_request *req,
11037 uint64_t gtt_offset)
11038{
11039 struct intel_engine_cs *engine = req->engine;
11040 struct drm_i915_private *dev_priv = dev->dev_private;
11041 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11042 uint32_t pf, pipesrc;
11043 int ret;
11044
11045 ret = intel_ring_begin(req, 4);
11046 if (ret)
11047 return ret;
11048
11049 /* i965+ uses the linear or tiled offsets from the
11050 * Display Registers (which do not change across a page-flip)
11051 * so we need only reprogram the base address.
11052 */
11053 intel_ring_emit(engine, MI_DISPLAY_FLIP |
11054 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11055 intel_ring_emit(engine, fb->pitches[0]);
11056 intel_ring_emit(engine, gtt_offset | obj->tiling_mode);
11057
11058 /* XXX Enabling the panel-fitter across page-flip is so far
11059 * untested on non-native modes, so ignore it for now.
11060 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
11061 */
11062 pf = 0;
11063 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11064 intel_ring_emit(engine, pf | pipesrc);
11065
11066 return 0;
11067}
11068
11069static int intel_gen6_queue_flip(struct drm_device *dev,
11070 struct drm_crtc *crtc,
11071 struct drm_framebuffer *fb,
11072 struct drm_i915_gem_object *obj,
11073 struct drm_i915_gem_request *req,
11074 uint64_t gtt_offset)
11075{
11076 struct intel_engine_cs *engine = req->engine;
11077 struct drm_i915_private *dev_priv = dev->dev_private;
11078 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11079 uint32_t pf, pipesrc;
11080 int ret;
11081
11082 ret = intel_ring_begin(req, 4);
11083 if (ret)
11084 return ret;
11085
11086 intel_ring_emit(engine, MI_DISPLAY_FLIP |
11087 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11088 intel_ring_emit(engine, fb->pitches[0] | obj->tiling_mode);
11089 intel_ring_emit(engine, gtt_offset);
11090
11091 /* Contrary to the suggestions in the documentation,
11092 * "Enable Panel Fitter" does not seem to be required when page
11093 * flipping with a non-native mode, and worse causes a normal
11094 * modeset to fail.
11095 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
11096 */
11097 pf = 0;
11098 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11099 intel_ring_emit(engine, pf | pipesrc);
11100
11101 return 0;
11102}
11103
11104static int intel_gen7_queue_flip(struct drm_device *dev,
11105 struct drm_crtc *crtc,
11106 struct drm_framebuffer *fb,
11107 struct drm_i915_gem_object *obj,
11108 struct drm_i915_gem_request *req,
11109 uint64_t gtt_offset)
11110{
11111 struct intel_engine_cs *engine = req->engine;
11112 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11113 uint32_t plane_bit = 0;
11114 int len, ret;
11115
11116 switch (intel_crtc->plane) {
11117 case PLANE_A:
11118 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
11119 break;
11120 case PLANE_B:
11121 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
11122 break;
11123 case PLANE_C:
11124 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
11125 break;
11126 default:
11127 WARN_ONCE(1, "unknown plane in flip command\n");
11128 return -ENODEV;
11129 }
11130
11131 len = 4;
11132 if (engine->id == RCS) {
11133 len += 6;
11134 /*
11135 * On Gen 8, SRM is now taking an extra dword to accommodate
11136 * 48bits addresses, and we need a NOOP for the batch size to
11137 * stay even.
11138 */
11139 if (IS_GEN8(dev))
11140 len += 2;
11141 }
11142
11143 /*
11144 * BSpec MI_DISPLAY_FLIP for IVB:
11145 * "The full packet must be contained within the same cache line."
11146 *
11147 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
11148 * cacheline, if we ever start emitting more commands before
11149 * the MI_DISPLAY_FLIP we may need to first emit everything else,
11150 * then do the cacheline alignment, and finally emit the
11151 * MI_DISPLAY_FLIP.
11152 */
11153 ret = intel_ring_cacheline_align(req);
11154 if (ret)
11155 return ret;
11156
11157 ret = intel_ring_begin(req, len);
11158 if (ret)
11159 return ret;
11160
11161 /* Unmask the flip-done completion message. Note that the bspec says that
11162 * we should do this for both the BCS and RCS, and that we must not unmask
11163 * more than one flip event at any time (or ensure that one flip message
11164 * can be sent by waiting for flip-done prior to queueing new flips).
11165 * Experimentation says that BCS works despite DERRMR masking all
11166 * flip-done completion events and that unmasking all planes at once
11167 * for the RCS also doesn't appear to drop events. Setting the DERRMR
11168 * to zero does lead to lockups within MI_DISPLAY_FLIP.
11169 */
11170 if (engine->id == RCS) {
11171 intel_ring_emit(engine, MI_LOAD_REGISTER_IMM(1));
11172 intel_ring_emit_reg(engine, DERRMR);
11173 intel_ring_emit(engine, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
11174 DERRMR_PIPEB_PRI_FLIP_DONE |
11175 DERRMR_PIPEC_PRI_FLIP_DONE));
11176 if (IS_GEN8(dev))
11177 intel_ring_emit(engine, MI_STORE_REGISTER_MEM_GEN8 |
11178 MI_SRM_LRM_GLOBAL_GTT);
11179 else
11180 intel_ring_emit(engine, MI_STORE_REGISTER_MEM |
11181 MI_SRM_LRM_GLOBAL_GTT);
11182 intel_ring_emit_reg(engine, DERRMR);
11183 intel_ring_emit(engine, engine->scratch.gtt_offset + 256);
11184 if (IS_GEN8(dev)) {
11185 intel_ring_emit(engine, 0);
11186 intel_ring_emit(engine, MI_NOOP);
11187 }
11188 }
11189
11190 intel_ring_emit(engine, MI_DISPLAY_FLIP_I915 | plane_bit);
11191 intel_ring_emit(engine, (fb->pitches[0] | obj->tiling_mode));
11192 intel_ring_emit(engine, gtt_offset);
11193 intel_ring_emit(engine, (MI_NOOP));
11194
11195 return 0;
11196}
11197
11198static void intel_mmio_flip_work_func(struct work_struct *w) 10967static void intel_mmio_flip_work_func(struct work_struct *w)
11199{ 10968{
11200 struct intel_flip_work *work = 10969 struct intel_flip_work *work =
@@ -14752,34 +14521,6 @@ void intel_init_display_hooks(struct drm_i915_private *dev_priv)
14752 dev_priv->display.modeset_calc_cdclk = 14521 dev_priv->display.modeset_calc_cdclk =
14753 broxton_modeset_calc_cdclk; 14522 broxton_modeset_calc_cdclk;
14754 } 14523 }
14755
14756 switch (INTEL_INFO(dev_priv)->gen) {
14757 case 2:
14758 dev_priv->display.queue_flip = intel_gen2_queue_flip;
14759 break;
14760
14761 case 3:
14762 dev_priv->display.queue_flip = intel_gen3_queue_flip;
14763 break;
14764
14765 case 4:
14766 case 5:
14767 dev_priv->display.queue_flip = intel_gen4_queue_flip;
14768 break;
14769
14770 case 6:
14771 dev_priv->display.queue_flip = intel_gen6_queue_flip;
14772 break;
14773 case 7:
14774 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
14775 dev_priv->display.queue_flip = intel_gen7_queue_flip;
14776 break;
14777 case 9:
14778 /* Drop through - unsupported since execlist only. */
14779 default:
14780 /* Default just returns -ENODEV to indicate unsupported */
14781 break;
14782 }
14783} 14524}
14784 14525
14785/* 14526/*
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-22 03:04:01 -0400