drm/exynos/mixer: fix synchronization check in interlaced mode

In case of interlace mode video processor registers and mixer config
register must be check to ensure internal state is in sync with shadow
registers.
This patch fixes page-faults in interlaced mode.

Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
Signed-off-by: Inki Dae <inki.dae@samsung.com>

2 files changed, 11 insertions, 0 deletions

diff --git a/drivers/gpu/drm/exynos/exynos_mixer.c b/drivers/gpu/drm/exynos/exynos_mixer.c
index 257299ec95c4..a8d978d6e4e0 100644
--- a/drivers/gpu/drm/exynos/exynos_mixer.c
+++ b/drivers/gpu/drm/exynos/exynos_mixer.c
@@ -482,6 +482,7 @@ static void vp_video_buffer(struct mixer_context *ctx,
 
         spin_lock_irqsave(&ctx->reg_slock, flags);
 
+        vp_reg_write(ctx, VP_SHADOW_UPDATE, 1);
         /* interlace or progressive scan mode */
         val = (test_bit(MXR_BIT_INTERLACE, &ctx->flags) ? ~0 : 0);
         vp_reg_writemask(ctx, VP_MODE, val, VP_MODE_LINE_SKIP);
@@ -699,6 +700,15 @@ static irqreturn_t mixer_irq_handler(int irq, void *arg)
 
                 /* interlace scan need to check shadow register */
                 if (test_bit(MXR_BIT_INTERLACE, &ctx->flags)) {
+                        if (test_bit(MXR_BIT_VP_ENABLED, &ctx->flags) &&
+                            vp_reg_read(ctx, VP_SHADOW_UPDATE))
+                                goto out;
+
+                        base = mixer_reg_read(ctx, MXR_CFG);
+                        shadow = mixer_reg_read(ctx, MXR_CFG_S);
+                        if (base != shadow)
+                                goto out;
+
                         base = mixer_reg_read(ctx, MXR_GRAPHIC_BASE(0));
                         shadow = mixer_reg_read(ctx, MXR_GRAPHIC_BASE_S(0));
                         if (base != shadow)
diff --git a/drivers/gpu/drm/exynos/regs-mixer.h b/drivers/gpu/drm/exynos/regs-mixer.h
index c311f571bdf9..189cfa2470a8 100644
--- a/drivers/gpu/drm/exynos/regs-mixer.h
+++ b/drivers/gpu/drm/exynos/regs-mixer.h
@@ -47,6 +47,7 @@
 #define MXR_MO                          0x0304
 #define MXR_RESOLUTION                  0x0310
 
+#define MXR_CFG_S                       0x2004
 #define MXR_GRAPHIC0_BASE_S             0x2024
 #define MXR_GRAPHIC1_BASE_S             0x2044