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authorChanwoo Choi <cw00.choi@samsung.com>2015-02-02 09:24:03 -0500
committerSylwester Nawrocki <s.nawrocki@samsung.com>2015-02-04 12:58:13 -0500
commit2e997c035945784fb8c564305c0f0ddacc374fe4 (patch)
treea015ff58443152d2da80d50da2a3f09f8339964e
parent2a1808a6c00fb6d75ebfa596add57638b9290926 (diff)
clk: samsung: exynos5433: Add clocks for CMU_AUD domain
This patch adds the mux/divider/gate clocks for CMU_AUD domain which includes the clocks of Cortex-A5/Bus/Audio clocks. Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Acked-by: Inki Dae <inki.dae@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Diffstat
-rw-r--r--drivers/clk/samsung/clk-exynos5433.c172
-rw-r--r--include/dt-bindings/clock/exynos5433.h53
2 files changed, 225 insertions, 0 deletions
diff --git a/drivers/clk/samsung/clk-exynos5433.c b/drivers/clk/samsung/clk-exynos5433.c
index 3e6c3d595e96..ad0105aa0de6 100644
--- a/drivers/clk/samsung/clk-exynos5433.c
+++ b/drivers/clk/samsung/clk-exynos5433.c
@@ -2459,3 +2459,175 @@ static void __init exynos5433_cmu_disp_init(struct device_node *np)
2459 2459
2460CLK_OF_DECLARE(exynos5433_cmu_disp, "samsung,exynos5433-cmu-disp", 2460CLK_OF_DECLARE(exynos5433_cmu_disp, "samsung,exynos5433-cmu-disp",
2461 exynos5433_cmu_disp_init); 2461 exynos5433_cmu_disp_init);
2462
2463/*
2464 * Register offset definitions for CMU_AUD
2465 */
2466#define MUX_SEL_AUD0 0x0200
2467#define MUX_SEL_AUD1 0x0204
2468#define MUX_ENABLE_AUD0 0x0300
2469#define MUX_ENABLE_AUD1 0x0304
2470#define MUX_STAT_AUD0 0x0400
2471#define DIV_AUD0 0x0600
2472#define DIV_AUD1 0x0604
2473#define DIV_STAT_AUD0 0x0700
2474#define DIV_STAT_AUD1 0x0704
2475#define ENABLE_ACLK_AUD 0x0800
2476#define ENABLE_PCLK_AUD 0x0900
2477#define ENABLE_SCLK_AUD0 0x0a00
2478#define ENABLE_SCLK_AUD1 0x0a04
2479#define ENABLE_IP_AUD0 0x0b00
2480#define ENABLE_IP_AUD1 0x0b04
2481
2482static unsigned long aud_clk_regs[] __initdata = {
2483 MUX_SEL_AUD0,
2484 MUX_SEL_AUD1,
2485 MUX_ENABLE_AUD0,
2486 MUX_ENABLE_AUD1,
2487 MUX_STAT_AUD0,
2488 DIV_AUD0,
2489 DIV_AUD1,
2490 DIV_STAT_AUD0,
2491 DIV_STAT_AUD1,
2492 ENABLE_ACLK_AUD,
2493 ENABLE_PCLK_AUD,
2494 ENABLE_SCLK_AUD0,
2495 ENABLE_SCLK_AUD1,
2496 ENABLE_IP_AUD0,
2497 ENABLE_IP_AUD1,
2498};
2499
2500/* list of all parent clock list */
2501PNAME(mout_aud_pll_user_aud_p) = { "oscclk", "fout_aud_pll", };
2502PNAME(mout_sclk_aud_pcm_p) = { "mout_aud_pll_user", "ioclk_audiocdclk0",};
2503
2504static struct samsung_fixed_rate_clock aud_fixed_clks[] __initdata = {
2505 FRATE(0, "ioclk_jtag_tclk", NULL, CLK_IS_ROOT, 33000000),
2506 FRATE(0, "ioclk_slimbus_clk", NULL, CLK_IS_ROOT, 25000000),
2507 FRATE(0, "ioclk_i2s_bclk", NULL, CLK_IS_ROOT, 50000000),
2508};
2509
2510static struct samsung_mux_clock aud_mux_clks[] __initdata = {
2511 /* MUX_SEL_AUD0 */
2512 MUX(CLK_MOUT_AUD_PLL_USER, "mout_aud_pll_user",
2513 mout_aud_pll_user_aud_p, MUX_SEL_AUD0, 0, 1),
2514
2515 /* MUX_SEL_AUD1 */
2516 MUX(CLK_MOUT_SCLK_AUD_PCM, "mout_sclk_aud_pcm", mout_sclk_aud_pcm_p,
2517 MUX_SEL_AUD1, 8, 1),
2518 MUX(CLK_MOUT_SCLK_AUD_I2S, "mout_sclk_aud_i2s", mout_sclk_aud_pcm_p,
2519 MUX_SEL_AUD1, 0, 1),
2520};
2521
2522static struct samsung_div_clock aud_div_clks[] __initdata = {
2523 /* DIV_AUD0 */
2524 DIV(CLK_DIV_ATCLK_AUD, "div_atclk_aud", "div_aud_ca5", DIV_AUD0,
2525 12, 4),
2526 DIV(CLK_DIV_PCLK_DBG_AUD, "div_pclk_dbg_aud", "div_aud_ca5", DIV_AUD0,
2527 8, 4),
2528 DIV(CLK_DIV_ACLK_AUD, "div_aclk_aud", "div_aud_ca5", DIV_AUD0,
2529 4, 4),
2530 DIV(CLK_DIV_AUD_CA5, "div_aud_ca5", "mout_aud_pll_user", DIV_AUD0,
2531 0, 4),
2532
2533 /* DIV_AUD1 */
2534 DIV(CLK_DIV_SCLK_AUD_SLIMBUS, "div_sclk_aud_slimbus",
2535 "mout_aud_pll_user", DIV_AUD1, 16, 5),
2536 DIV(CLK_DIV_SCLK_AUD_UART, "div_sclk_aud_uart", "mout_aud_pll_user",
2537 DIV_AUD1, 12, 4),
2538 DIV(CLK_DIV_SCLK_AUD_PCM, "div_sclk_aud_pcm", "mout_sclk_aud_pcm",
2539 DIV_AUD1, 4, 8),
2540 DIV(CLK_DIV_SCLK_AUD_I2S, "div_sclk_aud_i2s", "mout_sclk_aud_i2s",
2541 DIV_AUD1, 0, 4),
2542};
2543
2544static struct samsung_gate_clock aud_gate_clks[] __initdata = {
2545 /* ENABLE_ACLK_AUD */
2546 GATE(CLK_ACLK_INTR_CTRL, "aclk_intr_ctrl", "div_aclk_aud",
2547 ENABLE_ACLK_AUD, 12, 0, 0),
2548 GATE(CLK_ACLK_SMMU_LPASSX, "aclk_smmu_lpassx", "div_aclk_aud",
2549 ENABLE_ACLK_AUD, 7, 0, 0),
2550 GATE(CLK_ACLK_XIU_LPASSX, "aclk_xiu_lpassx", "div_aclk_aud",
2551 ENABLE_ACLK_AUD, 0, 4, 0),
2552 GATE(CLK_ACLK_AUDNP_133, "aclk_audnp_133", "div_aclk_aud",
2553 ENABLE_ACLK_AUD, 0, 3, 0),
2554 GATE(CLK_ACLK_AUDND_133, "aclk_audnd_133", "div_aclk_aud",
2555 ENABLE_ACLK_AUD, 0, 2, 0),
2556 GATE(CLK_ACLK_SRAMC, "aclk_sramc", "div_aclk_aud", ENABLE_ACLK_AUD,
2557 0, 1, 0),
2558 GATE(CLK_ACLK_DMAC, "aclk_dmac", "div_aclk_aud", ENABLE_ACLK_AUD,
2559 0, CLK_IGNORE_UNUSED, 0),
2560
2561 /* ENABLE_PCLK_AUD */
2562 GATE(CLK_PCLK_WDT1, "pclk_wdt1", "div_aclk_aud", ENABLE_PCLK_AUD,
2563 13, 0, 0),
2564 GATE(CLK_PCLK_WDT0, "pclk_wdt0", "div_aclk_aud", ENABLE_PCLK_AUD,
2565 12, 0, 0),
2566 GATE(CLK_PCLK_SFR1, "pclk_sfr1", "div_aclk_aud", ENABLE_PCLK_AUD,
2567 11, 0, 0),
2568 GATE(CLK_PCLK_SMMU_LPASSX, "pclk_smmu_lpassx", "div_aclk_aud",
2569 ENABLE_PCLK_AUD, 10, 0, 0),
2570 GATE(CLK_PCLK_GPIO_AUD, "pclk_gpio_aud", "div_aclk_aud",
2571 ENABLE_PCLK_AUD, 9, CLK_IGNORE_UNUSED, 0),
2572 GATE(CLK_PCLK_PMU_AUD, "pclk_pmu_aud", "div_aclk_aud",
2573 ENABLE_PCLK_AUD, 8, CLK_IGNORE_UNUSED, 0),
2574 GATE(CLK_PCLK_SYSREG_AUD, "pclk_sysreg_aud", "div_aclk_aud",
2575 ENABLE_PCLK_AUD, 7, CLK_IGNORE_UNUSED, 0),
2576 GATE(CLK_PCLK_AUD_SLIMBUS, "pclk_aud_slimbus", "div_aclk_aud",
2577 ENABLE_PCLK_AUD, 6, 0, 0),
2578 GATE(CLK_PCLK_AUD_UART, "pclk_aud_uart", "div_aclk_aud",
2579 ENABLE_PCLK_AUD, 5, 0, 0),
2580 GATE(CLK_PCLK_AUD_PCM, "pclk_aud_pcm", "div_aclk_aud",
2581 ENABLE_PCLK_AUD, 4, 0, 0),
2582 GATE(CLK_PCLK_AUD_I2S, "pclk_aud_i2s", "div_aclk_aud",
2583 ENABLE_PCLK_AUD, 3, 0, 0),
2584 GATE(CLK_PCLK_TIMER, "pclk_timer", "div_aclk_aud", ENABLE_PCLK_AUD,
2585 2, 0, 0),
2586 GATE(CLK_PCLK_SFR0_CTRL, "pclk_sfr0_ctrl", "div_aclk_aud",
2587 ENABLE_PCLK_AUD, 0, 0, 0),
2588
2589 /* ENABLE_SCLK_AUD0 */
2590 GATE(CLK_ATCLK_AUD, "atclk_aud", "div_atclk_aud", ENABLE_SCLK_AUD0,
2591 2, 0, 0),
2592 GATE(CLK_PCLK_DBG_AUD, "pclk_dbg_aud", "div_pclk_dbg_aud",
2593 ENABLE_SCLK_AUD0, 1, 0, 0),
2594 GATE(CLK_SCLK_AUD_CA5, "sclk_aud_ca5", "div_aud_ca5", ENABLE_SCLK_AUD0,
2595 0, 0, 0),
2596
2597 /* ENABLE_SCLK_AUD1 */
2598 GATE(CLK_SCLK_JTAG_TCK, "sclk_jtag_tck", "ioclk_jtag_tclk",
2599 ENABLE_SCLK_AUD1, 6, 0, 0),
2600 GATE(CLK_SCLK_SLIMBUS_CLKIN, "sclk_slimbus_clkin", "ioclk_slimbus_clk",
2601 ENABLE_SCLK_AUD1, 5, 0, 0),
2602 GATE(CLK_SCLK_AUD_SLIMBUS, "sclk_aud_slimbus", "div_sclk_aud_slimbus",
2603 ENABLE_SCLK_AUD1, 4, 0, 0),
2604 GATE(CLK_SCLK_AUD_UART, "sclk_aud_uart", "div_sclk_aud_uart",
2605 ENABLE_SCLK_AUD1, 3, 0, 0),
2606 GATE(CLK_SCLK_AUD_PCM, "sclk_aud_pcm", "div_sclk_aud_pcm",
2607 ENABLE_SCLK_AUD1, 2, 0, 0),
2608 GATE(CLK_SCLK_I2S_BCLK, "sclk_i2s_bclk", "ioclk_i2s_bclk",
2609 ENABLE_SCLK_AUD1, 1, CLK_IGNORE_UNUSED, 0),
2610 GATE(CLK_SCLK_AUD_I2S, "sclk_aud_i2s", "div_sclk_aud_i2s",
2611 ENABLE_SCLK_AUD1, 0, CLK_IGNORE_UNUSED, 0),
2612};
2613
2614static struct samsung_cmu_info aud_cmu_info __initdata = {
2615 .mux_clks = aud_mux_clks,
2616 .nr_mux_clks = ARRAY_SIZE(aud_mux_clks),
2617 .div_clks = aud_div_clks,
2618 .nr_div_clks = ARRAY_SIZE(aud_div_clks),
2619 .gate_clks = aud_gate_clks,
2620 .nr_gate_clks = ARRAY_SIZE(aud_gate_clks),
2621 .fixed_clks = aud_fixed_clks,
2622 .nr_fixed_clks = ARRAY_SIZE(aud_fixed_clks),
2623 .nr_clk_ids = AUD_NR_CLK,
2624 .clk_regs = aud_clk_regs,
2625 .nr_clk_regs = ARRAY_SIZE(aud_clk_regs),
2626};
2627
2628static void __init exynos5433_cmu_aud_init(struct device_node *np)
2629{
2630 samsung_cmu_register_one(np, &aud_cmu_info);
2631}
2632CLK_OF_DECLARE(exynos5433_cmu_aud, "samsung,exynos5433-cmu-aud",
2633 exynos5433_cmu_aud_init);
diff --git a/include/dt-bindings/clock/exynos5433.h b/include/dt-bindings/clock/exynos5433.h
index fe0650fad766..4d150e244057 100644
--- a/include/dt-bindings/clock/exynos5433.h
+++ b/include/dt-bindings/clock/exynos5433.h
@@ -626,4 +626,57 @@
626 626
627#define DISP_NR_CLK 111 627#define DISP_NR_CLK 111
628 628
629/* CMU_AUD */
630#define CLK_MOUT_AUD_PLL_USER 1
631#define CLK_MOUT_SCLK_AUD_PCM 2
632#define CLK_MOUT_SCLK_AUD_I2S 3
633
634#define CLK_DIV_ATCLK_AUD 4
635#define CLK_DIV_PCLK_DBG_AUD 5
636#define CLK_DIV_ACLK_AUD 6
637#define CLK_DIV_AUD_CA5 7
638#define CLK_DIV_SCLK_AUD_SLIMBUS 8
639#define CLK_DIV_SCLK_AUD_UART 9
640#define CLK_DIV_SCLK_AUD_PCM 10
641#define CLK_DIV_SCLK_AUD_I2S 11
642
643#define CLK_ACLK_INTR_CTRL 12
644#define CLK_ACLK_AXIDS2_LPASSP 13
645#define CLK_ACLK_AXIDS1_LPASSP 14
646#define CLK_ACLK_AXI2APB1_LPASSP 15
647#define CLK_ACLK_AXI2APH_LPASSP 16
648#define CLK_ACLK_SMMU_LPASSX 17
649#define CLK_ACLK_AXIDS0_LPASSP 18
650#define CLK_ACLK_AXI2APB0_LPASSP 19
651#define CLK_ACLK_XIU_LPASSX 20
652#define CLK_ACLK_AUDNP_133 21
653#define CLK_ACLK_AUDND_133 22
654#define CLK_ACLK_SRAMC 23
655#define CLK_ACLK_DMAC 24
656#define CLK_PCLK_WDT1 25
657#define CLK_PCLK_WDT0 26
658#define CLK_PCLK_SFR1 27
659#define CLK_PCLK_SMMU_LPASSX 28
660#define CLK_PCLK_GPIO_AUD 29
661#define CLK_PCLK_PMU_AUD 30
662#define CLK_PCLK_SYSREG_AUD 31
663#define CLK_PCLK_AUD_SLIMBUS 32
664#define CLK_PCLK_AUD_UART 33
665#define CLK_PCLK_AUD_PCM 34
666#define CLK_PCLK_AUD_I2S 35
667#define CLK_PCLK_TIMER 36
668#define CLK_PCLK_SFR0_CTRL 37
669#define CLK_ATCLK_AUD 38
670#define CLK_PCLK_DBG_AUD 39
671#define CLK_SCLK_AUD_CA5 40
672#define CLK_SCLK_JTAG_TCK 41
673#define CLK_SCLK_SLIMBUS_CLKIN 42
674#define CLK_SCLK_AUD_SLIMBUS 43
675#define CLK_SCLK_AUD_UART 44
676#define CLK_SCLK_AUD_PCM 45
677#define CLK_SCLK_I2S_BCLK 46
678#define CLK_SCLK_AUD_I2S 47
679
680#define AUD_NR_CLK 48
681
629#endif /* _DT_BINDINGS_CLOCK_EXYNOS5433_H */ 682#endif /* _DT_BINDINGS_CLOCK_EXYNOS5433_H */
generated by cgit v1.2.2 (git 2.25.0) at 2025-09-06 03:56:17 -0400