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authorAlex Deucher <alexander.deucher@amd.com>2017-08-18 23:39:52 -0400
committerAlex Deucher <alexander.deucher@amd.com>2017-08-29 15:27:39 -0400
commit2d6fb10565ca13e7a0f6f4725f1c3da5a99a2bcc (patch)
treea3b1488851fa227f53c816c0778e7fbfb56bc3d5
parent9dd73b1e89d7eb3f5c0a00aa264e473364ba1aa6 (diff)
drm/amdgpu/gfx8: fix spelling typo in mqd allocation
Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-rw-r--r--drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c12
-rw-r--r--drivers/gpu/drm/amd/include/vi_structs.h4
2 files changed, 8 insertions, 8 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index 832e592fcd07..fc260c13b1da 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -4579,9 +4579,9 @@ static int gfx_v8_0_mqd_init(struct amdgpu_ring *ring)
4579 mqd->compute_misc_reserved = 0x00000003; 4579 mqd->compute_misc_reserved = 0x00000003;
4580 if (!(adev->flags & AMD_IS_APU)) { 4580 if (!(adev->flags & AMD_IS_APU)) {
4581 mqd->dynamic_cu_mask_addr_lo = lower_32_bits(ring->mqd_gpu_addr 4581 mqd->dynamic_cu_mask_addr_lo = lower_32_bits(ring->mqd_gpu_addr
4582 + offsetof(struct vi_mqd_allocation, dyamic_cu_mask)); 4582 + offsetof(struct vi_mqd_allocation, dynamic_cu_mask));
4583 mqd->dynamic_cu_mask_addr_hi = upper_32_bits(ring->mqd_gpu_addr 4583 mqd->dynamic_cu_mask_addr_hi = upper_32_bits(ring->mqd_gpu_addr
4584 + offsetof(struct vi_mqd_allocation, dyamic_cu_mask)); 4584 + offsetof(struct vi_mqd_allocation, dynamic_cu_mask));
4585 } 4585 }
4586 eop_base_addr = ring->eop_gpu_addr >> 8; 4586 eop_base_addr = ring->eop_gpu_addr >> 8;
4587 mqd->cp_hqd_eop_base_addr_lo = eop_base_addr; 4587 mqd->cp_hqd_eop_base_addr_lo = eop_base_addr;
@@ -4768,8 +4768,8 @@ static int gfx_v8_0_kiq_init_queue(struct amdgpu_ring *ring)
4768 mutex_unlock(&adev->srbm_mutex); 4768 mutex_unlock(&adev->srbm_mutex);
4769 } else { 4769 } else {
4770 memset((void *)mqd, 0, sizeof(struct vi_mqd_allocation)); 4770 memset((void *)mqd, 0, sizeof(struct vi_mqd_allocation));
4771 ((struct vi_mqd_allocation *)mqd)->dyamic_cu_mask = 0xFFFFFFFF; 4771 ((struct vi_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF;
4772 ((struct vi_mqd_allocation *)mqd)->dyamic_rb_mask = 0xFFFFFFFF; 4772 ((struct vi_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF;
4773 mutex_lock(&adev->srbm_mutex); 4773 mutex_lock(&adev->srbm_mutex);
4774 vi_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 4774 vi_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
4775 gfx_v8_0_mqd_init(ring); 4775 gfx_v8_0_mqd_init(ring);
@@ -4792,8 +4792,8 @@ static int gfx_v8_0_kcq_init_queue(struct amdgpu_ring *ring)
4792 4792
4793 if (!adev->gfx.in_reset && !adev->gfx.in_suspend) { 4793 if (!adev->gfx.in_reset && !adev->gfx.in_suspend) {
4794 memset((void *)mqd, 0, sizeof(struct vi_mqd_allocation)); 4794 memset((void *)mqd, 0, sizeof(struct vi_mqd_allocation));
4795 ((struct vi_mqd_allocation *)mqd)->dyamic_cu_mask = 0xFFFFFFFF; 4795 ((struct vi_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF;
4796 ((struct vi_mqd_allocation *)mqd)->dyamic_rb_mask = 0xFFFFFFFF; 4796 ((struct vi_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF;
4797 mutex_lock(&adev->srbm_mutex); 4797 mutex_lock(&adev->srbm_mutex);
4798 vi_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 4798 vi_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
4799 gfx_v8_0_mqd_init(ring); 4799 gfx_v8_0_mqd_init(ring);
diff --git a/drivers/gpu/drm/amd/include/vi_structs.h b/drivers/gpu/drm/amd/include/vi_structs.h
index ca93b5160ba6..3e606a761d0e 100644
--- a/drivers/gpu/drm/amd/include/vi_structs.h
+++ b/drivers/gpu/drm/amd/include/vi_structs.h
@@ -419,8 +419,8 @@ struct vi_mqd_allocation {
419 struct vi_mqd mqd; 419 struct vi_mqd mqd;
420 uint32_t wptr_poll_mem; 420 uint32_t wptr_poll_mem;
421 uint32_t rptr_report_mem; 421 uint32_t rptr_report_mem;
422 uint32_t dyamic_cu_mask; 422 uint32_t dynamic_cu_mask;
423 uint32_t dyamic_rb_mask; 423 uint32_t dynamic_rb_mask;
424}; 424};
425 425
426struct cz_mqd { 426struct cz_mqd {