drm/amd/powerplay: always use fast UCLK switching when UCLK DPM enabled

With UCLK DPM enabled, slow switching is not supported any more.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

1 files changed, 17 insertions, 20 deletions

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
index 10c80aae030f..cb3c3d69c3d3 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
@@ -830,6 +830,18 @@ static int vega20_enable_all_smu_features(struct pp_hwmgr *hwmgr)
         return 0;
 }
 
+static int vega20_notify_smc_display_change(struct pp_hwmgr *hwmgr)
+{
+        struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
+
+        if (data->smu_features[GNLD_DPM_UCLK].enabled)
+                return smum_send_msg_to_smc_with_parameter(hwmgr,
+                        PPSMC_MSG_SetUclkFastSwitch,
+                        1);
+
+        return 0;
+}
+
 static int vega20_send_clock_ratio(struct pp_hwmgr *hwmgr)
 {
         struct vega20_hwmgr *data =
@@ -1543,6 +1555,11 @@ static int vega20_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
                         "[EnableDPMTasks] Failed to enable all smu features!",
                         return result);
 
+        result = vega20_notify_smc_display_change(hwmgr);
+        PP_ASSERT_WITH_CODE(!result,
+                        "[EnableDPMTasks] Failed to notify smc display change!",
+                        return result);
+
         result = vega20_send_clock_ratio(hwmgr);
         PP_ASSERT_WITH_CODE(!result,
                         "[EnableDPMTasks] Failed to send clock ratio!",
@@ -1988,19 +2005,6 @@ static int vega20_read_sensor(struct pp_hwmgr *hwmgr, int idx,
         return ret;
 }
 
-static int vega20_notify_smc_display_change(struct pp_hwmgr *hwmgr,
-                bool has_disp)
-{
-        struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
-
-        if (data->smu_features[GNLD_DPM_UCLK].enabled)
-                return smum_send_msg_to_smc_with_parameter(hwmgr,
-                        PPSMC_MSG_SetUclkFastSwitch,
-                        has_disp ? 1 : 0);
-
-        return 0;
-}
-
 int vega20_display_clock_voltage_request(struct pp_hwmgr *hwmgr,
                 struct pp_display_clock_request *clock_req)
 {
@@ -2060,13 +2064,6 @@ static int vega20_notify_smc_display_config_after_ps_adjustment(
         struct pp_display_clock_request clock_req;
         int ret = 0;
 
-        if ((hwmgr->display_config->num_display > 1) &&
-             !hwmgr->display_config->multi_monitor_in_sync &&
-             !hwmgr->display_config->nb_pstate_switch_disable)
-                vega20_notify_smc_display_change(hwmgr, false);
-        else
-                vega20_notify_smc_display_change(hwmgr, true);
-
         min_clocks.dcefClock = hwmgr->display_config->min_dcef_set_clk;
         min_clocks.dcefClockInSR = hwmgr->display_config->min_dcef_deep_sleep_set_clk;
         min_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock;