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authorAndrew Lunn <andrew@lunn.ch>2018-08-09 09:38:45 -0400
committerDavid S. Miller <davem@davemloft.net>2018-08-09 14:08:20 -0400
commit2d2e1dd29962ce0e6bc2c35fe804d919bf3e7f68 (patch)
tree6c9adedf60fc3f56f608d7ea4de4ecb67134091a
parentf8236a0835597b166a9f0bab38b9b31bd932ce98 (diff)
net: dsa: mv88e6xxx: Cache the port cmode
The ports CMODE indicates the type of link between the MAC and the PHY. It is used often in the SERDES code. Rather than read it each time, cache its value. Signed-off-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
-rw-r--r--drivers/net/dsa/mv88e6xxx/chip.c38
-rw-r--r--drivers/net/dsa/mv88e6xxx/chip.h2
-rw-r--r--drivers/net/dsa/mv88e6xxx/port.c16
-rw-r--r--drivers/net/dsa/mv88e6xxx/port.h3
-rw-r--r--drivers/net/dsa/mv88e6xxx/serdes.c45
5 files changed, 57 insertions, 47 deletions
diff --git a/drivers/net/dsa/mv88e6xxx/chip.c b/drivers/net/dsa/mv88e6xxx/chip.c
index 4c9ae5b9440b..66e0281604df 100644
--- a/drivers/net/dsa/mv88e6xxx/chip.c
+++ b/drivers/net/dsa/mv88e6xxx/chip.c
@@ -2381,6 +2381,7 @@ static int mv88e6xxx_stats_setup(struct mv88e6xxx_chip *chip)
2381static int mv88e6xxx_setup(struct dsa_switch *ds) 2381static int mv88e6xxx_setup(struct dsa_switch *ds)
2382{ 2382{
2383 struct mv88e6xxx_chip *chip = ds->priv; 2383 struct mv88e6xxx_chip *chip = ds->priv;
2384 u8 cmode;
2384 int err; 2385 int err;
2385 int i; 2386 int i;
2386 2387
@@ -2389,6 +2390,17 @@ static int mv88e6xxx_setup(struct dsa_switch *ds)
2389 2390
2390 mutex_lock(&chip->reg_lock); 2391 mutex_lock(&chip->reg_lock);
2391 2392
2393 /* Cache the cmode of each port. */
2394 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
2395 if (chip->info->ops->port_get_cmode) {
2396 err = chip->info->ops->port_get_cmode(chip, i, &cmode);
2397 if (err)
2398 return err;
2399
2400 chip->ports[i].cmode = cmode;
2401 }
2402 }
2403
2392 /* Setup Switch Port Registers */ 2404 /* Setup Switch Port Registers */
2393 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 2405 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
2394 if (dsa_is_unused_port(ds, i)) 2406 if (dsa_is_unused_port(ds, i))
@@ -2697,6 +2709,7 @@ static const struct mv88e6xxx_ops mv88e6085_ops = {
2697 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2709 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2698 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2710 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2699 .port_link_state = mv88e6352_port_link_state, 2711 .port_link_state = mv88e6352_port_link_state,
2712 .port_get_cmode = mv88e6185_port_get_cmode,
2700 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 2713 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
2701 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 2714 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2702 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2715 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
@@ -2730,6 +2743,7 @@ static const struct mv88e6xxx_ops mv88e6095_ops = {
2730 .port_set_egress_floods = mv88e6185_port_set_egress_floods, 2743 .port_set_egress_floods = mv88e6185_port_set_egress_floods,
2731 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 2744 .port_set_upstream_port = mv88e6095_port_set_upstream_port,
2732 .port_link_state = mv88e6185_port_link_state, 2745 .port_link_state = mv88e6185_port_link_state,
2746 .port_get_cmode = mv88e6185_port_get_cmode,
2733 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 2747 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
2734 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 2748 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2735 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2749 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
@@ -2765,6 +2779,7 @@ static const struct mv88e6xxx_ops mv88e6097_ops = {
2765 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2779 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2766 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2780 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2767 .port_link_state = mv88e6352_port_link_state, 2781 .port_link_state = mv88e6352_port_link_state,
2782 .port_get_cmode = mv88e6185_port_get_cmode,
2768 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 2783 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
2769 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 2784 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2770 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2785 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
@@ -2798,6 +2813,7 @@ static const struct mv88e6xxx_ops mv88e6123_ops = {
2798 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2813 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2799 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2814 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2800 .port_link_state = mv88e6352_port_link_state, 2815 .port_link_state = mv88e6352_port_link_state,
2816 .port_get_cmode = mv88e6185_port_get_cmode,
2801 .stats_snapshot = mv88e6320_g1_stats_snapshot, 2817 .stats_snapshot = mv88e6320_g1_stats_snapshot,
2802 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 2818 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2803 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2819 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
@@ -2834,6 +2850,7 @@ static const struct mv88e6xxx_ops mv88e6131_ops = {
2834 .port_pause_limit = mv88e6097_port_pause_limit, 2850 .port_pause_limit = mv88e6097_port_pause_limit,
2835 .port_set_pause = mv88e6185_port_set_pause, 2851 .port_set_pause = mv88e6185_port_set_pause,
2836 .port_link_state = mv88e6352_port_link_state, 2852 .port_link_state = mv88e6352_port_link_state,
2853 .port_get_cmode = mv88e6185_port_get_cmode,
2837 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 2854 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
2838 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 2855 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2839 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2856 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
@@ -2876,6 +2893,7 @@ static const struct mv88e6xxx_ops mv88e6141_ops = {
2876 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2893 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2877 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2894 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2878 .port_link_state = mv88e6352_port_link_state, 2895 .port_link_state = mv88e6352_port_link_state,
2896 .port_get_cmode = mv88e6352_port_get_cmode,
2879 .stats_snapshot = mv88e6390_g1_stats_snapshot, 2897 .stats_snapshot = mv88e6390_g1_stats_snapshot,
2880 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 2898 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2881 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 2899 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
@@ -2915,6 +2933,7 @@ static const struct mv88e6xxx_ops mv88e6161_ops = {
2915 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2933 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2916 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2934 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2917 .port_link_state = mv88e6352_port_link_state, 2935 .port_link_state = mv88e6352_port_link_state,
2936 .port_get_cmode = mv88e6185_port_get_cmode,
2918 .stats_snapshot = mv88e6320_g1_stats_snapshot, 2937 .stats_snapshot = mv88e6320_g1_stats_snapshot,
2919 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 2938 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2920 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2939 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
@@ -2947,6 +2966,7 @@ static const struct mv88e6xxx_ops mv88e6165_ops = {
2947 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2966 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2948 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2967 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2949 .port_link_state = mv88e6352_port_link_state, 2968 .port_link_state = mv88e6352_port_link_state,
2969 .port_get_cmode = mv88e6185_port_get_cmode,
2950 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 2970 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
2951 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 2971 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2952 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2972 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
@@ -2987,6 +3007,7 @@ static const struct mv88e6xxx_ops mv88e6171_ops = {
2987 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3007 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2988 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3008 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2989 .port_link_state = mv88e6352_port_link_state, 3009 .port_link_state = mv88e6352_port_link_state,
3010 .port_get_cmode = mv88e6352_port_get_cmode,
2990 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3011 .stats_snapshot = mv88e6320_g1_stats_snapshot,
2991 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3012 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2992 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3013 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
@@ -3027,6 +3048,7 @@ static const struct mv88e6xxx_ops mv88e6172_ops = {
3027 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3048 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3028 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3049 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3029 .port_link_state = mv88e6352_port_link_state, 3050 .port_link_state = mv88e6352_port_link_state,
3051 .port_get_cmode = mv88e6352_port_get_cmode,
3030 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3052 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3031 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3053 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3032 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3054 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
@@ -3068,6 +3090,7 @@ static const struct mv88e6xxx_ops mv88e6175_ops = {
3068 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3090 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3069 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3091 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3070 .port_link_state = mv88e6352_port_link_state, 3092 .port_link_state = mv88e6352_port_link_state,
3093 .port_get_cmode = mv88e6352_port_get_cmode,
3071 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3094 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3072 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3095 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3073 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3096 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
@@ -3108,6 +3131,7 @@ static const struct mv88e6xxx_ops mv88e6176_ops = {
3108 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3131 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3109 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3132 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3110 .port_link_state = mv88e6352_port_link_state, 3133 .port_link_state = mv88e6352_port_link_state,
3134 .port_get_cmode = mv88e6352_port_get_cmode,
3111 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3135 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3112 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3136 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3113 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3137 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
@@ -3143,6 +3167,7 @@ static const struct mv88e6xxx_ops mv88e6185_ops = {
3143 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 3167 .port_set_upstream_port = mv88e6095_port_set_upstream_port,
3144 .port_set_pause = mv88e6185_port_set_pause, 3168 .port_set_pause = mv88e6185_port_set_pause,
3145 .port_link_state = mv88e6185_port_link_state, 3169 .port_link_state = mv88e6185_port_link_state,
3170 .port_get_cmode = mv88e6185_port_get_cmode,
3146 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3171 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
3147 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3172 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3148 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3173 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
@@ -3181,6 +3206,7 @@ static const struct mv88e6xxx_ops mv88e6190_ops = {
3181 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3206 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3182 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3207 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3183 .port_link_state = mv88e6352_port_link_state, 3208 .port_link_state = mv88e6352_port_link_state,
3209 .port_get_cmode = mv88e6352_port_get_cmode,
3184 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3210 .stats_snapshot = mv88e6390_g1_stats_snapshot,
3185 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 3211 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3186 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3212 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
@@ -3220,6 +3246,7 @@ static const struct mv88e6xxx_ops mv88e6190x_ops = {
3220 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3246 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3221 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3247 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3222 .port_link_state = mv88e6352_port_link_state, 3248 .port_link_state = mv88e6352_port_link_state,
3249 .port_get_cmode = mv88e6352_port_get_cmode,
3223 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3250 .stats_snapshot = mv88e6390_g1_stats_snapshot,
3224 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 3251 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3225 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3252 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
@@ -3259,6 +3286,7 @@ static const struct mv88e6xxx_ops mv88e6191_ops = {
3259 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3286 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3260 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3287 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3261 .port_link_state = mv88e6352_port_link_state, 3288 .port_link_state = mv88e6352_port_link_state,
3289 .port_get_cmode = mv88e6352_port_get_cmode,
3262 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3290 .stats_snapshot = mv88e6390_g1_stats_snapshot,
3263 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 3291 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3264 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3292 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
@@ -3303,6 +3331,7 @@ static const struct mv88e6xxx_ops mv88e6240_ops = {
3303 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3331 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3304 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3332 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3305 .port_link_state = mv88e6352_port_link_state, 3333 .port_link_state = mv88e6352_port_link_state,
3334 .port_get_cmode = mv88e6352_port_get_cmode,
3306 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3335 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3307 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3336 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3308 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3337 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
@@ -3345,6 +3374,7 @@ static const struct mv88e6xxx_ops mv88e6290_ops = {
3345 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3374 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3346 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3375 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3347 .port_link_state = mv88e6352_port_link_state, 3376 .port_link_state = mv88e6352_port_link_state,
3377 .port_get_cmode = mv88e6352_port_get_cmode,
3348 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3378 .stats_snapshot = mv88e6390_g1_stats_snapshot,
3349 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 3379 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3350 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3380 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
@@ -3389,6 +3419,7 @@ static const struct mv88e6xxx_ops mv88e6320_ops = {
3389 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3419 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3390 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3420 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3391 .port_link_state = mv88e6352_port_link_state, 3421 .port_link_state = mv88e6352_port_link_state,
3422 .port_get_cmode = mv88e6352_port_get_cmode,
3392 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3423 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3393 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3424 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3394 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3425 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
@@ -3430,6 +3461,7 @@ static const struct mv88e6xxx_ops mv88e6321_ops = {
3430 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3461 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3431 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3462 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3432 .port_link_state = mv88e6352_port_link_state, 3463 .port_link_state = mv88e6352_port_link_state,
3464 .port_get_cmode = mv88e6352_port_get_cmode,
3433 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3465 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3434 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3466 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3435 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3467 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
@@ -3470,6 +3502,7 @@ static const struct mv88e6xxx_ops mv88e6341_ops = {
3470 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3502 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3471 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3503 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3472 .port_link_state = mv88e6352_port_link_state, 3504 .port_link_state = mv88e6352_port_link_state,
3505 .port_get_cmode = mv88e6352_port_get_cmode,
3473 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3506 .stats_snapshot = mv88e6390_g1_stats_snapshot,
3474 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3507 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3475 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3508 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
@@ -3512,6 +3545,7 @@ static const struct mv88e6xxx_ops mv88e6350_ops = {
3512 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3545 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3513 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3546 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3514 .port_link_state = mv88e6352_port_link_state, 3547 .port_link_state = mv88e6352_port_link_state,
3548 .port_get_cmode = mv88e6352_port_get_cmode,
3515 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3549 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3516 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3550 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3517 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3551 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
@@ -3550,6 +3584,7 @@ static const struct mv88e6xxx_ops mv88e6351_ops = {
3550 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3584 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3551 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3585 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3552 .port_link_state = mv88e6352_port_link_state, 3586 .port_link_state = mv88e6352_port_link_state,
3587 .port_get_cmode = mv88e6352_port_get_cmode,
3553 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3588 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3554 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3589 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3555 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3590 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
@@ -3592,6 +3627,7 @@ static const struct mv88e6xxx_ops mv88e6352_ops = {
3592 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3627 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3593 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3628 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3594 .port_link_state = mv88e6352_port_link_state, 3629 .port_link_state = mv88e6352_port_link_state,
3630 .port_get_cmode = mv88e6352_port_get_cmode,
3595 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3631 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3596 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3632 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3597 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3633 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
@@ -3639,6 +3675,7 @@ static const struct mv88e6xxx_ops mv88e6390_ops = {
3639 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3675 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3640 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3676 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3641 .port_link_state = mv88e6352_port_link_state, 3677 .port_link_state = mv88e6352_port_link_state,
3678 .port_get_cmode = mv88e6352_port_get_cmode,
3642 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3679 .stats_snapshot = mv88e6390_g1_stats_snapshot,
3643 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 3680 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3644 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3681 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
@@ -3683,6 +3720,7 @@ static const struct mv88e6xxx_ops mv88e6390x_ops = {
3683 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3720 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3684 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3721 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3685 .port_link_state = mv88e6352_port_link_state, 3722 .port_link_state = mv88e6352_port_link_state,
3723 .port_get_cmode = mv88e6352_port_get_cmode,
3686 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3724 .stats_snapshot = mv88e6390_g1_stats_snapshot,
3687 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 3725 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3688 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3726 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
diff --git a/drivers/net/dsa/mv88e6xxx/chip.h b/drivers/net/dsa/mv88e6xxx/chip.h
index cdc028fcdf96..08c74c88dbde 100644
--- a/drivers/net/dsa/mv88e6xxx/chip.h
+++ b/drivers/net/dsa/mv88e6xxx/chip.h
@@ -197,6 +197,7 @@ struct mv88e6xxx_port {
197 u64 atu_full_violation; 197 u64 atu_full_violation;
198 u64 vtu_member_violation; 198 u64 vtu_member_violation;
199 u64 vtu_miss_violation; 199 u64 vtu_miss_violation;
200 u8 cmode;
200}; 201};
201 202
202struct mv88e6xxx_chip { 203struct mv88e6xxx_chip {
@@ -390,6 +391,7 @@ struct mv88e6xxx_ops {
390 */ 391 */
391 int (*port_set_cmode)(struct mv88e6xxx_chip *chip, int port, 392 int (*port_set_cmode)(struct mv88e6xxx_chip *chip, int port,
392 phy_interface_t mode); 393 phy_interface_t mode);
394 int (*port_get_cmode)(struct mv88e6xxx_chip *chip, int port, u8 *cmode);
393 395
394 /* Some devices have a per port register indicating what is 396 /* Some devices have a per port register indicating what is
395 * the upstream port this port should forward to. 397 * the upstream port this port should forward to.
diff --git a/drivers/net/dsa/mv88e6xxx/port.c b/drivers/net/dsa/mv88e6xxx/port.c
index 2ff370cb2f3c..d236f3420f2d 100644
--- a/drivers/net/dsa/mv88e6xxx/port.c
+++ b/drivers/net/dsa/mv88e6xxx/port.c
@@ -385,11 +385,12 @@ int mv88e6390x_port_set_cmode(struct mv88e6xxx_chip *chip, int port,
385 return err; 385 return err;
386 } 386 }
387 387
388 chip->ports[port].cmode = cmode;
389
388 return 0; 390 return 0;
389} 391}
390 392
391/* mv88e6185 only has 3 bits for CMODE */ 393int mv88e6185_port_get_cmode(struct mv88e6xxx_chip *chip, int port, u8 *cmode)
392static int mv88e6185_port_get_cmode(struct mv88e6xxx_chip *chip, int port)
393{ 394{
394 int err; 395 int err;
395 u16 reg; 396 u16 reg;
@@ -398,10 +399,12 @@ static int mv88e6185_port_get_cmode(struct mv88e6xxx_chip *chip, int port)
398 if (err) 399 if (err)
399 return err; 400 return err;
400 401
401 return reg & MV88E6185_PORT_STS_CMODE_MASK; 402 *cmode = reg & MV88E6185_PORT_STS_CMODE_MASK;
403
404 return 0;
402} 405}
403 406
404int mv88e6xxx_port_get_cmode(struct mv88e6xxx_chip *chip, int port, u8 *cmode) 407int mv88e6352_port_get_cmode(struct mv88e6xxx_chip *chip, int port, u8 *cmode)
405{ 408{
406 int err; 409 int err;
407 u16 reg; 410 u16 reg;
@@ -457,10 +460,7 @@ int mv88e6185_port_link_state(struct mv88e6xxx_chip *chip, int port,
457 struct phylink_link_state *state) 460 struct phylink_link_state *state)
458{ 461{
459 if (state->interface == PHY_INTERFACE_MODE_1000BASEX) { 462 if (state->interface == PHY_INTERFACE_MODE_1000BASEX) {
460 int cmode = mv88e6185_port_get_cmode(chip, port); 463 u8 cmode = chip->ports[port].cmode;
461
462 if (cmode < 0)
463 return cmode;
464 464
465 /* When a port is in "Cross-chip serdes" mode, it uses 465 /* When a port is in "Cross-chip serdes" mode, it uses
466 * 1000Base-X full duplex mode, but there is no automatic 466 * 1000Base-X full duplex mode, but there is no automatic
diff --git a/drivers/net/dsa/mv88e6xxx/port.h b/drivers/net/dsa/mv88e6xxx/port.h
index 9b8d2b229907..f32f56af8e35 100644
--- a/drivers/net/dsa/mv88e6xxx/port.h
+++ b/drivers/net/dsa/mv88e6xxx/port.h
@@ -311,7 +311,8 @@ int mv88e6390_port_pause_limit(struct mv88e6xxx_chip *chip, int port, u8 in,
311 u8 out); 311 u8 out);
312int mv88e6390x_port_set_cmode(struct mv88e6xxx_chip *chip, int port, 312int mv88e6390x_port_set_cmode(struct mv88e6xxx_chip *chip, int port,
313 phy_interface_t mode); 313 phy_interface_t mode);
314int mv88e6xxx_port_get_cmode(struct mv88e6xxx_chip *chip, int port, u8 *cmode); 314int mv88e6185_port_get_cmode(struct mv88e6xxx_chip *chip, int port, u8 *cmode);
315int mv88e6352_port_get_cmode(struct mv88e6xxx_chip *chip, int port, u8 *cmode);
315int mv88e6185_port_link_state(struct mv88e6xxx_chip *chip, int port, 316int mv88e6185_port_link_state(struct mv88e6xxx_chip *chip, int port,
316 struct phylink_link_state *state); 317 struct phylink_link_state *state);
317int mv88e6352_port_link_state(struct mv88e6xxx_chip *chip, int port, 318int mv88e6352_port_link_state(struct mv88e6xxx_chip *chip, int port,
diff --git a/drivers/net/dsa/mv88e6xxx/serdes.c b/drivers/net/dsa/mv88e6xxx/serdes.c
index b57d4271acdb..064d0bb8fe02 100644
--- a/drivers/net/dsa/mv88e6xxx/serdes.c
+++ b/drivers/net/dsa/mv88e6xxx/serdes.c
@@ -73,14 +73,7 @@ static int mv88e6352_serdes_power_set(struct mv88e6xxx_chip *chip, bool on)
73 73
74static bool mv88e6352_port_has_serdes(struct mv88e6xxx_chip *chip, int port) 74static bool mv88e6352_port_has_serdes(struct mv88e6xxx_chip *chip, int port)
75{ 75{
76 u8 cmode; 76 u8 cmode = chip->ports[port].cmode;
77 int err;
78
79 err = mv88e6xxx_port_get_cmode(chip, port, &cmode);
80 if (err) {
81 dev_err(chip->dev, "failed to read cmode\n");
82 return false;
83 }
84 77
85 if ((cmode == MV88E6XXX_PORT_STS_CMODE_100BASE_X) || 78 if ((cmode == MV88E6XXX_PORT_STS_CMODE_100BASE_X) ||
86 (cmode == MV88E6XXX_PORT_STS_CMODE_1000BASE_X) || 79 (cmode == MV88E6XXX_PORT_STS_CMODE_1000BASE_X) ||
@@ -195,12 +188,7 @@ int mv88e6352_serdes_get_stats(struct mv88e6xxx_chip *chip, int port,
195 */ 188 */
196static int mv88e6390_serdes_get_lane(struct mv88e6xxx_chip *chip, int port) 189static int mv88e6390_serdes_get_lane(struct mv88e6xxx_chip *chip, int port)
197{ 190{
198 u8 cmode; 191 u8 cmode = chip->ports[port].cmode;
199 int err;
200
201 err = mv88e6xxx_port_get_cmode(chip, port, &cmode);
202 if (err)
203 return err;
204 192
205 switch (port) { 193 switch (port) {
206 case 9: 194 case 9:
@@ -227,19 +215,10 @@ static int mv88e6390_serdes_get_lane(struct mv88e6xxx_chip *chip, int port)
227static int mv88e6390x_serdes_get_lane(struct mv88e6xxx_chip *chip, int port) 215static int mv88e6390x_serdes_get_lane(struct mv88e6xxx_chip *chip, int port)
228{ 216{
229 u8 cmode_port9, cmode_port10, cmode_port; 217 u8 cmode_port9, cmode_port10, cmode_port;
230 int err;
231 218
232 err = mv88e6xxx_port_get_cmode(chip, 9, &cmode_port9); 219 cmode_port9 = chip->ports[9].cmode;
233 if (err) 220 cmode_port10 = chip->ports[10].cmode;
234 return err; 221 cmode_port = chip->ports[port].cmode;
235
236 err = mv88e6xxx_port_get_cmode(chip, 10, &cmode_port10);
237 if (err)
238 return err;
239
240 err = mv88e6xxx_port_get_cmode(chip, port, &cmode_port);
241 if (err)
242 return err;
243 222
244 switch (port) { 223 switch (port) {
245 case 2: 224 case 2:
@@ -365,12 +344,7 @@ static int mv88e6390_serdes_power_sgmii(struct mv88e6xxx_chip *chip, int lane,
365static int mv88e6390_serdes_power_lane(struct mv88e6xxx_chip *chip, int port, 344static int mv88e6390_serdes_power_lane(struct mv88e6xxx_chip *chip, int port,
366 int lane, bool on) 345 int lane, bool on)
367{ 346{
368 u8 cmode; 347 u8 cmode = chip->ports[port].cmode;
369 int err;
370
371 err = mv88e6xxx_port_get_cmode(chip, port, &cmode);
372 if (err)
373 return err;
374 348
375 switch (cmode) { 349 switch (cmode) {
376 case MV88E6XXX_PORT_STS_CMODE_SGMII: 350 case MV88E6XXX_PORT_STS_CMODE_SGMII:
@@ -427,16 +401,11 @@ int mv88e6390x_serdes_power(struct mv88e6xxx_chip *chip, int port, bool on)
427 401
428int mv88e6341_serdes_power(struct mv88e6xxx_chip *chip, int port, bool on) 402int mv88e6341_serdes_power(struct mv88e6xxx_chip *chip, int port, bool on)
429{ 403{
430 int err; 404 u8 cmode = chip->ports[port].cmode;
431 u8 cmode;
432 405
433 if (port != 5) 406 if (port != 5)
434 return 0; 407 return 0;
435 408
436 err = mv88e6xxx_port_get_cmode(chip, port, &cmode);
437 if (err)
438 return err;
439
440 if (cmode == MV88E6XXX_PORT_STS_CMODE_1000BASE_X || 409 if (cmode == MV88E6XXX_PORT_STS_CMODE_1000BASE_X ||
441 cmode == MV88E6XXX_PORT_STS_CMODE_SGMII || 410 cmode == MV88E6XXX_PORT_STS_CMODE_SGMII ||
442 cmode == MV88E6XXX_PORT_STS_CMODE_2500BASEX) 411 cmode == MV88E6XXX_PORT_STS_CMODE_2500BASEX)