Merge tag 'tegra-for-4.2-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into clk-next

clk: tegra: Changes for v4.2-rc1

This contains the EMC clock driver that's been exhaustively reviewed and
tested. It also includes a change to the clock core that allows a clock
provider to perform low-level reparenting of clocks. This is required by
the EMC clock driver because the reparenting needs to be done at a very
specific point in time during the EMC frequency switch.

13 files changed, 637 insertions, 16 deletions

diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra124-car.txt b/Documentation/devicetree/bindings/clock/nvidia,tegra124-car.txt
index c6620bc96703..7f02fb4ca4ad 100644
--- a/Documentation/devicetree/bindings/clock/nvidia,tegra124-car.txt
+++ b/Documentation/devicetree/bindings/clock/nvidia,tegra124-car.txt
@@ -20,15 +20,38 @@ Required properties :
 - #reset-cells : Should be 1.
   In clock consumers, this cell represents the bit number in the CAR's
   array of CLK_RST_CONTROLLER_RST_DEVICES_* registers.
+- nvidia,external-memory-controller : phandle of the EMC driver.
+
+The node should contain a "emc-timings" subnode for each supported RAM type (see
+field RAM_CODE in register PMC_STRAPPING_OPT_A).
+
+Required properties for "emc-timings" nodes :
+- nvidia,ram-code : Should contain the value of RAM_CODE this timing set
+  is used for.
+
+Each "emc-timings" node should contain a "timing" subnode for every supported
+EMC clock rate.
+
+Required properties for "timing" nodes :
+- clock-frequency : Should contain the memory clock rate to which this timing
+relates.
+- nvidia,parent-clock-frequency : Should contain the rate at which the current
+parent of the EMC clock should be running at this timing.
+- clocks : Must contain an entry for each entry in clock-names.
+  See ../clocks/clock-bindings.txt for details.
+- clock-names : Must include the following entries:
+  - emc-parent : the clock that should be the parent of the EMC clock at this
+timing.
 
 Example SoC include file:
 
 / {
-        tegra_car: clock {
+        tegra_car: clock@60006000 {
                 compatible = "nvidia,tegra124-car";
                 reg = <0x60006000 0x1000>;
                 #clock-cells = <1>;
                 #reset-cells = <1>;
+                nvidia,external-memory-controller = <&emc>;
         };
 
         usb@c5004000 {
@@ -62,4 +85,23 @@ Example board file:
         &tegra_car {
                 clocks = <&clk_32k> <&osc>;
         };
+
+        clock@60006000 {
+                emc-timings-3 {
+                        nvidia,ram-code = <3>;
+
+                        timing-12750000 {
+                                clock-frequency = <12750000>;
+                                nvidia,parent-clock-frequency = <408000000>;
+                                clocks = <&tegra_car TEGRA124_CLK_PLL_P>;
+                                clock-names = "emc-parent";
+                        };
+                        timing-20400000 {
+                                clock-frequency = <20400000>;
+                                nvidia,parent-clock-frequency = <408000000>;
+                                clocks = <&tegra_car TEGRA124_CLK_PLL_P>;
+                                clock-names = "emc-parent";
+                        };
+                };
+        };
 };
diff --git a/Documentation/devicetree/bindings/misc/nvidia,tegra20-apbmisc.txt b/Documentation/devicetree/bindings/misc/nvidia,tegra20-apbmisc.txt
index 47b205cc9cc7..4556359c5876 100644
--- a/Documentation/devicetree/bindings/misc/nvidia,tegra20-apbmisc.txt
+++ b/Documentation/devicetree/bindings/misc/nvidia,tegra20-apbmisc.txt
@@ -10,3 +10,5 @@ Required properties:
        The second entry gives the physical address and length of the
        registers indicating the strapping options.
 
+Optional properties:
+- nvidia,long-ram-code: If present, the RAM code is long (4 bit). If not, short (2 bit).
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 1dd4f9d8bcb6..42f7120ca9ce 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -176,3 +176,4 @@ endmenu
 source "drivers/clk/mvebu/Kconfig"
 
 source "drivers/clk/samsung/Kconfig"
+source "drivers/clk/tegra/Kconfig"
diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
index 059e5d25c9ba..ddb4b541016f 100644
--- a/drivers/clk/clk.c
+++ b/drivers/clk/clk.c
@@ -1660,6 +1660,14 @@ static void clk_core_reparent(struct clk_core *core,
         __clk_recalc_rates(core, POST_RATE_CHANGE);
 }
 
+void clk_hw_reparent(struct clk_hw *hw, struct clk_hw *new_parent)
+{
+        if (!hw)
+                return;
+
+        clk_core_reparent(hw->core, !new_parent ? NULL : new_parent->core);
+}
+
 /**
  * clk_has_parent - check if a clock is a possible parent for another
  * @clk: clock source
diff --git a/drivers/clk/tegra/Kconfig b/drivers/clk/tegra/Kconfig
new file mode 100644
index 000000000000..1ba30d1e14f2
--- /dev/null
+++ b/drivers/clk/tegra/Kconfig
@@ -0,0 +1,3 @@
+config TEGRA_CLK_EMC
+        def_bool y
+        depends on TEGRA124_EMC
diff --git a/drivers/clk/tegra/Makefile b/drivers/clk/tegra/Makefile
index edb8358fa6ce..aec862ba7a17 100644
--- a/drivers/clk/tegra/Makefile
+++ b/drivers/clk/tegra/Makefile
@@ -11,6 +11,7 @@ obj-y					+= clk-tegra-periph.o
 obj-y                                   += clk-tegra-pmc.o
 obj-y                                   += clk-tegra-fixed.o
 obj-y                                   += clk-tegra-super-gen4.o
+obj-$(CONFIG_TEGRA_CLK_EMC)             += clk-emc.o
 obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += clk-tegra20.o
 obj-$(CONFIG_ARCH_TEGRA_3x_SOC)         += clk-tegra30.o
 obj-$(CONFIG_ARCH_TEGRA_114_SOC)        += clk-tegra114.o
diff --git a/drivers/clk/tegra/clk-emc.c b/drivers/clk/tegra/clk-emc.c
new file mode 100644
index 000000000000..7649685c86bc
--- /dev/null
+++ b/drivers/clk/tegra/clk-emc.c
@@ -0,0 +1,538 @@
+/*
+ * drivers/clk/tegra/clk-emc.c
+ *
+ * Copyright (c) 2014, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Author:
+ *      Mikko Perttunen <mperttunen@nvidia.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/clk.h>
+#include <linux/clkdev.h>
+#include <linux/delay.h>
+#include <linux/module.h>
+#include <linux/of_address.h>
+#include <linux/of_platform.h>
+#include <linux/platform_device.h>
+#include <linux/sort.h>
+#include <linux/string.h>
+
+#include <soc/tegra/fuse.h>
+#include <soc/tegra/emc.h>
+
+#include "clk.h"
+
+#define CLK_SOURCE_EMC 0x19c
+
+#define CLK_SOURCE_EMC_EMC_2X_CLK_DIVISOR_SHIFT 0
+#define CLK_SOURCE_EMC_EMC_2X_CLK_DIVISOR_MASK 0xff
+#define CLK_SOURCE_EMC_EMC_2X_CLK_DIVISOR(x) (((x) & CLK_SOURCE_EMC_EMC_2X_CLK_DIVISOR_MASK) << \
+                                              CLK_SOURCE_EMC_EMC_2X_CLK_DIVISOR_SHIFT)
+
+#define CLK_SOURCE_EMC_EMC_2X_CLK_SRC_SHIFT 29
+#define CLK_SOURCE_EMC_EMC_2X_CLK_SRC_MASK 0x7
+#define CLK_SOURCE_EMC_EMC_2X_CLK_SRC(x) (((x) & CLK_SOURCE_EMC_EMC_2X_CLK_SRC_MASK) << \
+                                          CLK_SOURCE_EMC_EMC_2X_CLK_SRC_SHIFT)
+
+static const char * const emc_parent_clk_names[] = {
+        "pll_m", "pll_c", "pll_p", "clk_m", "pll_m_ud",
+        "pll_c2", "pll_c3", "pll_c_ud"
+};
+
+/*
+ * List of clock sources for various parents the EMC clock can have.
+ * When we change the timing to a timing with a parent that has the same
+ * clock source as the current parent, we must first change to a backup
+ * timing that has a different clock source.
+ */
+
+#define EMC_SRC_PLL_M 0
+#define EMC_SRC_PLL_C 1
+#define EMC_SRC_PLL_P 2
+#define EMC_SRC_CLK_M 3
+#define EMC_SRC_PLL_C2 4
+#define EMC_SRC_PLL_C3 5
+
+static const char emc_parent_clk_sources[] = {
+        EMC_SRC_PLL_M, EMC_SRC_PLL_C, EMC_SRC_PLL_P, EMC_SRC_CLK_M,
+        EMC_SRC_PLL_M, EMC_SRC_PLL_C2, EMC_SRC_PLL_C3, EMC_SRC_PLL_C
+};
+
+struct emc_timing {
+        unsigned long rate, parent_rate;
+        u8 parent_index;
+        struct clk *parent;
+        u32 ram_code;
+};
+
+struct tegra_clk_emc {
+        struct clk_hw hw;
+        void __iomem *clk_regs;
+        struct clk *prev_parent;
+        bool changing_timing;
+
+        struct device_node *emc_node;
+        struct tegra_emc *emc;
+
+        int num_timings;
+        struct emc_timing *timings;
+        spinlock_t *lock;
+};
+
+/* Common clock framework callback implementations */
+
+static unsigned long emc_recalc_rate(struct clk_hw *hw,
+                                     unsigned long parent_rate)
+{
+        struct tegra_clk_emc *tegra;
+        u32 val, div;
+
+        tegra = container_of(hw, struct tegra_clk_emc, hw);
+
+        /*
+         * CCF wrongly assumes that the parent won't change during set_rate,
+         * so get the parent rate explicitly.
+         */
+        parent_rate = __clk_get_rate(__clk_get_parent(hw->clk));
+
+        val = readl(tegra->clk_regs + CLK_SOURCE_EMC);
+        div = val & CLK_SOURCE_EMC_EMC_2X_CLK_DIVISOR_MASK;
+
+        return parent_rate / (div + 2) * 2;
+}
+
+/*
+ * Rounds up unless no higher rate exists, in which case down. This way is
+ * safer since things have EMC rate floors. Also don't touch parent_rate
+ * since we don't want the CCF to play with our parent clocks.
+ */
+static long emc_determine_rate(struct clk_hw *hw, unsigned long rate,
+                               unsigned long min_rate,
+                               unsigned long max_rate,
+                               unsigned long *best_parent_rate,
+                               struct clk_hw **best_parent_hw)
+{
+        struct tegra_clk_emc *tegra;
+        u8 ram_code = tegra_read_ram_code();
+        struct emc_timing *timing = NULL;
+        int i;
+
+        tegra = container_of(hw, struct tegra_clk_emc, hw);
+
+        for (i = 0; i < tegra->num_timings; i++) {
+                if (tegra->timings[i].ram_code != ram_code)
+                        continue;
+
+                timing = tegra->timings + i;
+
+                if (timing->rate > max_rate) {
+                        i = min(i, 1);
+                        return tegra->timings[i - 1].rate;
+                }
+
+                if (timing->rate < min_rate)
+                        continue;
+
+                if (timing->rate >= rate)
+                        return timing->rate;
+        }
+
+        if (timing)
+                return timing->rate;
+
+        return __clk_get_rate(hw->clk);
+}
+
+static u8 emc_get_parent(struct clk_hw *hw)
+{
+        struct tegra_clk_emc *tegra;
+        u32 val;
+
+        tegra = container_of(hw, struct tegra_clk_emc, hw);
+
+        val = readl(tegra->clk_regs + CLK_SOURCE_EMC);
+
+        return (val >> CLK_SOURCE_EMC_EMC_2X_CLK_SRC_SHIFT)
+                & CLK_SOURCE_EMC_EMC_2X_CLK_SRC_MASK;
+}
+
+static struct tegra_emc *emc_ensure_emc_driver(struct tegra_clk_emc *tegra)
+{
+        struct platform_device *pdev;
+
+        if (tegra->emc)
+                return tegra->emc;
+
+        if (!tegra->emc_node)
+                return NULL;
+
+        pdev = of_find_device_by_node(tegra->emc_node);
+        if (!pdev) {
+                pr_err("%s: could not get external memory controller\n",
+                       __func__);
+                return NULL;
+        }
+
+        of_node_put(tegra->emc_node);
+        tegra->emc_node = NULL;
+
+        tegra->emc = platform_get_drvdata(pdev);
+        if (!tegra->emc) {
+                pr_err("%s: cannot find EMC driver\n", __func__);
+                return NULL;
+        }
+
+        return tegra->emc;
+}
+
+static int emc_set_timing(struct tegra_clk_emc *tegra,
+                          struct emc_timing *timing)
+{
+        int err;
+        u8 div;
+        u32 car_value;
+        unsigned long flags = 0;
+        struct tegra_emc *emc = emc_ensure_emc_driver(tegra);
+
+        if (!emc)
+                return -ENOENT;
+
+        pr_debug("going to rate %ld prate %ld p %s\n", timing->rate,
+                 timing->parent_rate, __clk_get_name(timing->parent));
+
+        if (emc_get_parent(&tegra->hw) == timing->parent_index &&
+            clk_get_rate(timing->parent) != timing->parent_rate) {
+                BUG();
+                return -EINVAL;
+        }
+
+        tegra->changing_timing = true;
+
+        err = clk_set_rate(timing->parent, timing->parent_rate);
+        if (err) {
+                pr_err("cannot change parent %s rate to %ld: %d\n",
+                       __clk_get_name(timing->parent), timing->parent_rate,
+                       err);
+
+                return err;
+        }
+
+        err = clk_prepare_enable(timing->parent);
+        if (err) {
+                pr_err("cannot enable parent clock: %d\n", err);
+                return err;
+        }
+
+        div = timing->parent_rate / (timing->rate / 2) - 2;
+
+        err = tegra_emc_prepare_timing_change(emc, timing->rate);
+        if (err)
+                return err;
+
+        spin_lock_irqsave(tegra->lock, flags);
+
+        car_value = readl(tegra->clk_regs + CLK_SOURCE_EMC);
+
+        car_value &= ~CLK_SOURCE_EMC_EMC_2X_CLK_SRC(~0);
+        car_value |= CLK_SOURCE_EMC_EMC_2X_CLK_SRC(timing->parent_index);
+
+        car_value &= ~CLK_SOURCE_EMC_EMC_2X_CLK_DIVISOR(~0);
+        car_value |= CLK_SOURCE_EMC_EMC_2X_CLK_DIVISOR(div);
+
+        writel(car_value, tegra->clk_regs + CLK_SOURCE_EMC);
+
+        spin_unlock_irqrestore(tegra->lock, flags);
+
+        tegra_emc_complete_timing_change(emc, timing->rate);
+
+        clk_hw_reparent(&tegra->hw, __clk_get_hw(timing->parent));
+        clk_disable_unprepare(tegra->prev_parent);
+
+        tegra->prev_parent = timing->parent;
+        tegra->changing_timing = false;
+
+        return 0;
+}
+
+/*
+ * Get backup timing to use as an intermediate step when a change between
+ * two timings with the same clock source has been requested. First try to
+ * find a timing with a higher clock rate to avoid a rate below any set rate
+ * floors. If that is not possible, find a lower rate.
+ */
+static struct emc_timing *get_backup_timing(struct tegra_clk_emc *tegra,
+                                            int timing_index)
+{
+        int i;
+        u32 ram_code = tegra_read_ram_code();
+        struct emc_timing *timing;
+
+        for (i = timing_index+1; i < tegra->num_timings; i++) {
+                timing = tegra->timings + i;
+                if (timing->ram_code != ram_code)
+                        continue;
+
+                if (emc_parent_clk_sources[timing->parent_index] !=
+                    emc_parent_clk_sources[
+                      tegra->timings[timing_index].parent_index])
+                        return timing;
+        }
+
+        for (i = timing_index-1; i >= 0; --i) {
+                timing = tegra->timings + i;
+                if (timing->ram_code != ram_code)
+                        continue;
+
+                if (emc_parent_clk_sources[timing->parent_index] !=
+                    emc_parent_clk_sources[
+                      tegra->timings[timing_index].parent_index])
+                        return timing;
+        }
+
+        return NULL;
+}
+
+static int emc_set_rate(struct clk_hw *hw, unsigned long rate,
+                        unsigned long parent_rate)
+{
+        struct tegra_clk_emc *tegra;
+        struct emc_timing *timing = NULL;
+        int i, err;
+        u32 ram_code = tegra_read_ram_code();
+
+        tegra = container_of(hw, struct tegra_clk_emc, hw);
+
+        if (__clk_get_rate(hw->clk) == rate)
+                return 0;
+
+        /*
+         * When emc_set_timing changes the parent rate, CCF will propagate
+         * that downward to us, so ignore any set_rate calls while a rate
+         * change is already going on.
+         */
+        if (tegra->changing_timing)
+                return 0;
+
+        for (i = 0; i < tegra->num_timings; i++) {
+                if (tegra->timings[i].rate == rate &&
+                    tegra->timings[i].ram_code == ram_code) {
+                        timing = tegra->timings + i;
+                        break;
+                }
+        }
+
+        if (!timing) {
+                pr_err("cannot switch to rate %ld without emc table\n", rate);
+                return -EINVAL;
+        }
+
+        if (emc_parent_clk_sources[emc_get_parent(hw)] ==
+            emc_parent_clk_sources[timing->parent_index] &&
+            clk_get_rate(timing->parent) != timing->parent_rate) {
+                /*
+                 * Parent clock source not changed but parent rate has changed,
+                 * need to temporarily switch to another parent
+                 */
+
+                struct emc_timing *backup_timing;
+
+                backup_timing = get_backup_timing(tegra, i);
+                if (!backup_timing) {
+                        pr_err("cannot find backup timing\n");
+                        return -EINVAL;
+                }
+
+                pr_debug("using %ld as backup rate when going to %ld\n",
+                         backup_timing->rate, rate);
+
+                err = emc_set_timing(tegra, backup_timing);
+                if (err) {
+                        pr_err("cannot set backup timing: %d\n", err);
+                        return err;
+                }
+        }
+
+        return emc_set_timing(tegra, timing);
+}
+
+/* Initialization and deinitialization */
+
+static int load_one_timing_from_dt(struct tegra_clk_emc *tegra,
+                                   struct emc_timing *timing,
+                                   struct device_node *node)
+{
+        int err, i;
+        u32 tmp;
+
+        err = of_property_read_u32(node, "clock-frequency", &tmp);
+        if (err) {
+                pr_err("timing %s: failed to read rate\n", node->full_name);
+                return err;
+        }
+
+        timing->rate = tmp;
+
+        err = of_property_read_u32(node, "nvidia,parent-clock-frequency", &tmp);
+        if (err) {
+                pr_err("timing %s: failed to read parent rate\n",
+                       node->full_name);
+                return err;
+        }
+
+        timing->parent_rate = tmp;
+
+        timing->parent = of_clk_get_by_name(node, "emc-parent");
+        if (IS_ERR(timing->parent)) {
+                pr_err("timing %s: failed to get parent clock\n",
+                       node->full_name);
+                return PTR_ERR(timing->parent);
+        }
+
+        timing->parent_index = 0xff;
+        for (i = 0; i < ARRAY_SIZE(emc_parent_clk_names); i++) {
+                if (!strcmp(emc_parent_clk_names[i],
+                            __clk_get_name(timing->parent))) {
+                        timing->parent_index = i;
+                        break;
+                }
+        }
+        if (timing->parent_index == 0xff) {
+                pr_err("timing %s: %s is not a valid parent\n",
+                       node->full_name, __clk_get_name(timing->parent));
+                clk_put(timing->parent);
+                return -EINVAL;
+        }
+
+        return 0;
+}
+
+static int cmp_timings(const void *_a, const void *_b)
+{
+        const struct emc_timing *a = _a;
+        const struct emc_timing *b = _b;
+
+        if (a->rate < b->rate)
+                return -1;
+        else if (a->rate == b->rate)
+                return 0;
+        else
+                return 1;
+}
+
+static int load_timings_from_dt(struct tegra_clk_emc *tegra,
+                                struct device_node *node,
+                                u32 ram_code)
+{
+        struct device_node *child;
+        int child_count = of_get_child_count(node);
+        int i = 0, err;
+
+        tegra->timings = kcalloc(child_count, sizeof(struct emc_timing),
+                                 GFP_KERNEL);
+        if (!tegra->timings)
+                return -ENOMEM;
+
+        tegra->num_timings = child_count;
+
+        for_each_child_of_node(node, child) {
+                struct emc_timing *timing = tegra->timings + (i++);
+
+                err = load_one_timing_from_dt(tegra, timing, child);
+                if (err)
+                        return err;
+
+                timing->ram_code = ram_code;
+        }
+
+        sort(tegra->timings, tegra->num_timings, sizeof(struct emc_timing),
+             cmp_timings, NULL);
+
+        return 0;
+}
+
+static const struct clk_ops tegra_clk_emc_ops = {
+        .recalc_rate = emc_recalc_rate,
+        .determine_rate = emc_determine_rate,
+        .set_rate = emc_set_rate,
+        .get_parent = emc_get_parent,
+};
+
+struct clk *tegra_clk_register_emc(void __iomem *base, struct device_node *np,
+                                   spinlock_t *lock)
+{
+        struct tegra_clk_emc *tegra;
+        struct clk_init_data init;
+        struct device_node *node;
+        u32 node_ram_code;
+        struct clk *clk;
+        int err;
+
+        tegra = kcalloc(1, sizeof(*tegra), GFP_KERNEL);
+        if (!tegra)
+                return ERR_PTR(-ENOMEM);
+
+        tegra->clk_regs = base;
+        tegra->lock = lock;
+
+        tegra->num_timings = 0;
+
+        for_each_child_of_node(np, node) {
+                err = of_property_read_u32(node, "nvidia,ram-code",
+                                           &node_ram_code);
+                if (err) {
+                        of_node_put(node);
+                        continue;
+                }
+
+                /*
+                 * Store timings for all ram codes as we cannot read the
+                 * fuses until the apbmisc driver is loaded.
+                 */
+                err = load_timings_from_dt(tegra, node, node_ram_code);
+                if (err)
+                        return ERR_PTR(err);
+                of_node_put(node);
+                break;
+        }
+
+        if (tegra->num_timings == 0)
+                pr_warn("%s: no memory timings registered\n", __func__);
+
+        tegra->emc_node = of_parse_phandle(np,
+                        "nvidia,external-memory-controller", 0);
+        if (!tegra->emc_node)
+                pr_warn("%s: couldn't find node for EMC driver\n", __func__);
+
+        init.name = "emc";
+        init.ops = &tegra_clk_emc_ops;
+        init.flags = 0;
+        init.parent_names = emc_parent_clk_names;
+        init.num_parents = ARRAY_SIZE(emc_parent_clk_names);
+
+        tegra->hw.init = &init;
+
+        clk = clk_register(NULL, &tegra->hw);
+        if (IS_ERR(clk))
+                return clk;
+
+        tegra->prev_parent = clk_get_parent_by_index(
+                tegra->hw.clk, emc_get_parent(&tegra->hw));
+        tegra->changing_timing = false;
+
+        /* Allow debugging tools to see the EMC clock */
+        clk_register_clkdev(clk, "emc", "tegra-clk-debug");
+
+        clk_prepare_enable(clk);
+
+        return clk;
+};
diff --git a/drivers/clk/tegra/clk-tegra124.c b/drivers/clk/tegra/clk-tegra124.c
index 11f857cd5f6a..e8cca3eac007 100644
--- a/drivers/clk/tegra/clk-tegra124.c
+++ b/drivers/clk/tegra/clk-tegra124.c
@@ -152,11 +152,6 @@ static unsigned long tegra124_input_freq[] = {
         [12] = 260000000,
 };
 
-static const char *mux_pllmcp_clkm[] = {
-        "pll_m", "pll_c", "pll_p", "clk_m", "pll_m_ud", "pll_c2", "pll_c3",
-};
-#define mux_pllmcp_clkm_idx NULL
-
 static struct div_nmp pllxc_nmp = {
         .divm_shift = 0,
         .divm_width = 8,
@@ -791,7 +786,6 @@ static struct tegra_clk tegra124_clks[tegra_clk_max] __initdata = {
         [tegra_clk_i2c2] = { .dt_id = TEGRA124_CLK_I2C2, .present = true },
         [tegra_clk_uartc] = { .dt_id = TEGRA124_CLK_UARTC, .present = true },
         [tegra_clk_mipi_cal] = { .dt_id = TEGRA124_CLK_MIPI_CAL, .present = true },
-        [tegra_clk_emc] = { .dt_id = TEGRA124_CLK_EMC, .present = true },
         [tegra_clk_usb2] = { .dt_id = TEGRA124_CLK_USB2, .present = true },
         [tegra_clk_usb3] = { .dt_id = TEGRA124_CLK_USB3, .present = true },
         [tegra_clk_vde_8] = { .dt_id = TEGRA124_CLK_VDE, .present = true },
@@ -1127,13 +1121,7 @@ static __init void tegra124_periph_clk_init(void __iomem *clk_base,
                                              periph_clk_enb_refcnt);
         clks[TEGRA124_CLK_DSIB] = clk;
 
-        /* emc mux */
-        clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm,
-                               ARRAY_SIZE(mux_pllmcp_clkm), 0,
-                               clk_base + CLK_SOURCE_EMC,
-                               29, 3, 0, &emc_lock);
-
-        clk = tegra_clk_register_mc("mc", "emc_mux", clk_base + CLK_SOURCE_EMC,
+        clk = tegra_clk_register_mc("mc", "emc", clk_base + CLK_SOURCE_EMC,
                                     &emc_lock);
         clks[TEGRA124_CLK_MC] = clk;
 
@@ -1389,7 +1377,6 @@ static struct tegra_clk_init_table common_init_table[] __initdata = {
         {TEGRA124_CLK_XUSB_HOST_SRC, TEGRA124_CLK_PLL_RE_OUT, 112000000, 0},
         {TEGRA124_CLK_SATA, TEGRA124_CLK_PLL_P, 104000000, 0},
         {TEGRA124_CLK_SATA_OOB, TEGRA124_CLK_PLL_P, 204000000, 0},
-        {TEGRA124_CLK_EMC, TEGRA124_CLK_CLK_MAX, 0, 1},
         {TEGRA124_CLK_MSELECT, TEGRA124_CLK_CLK_MAX, 0, 1},
         {TEGRA124_CLK_CSITE, TEGRA124_CLK_CLK_MAX, 0, 1},
         {TEGRA124_CLK_TSENSOR, TEGRA124_CLK_CLK_M, 400000, 0},
@@ -1513,6 +1500,10 @@ static void __init tegra124_132_clock_init_post(struct device_node *np)
         tegra_super_clk_gen4_init(clk_base, pmc_base, tegra124_clks,
                                   &pll_x_params);
         tegra_add_of_provider(np);
+
+        clks[TEGRA124_CLK_EMC] = tegra_clk_register_emc(clk_base, np,
+                                                        &emc_lock);
+
         tegra_register_devclks(devclks, ARRAY_SIZE(devclks));
 
         tegra_cpu_car_ops = &tegra124_cpu_car_ops;
diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c
index 4b26509fc218..0af3e834dd24 100644
--- a/drivers/clk/tegra/clk-tegra30.c
+++ b/drivers/clk/tegra/clk-tegra30.c
@@ -679,7 +679,7 @@ static struct tegra_devclk devclks[] __initdata = {
         { .dev_id = "tegra30-dam.1", .dt_id = TEGRA30_CLK_DAM1 },
         { .dev_id = "tegra30-dam.2", .dt_id = TEGRA30_CLK_DAM2 },
         { .con_id = "hda", .dev_id = "tegra30-hda", .dt_id = TEGRA30_CLK_HDA },
-        { .con_id = "hda2codec", .dev_id = "tegra30-hda", .dt_id = TEGRA30_CLK_HDA2CODEC_2X },
+        { .con_id = "hda2codec_2x", .dev_id = "tegra30-hda", .dt_id = TEGRA30_CLK_HDA2CODEC_2X },
         { .dev_id = "spi_tegra.0", .dt_id = TEGRA30_CLK_SBC1 },
         { .dev_id = "spi_tegra.1", .dt_id = TEGRA30_CLK_SBC2 },
         { .dev_id = "spi_tegra.2", .dt_id = TEGRA30_CLK_SBC3 },
diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h
index d6ac00647faf..75ddc8ff8bd4 100644
--- a/drivers/clk/tegra/clk.h
+++ b/drivers/clk/tegra/clk.h
@@ -623,6 +623,18 @@ void tegra_super_clk_gen4_init(void __iomem *clk_base,
                         void __iomem *pmc_base, struct tegra_clk *tegra_clks,
                         struct tegra_clk_pll_params *pll_params);
 
+#ifdef CONFIG_TEGRA_CLK_EMC
+struct clk *tegra_clk_register_emc(void __iomem *base, struct device_node *np,
+                                   spinlock_t *lock);
+#else
+static inline struct clk *tegra_clk_register_emc(void __iomem *base,
+                                                 struct device_node *np,
+                                                 spinlock_t *lock)
+{
+        return NULL;
+}
+#endif
+
 void tegra114_clock_tune_cpu_trimmers_high(void);
 void tegra114_clock_tune_cpu_trimmers_low(void);
 void tegra114_clock_tune_cpu_trimmers_init(void);
diff --git a/drivers/soc/tegra/fuse/tegra-apbmisc.c b/drivers/soc/tegra/fuse/tegra-apbmisc.c
index 3bf5aba4caaa..73fad05d8f2c 100644
--- a/drivers/soc/tegra/fuse/tegra-apbmisc.c
+++ b/drivers/soc/tegra/fuse/tegra-apbmisc.c
@@ -28,8 +28,15 @@
 #define APBMISC_SIZE    0x64
 #define FUSE_SKU_INFO   0x10
 
+#define PMC_STRAPPING_OPT_A_RAM_CODE_SHIFT      4
+#define PMC_STRAPPING_OPT_A_RAM_CODE_MASK_LONG  \
+        (0xf << PMC_STRAPPING_OPT_A_RAM_CODE_SHIFT)
+#define PMC_STRAPPING_OPT_A_RAM_CODE_MASK_SHORT \
+        (0x3 << PMC_STRAPPING_OPT_A_RAM_CODE_SHIFT)
+
 static void __iomem *apbmisc_base;
 static void __iomem *strapping_base;
+static bool long_ram_code;
 
 u32 tegra_read_chipid(void)
 {
@@ -54,6 +61,18 @@ u32 tegra_read_straps(void)
                 return 0;
 }
 
+u32 tegra_read_ram_code(void)
+{
+        u32 straps = tegra_read_straps();
+
+        if (long_ram_code)
+                straps &= PMC_STRAPPING_OPT_A_RAM_CODE_MASK_LONG;
+        else
+                straps &= PMC_STRAPPING_OPT_A_RAM_CODE_MASK_SHORT;
+
+        return straps >> PMC_STRAPPING_OPT_A_RAM_CODE_SHIFT;
+}
+
 static const struct of_device_id apbmisc_match[] __initconst = {
         { .compatible = "nvidia,tegra20-apbmisc", },
         {},
@@ -112,4 +131,6 @@ void __init tegra_init_apbmisc(void)
         strapping_base = of_iomap(np, 1);
         if (!strapping_base)
                 pr_err("ioremap tegra strapping_base failed\n");
+
+        long_ram_code = of_property_read_bool(np, "nvidia,long-ram-code");
 }
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index 6a24df64b0a0..78842f46f152 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -592,6 +592,7 @@ long __clk_mux_determine_rate_closest(struct clk_hw *hw, unsigned long rate,
                               unsigned long max_rate,
                               unsigned long *best_parent_rate,
                               struct clk_hw **best_parent_p);
+void clk_hw_reparent(struct clk_hw *hw, struct clk_hw *new_parent);
 
 static inline void __clk_hw_set_clk(struct clk_hw *dst, struct clk_hw *src)
 {
diff --git a/include/soc/tegra/fuse.h b/include/soc/tegra/fuse.h
index b5f7b5f8d008..b019e3465f11 100644
--- a/include/soc/tegra/fuse.h
+++ b/include/soc/tegra/fuse.h
@@ -56,6 +56,7 @@ struct tegra_sku_info {
 };
 
 u32 tegra_read_straps(void);
+u32 tegra_read_ram_code(void);
 u32 tegra_read_chipid(void);
 int tegra_fuse_readl(unsigned long offset, u32 *value);