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authorLe Ma <le.ma@amd.com>2019-07-09 10:18:03 -0400
committerAlex Deucher <alexander.deucher@amd.com>2019-07-18 15:18:02 -0400
commit2cb2ea1e073fb8d8c1850383b70b78e69ef8b3cc (patch)
tree4b5cde7c200b1c5e773444c283b5026468e0f9ba
parentc8a6e2a3170064c1f476407139c3dd97d9a9087c (diff)
drm/amdgpu: add mmhub v9.4.1 block for Arcturus (v2)
Arcturus as an updated mmhub block. mmhub is the memory controller hub used for sdma and multimedia. v2: squash in AGP BAR programming (Alex) Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat
-rw-r--r--drivers/gpu/drm/amd/amdgpu/Makefile2
-rw-r--r--drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c504
-rw-r--r--drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.h33
3 files changed, 538 insertions, 1 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile
index 3f5329906fce..7b6fb0e9ee76 100644
--- a/drivers/gpu/drm/amd/amdgpu/Makefile
+++ b/drivers/gpu/drm/amd/amdgpu/Makefile
@@ -77,7 +77,7 @@ amdgpu-y += \
77amdgpu-y += \ 77amdgpu-y += \
78 gmc_v7_0.o \ 78 gmc_v7_0.o \
79 gmc_v8_0.o \ 79 gmc_v8_0.o \
80 gfxhub_v1_0.o mmhub_v1_0.o gmc_v9_0.o gfxhub_v1_1.o \ 80 gfxhub_v1_0.o mmhub_v1_0.o gmc_v9_0.o gfxhub_v1_1.o mmhub_v9_4.o \
81 gfxhub_v2_0.o mmhub_v2_0.o gmc_v10_0.o 81 gfxhub_v2_0.o mmhub_v2_0.o gmc_v10_0.o
82 82
83# add IH block 83# add IH block
diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c
new file mode 100644
index 000000000000..aa9b43b6ba6b
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c
@@ -0,0 +1,504 @@
1/*
2 * Copyright 2018 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#include "amdgpu.h"
24#include "mmhub_v9_4.h"
25
26#include "mmhub/mmhub_9_4_1_offset.h"
27#include "mmhub/mmhub_9_4_1_sh_mask.h"
28#include "mmhub/mmhub_9_4_1_default.h"
29#include "athub/athub_1_0_offset.h"
30#include "athub/athub_1_0_sh_mask.h"
31#include "vega10_enum.h"
32
33#include "soc15_common.h"
34
35#define MMHUB_NUM_INSTANCES 2
36#define MMHUB_INSTANCE_REGISTER_OFFSET 0x3000
37
38u64 mmhub_v9_4_get_fb_location(struct amdgpu_device *adev)
39{
40 /* The base should be same b/t 2 mmhubs on Acrturus. Read one here. */
41 u64 base = RREG32_SOC15(MMHUB, 0, mmVMSHAREDVC0_MC_VM_FB_LOCATION_BASE);
42
43 base &= VMSHAREDVC0_MC_VM_FB_LOCATION_BASE__FB_BASE_MASK;
44 base <<= 24;
45
46 return base;
47}
48
49static void mmhub_v9_4_init_gart_pt_regs(struct amdgpu_device *adev, int hubid)
50{
51 uint64_t value = amdgpu_gmc_pd_addr(adev->gart.bo);
52
53 WREG32_SOC15_OFFSET(MMHUB, 0,
54 mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
55 hubid * MMHUB_INSTANCE_REGISTER_OFFSET,
56 lower_32_bits(value));
57
58 WREG32_SOC15_OFFSET(MMHUB, 0,
59 mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,
60 hubid * MMHUB_INSTANCE_REGISTER_OFFSET,
61 upper_32_bits(value));
62
63}
64
65static void mmhub_v9_4_init_gart_aperture_regs(struct amdgpu_device *adev,
66 int hubid)
67{
68 mmhub_v9_4_init_gart_pt_regs(adev, hubid);
69
70 WREG32_SOC15_OFFSET(MMHUB, 0,
71 mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
72 hubid * MMHUB_INSTANCE_REGISTER_OFFSET,
73 (u32)(adev->gmc.gart_start >> 12));
74 WREG32_SOC15_OFFSET(MMHUB, 0,
75 mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,
76 hubid * MMHUB_INSTANCE_REGISTER_OFFSET,
77 (u32)(adev->gmc.gart_start >> 44));
78
79 WREG32_SOC15_OFFSET(MMHUB, 0,
80 mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,
81 hubid * MMHUB_INSTANCE_REGISTER_OFFSET,
82 (u32)(adev->gmc.gart_end >> 12));
83 WREG32_SOC15_OFFSET(MMHUB, 0,
84 mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,
85 hubid * MMHUB_INSTANCE_REGISTER_OFFSET,
86 (u32)(adev->gmc.gart_end >> 44));
87}
88
89static void mmhub_v9_4_init_system_aperture_regs(struct amdgpu_device *adev,
90 int hubid)
91{
92 uint64_t value;
93 uint32_t tmp;
94
95 /* Program the AGP BAR */
96 WREG32_SOC15_OFFSET(MMHUB, 0, mmVMSHAREDVC0_MC_VM_AGP_BASE,
97 hubid * MMHUB_INSTANCE_REGISTER_OFFSET,
98 0);
99 WREG32_SOC15_OFFSET(MMHUB, 0, mmVMSHAREDVC0_MC_VM_AGP_TOP,
100 hubid * MMHUB_INSTANCE_REGISTER_OFFSET,
101 adev->gmc.agp_end >> 24);
102 WREG32_SOC15_OFFSET(MMHUB, 0, mmVMSHAREDVC0_MC_VM_AGP_BOT,
103 hubid * MMHUB_INSTANCE_REGISTER_OFFSET,
104 adev->gmc.agp_start >> 24);
105
106 /* Program the system aperture low logical page number. */
107 WREG32_SOC15_OFFSET(MMHUB, 0,
108 mmVMSHAREDVC0_MC_VM_SYSTEM_APERTURE_LOW_ADDR,
109 hubid * MMHUB_INSTANCE_REGISTER_OFFSET,
110 min(adev->gmc.vram_start, adev->gmc.agp_start)
111 >> 18);
112 WREG32_SOC15_OFFSET(MMHUB, 0,
113 mmVMSHAREDVC0_MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
114 hubid * MMHUB_INSTANCE_REGISTER_OFFSET,
115 max(adev->gmc.vram_end, adev->gmc.agp_end) >> 18);
116
117 /* Set default page address. */
118 value = adev->vram_scratch.gpu_addr - adev->gmc.vram_start +
119 adev->vm_manager.vram_base_offset;
120 WREG32_SOC15_OFFSET(MMHUB, 0,
121 mmVMSHAREDPF0_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
122 hubid * MMHUB_INSTANCE_REGISTER_OFFSET,
123 (u32)(value >> 12));
124 WREG32_SOC15_OFFSET(MMHUB, 0,
125 mmVMSHAREDPF0_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,
126 hubid * MMHUB_INSTANCE_REGISTER_OFFSET,
127 (u32)(value >> 44));
128
129 /* Program "protection fault". */
130 WREG32_SOC15_OFFSET(MMHUB, 0,
131 mmVML2PF0_VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32,
132 hubid * MMHUB_INSTANCE_REGISTER_OFFSET,
133 (u32)(adev->dummy_page_addr >> 12));
134 WREG32_SOC15_OFFSET(MMHUB, 0,
135 mmVML2PF0_VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32,
136 hubid * MMHUB_INSTANCE_REGISTER_OFFSET,
137 (u32)((u64)adev->dummy_page_addr >> 44));
138
139 tmp = RREG32_SOC15_OFFSET(MMHUB, 0,
140 mmVML2PF0_VM_L2_PROTECTION_FAULT_CNTL2,
141 hubid * MMHUB_INSTANCE_REGISTER_OFFSET);
142 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL2,
143 ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1);
144 WREG32_SOC15_OFFSET(MMHUB, 0, mmVML2PF0_VM_L2_PROTECTION_FAULT_CNTL2,
145 hubid * MMHUB_INSTANCE_REGISTER_OFFSET, tmp);
146}
147
148static void mmhub_v9_4_init_tlb_regs(struct amdgpu_device *adev, int hubid)
149{
150 uint32_t tmp;
151
152 /* Setup TLB control */
153 tmp = RREG32_SOC15_OFFSET(MMHUB, 0,
154 mmVMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL,
155 hubid * MMHUB_INSTANCE_REGISTER_OFFSET);
156
157 tmp = REG_SET_FIELD(tmp, VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL,
158 ENABLE_L1_TLB, 1);
159 tmp = REG_SET_FIELD(tmp, VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL,
160 SYSTEM_ACCESS_MODE, 3);
161 tmp = REG_SET_FIELD(tmp, VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL,
162 ENABLE_ADVANCED_DRIVER_MODEL, 1);
163 tmp = REG_SET_FIELD(tmp, VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL,
164 SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
165 tmp = REG_SET_FIELD(tmp, VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL,
166 ECO_BITS, 0);
167 tmp = REG_SET_FIELD(tmp, VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL,
168 MTYPE, MTYPE_UC);/* XXX for emulation. */
169 tmp = REG_SET_FIELD(tmp, VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL,
170 ATC_EN, 1);
171
172 WREG32_SOC15_OFFSET(MMHUB, 0, mmVMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL,
173 hubid * MMHUB_INSTANCE_REGISTER_OFFSET, tmp);
174}
175
176static void mmhub_v9_4_init_cache_regs(struct amdgpu_device *adev, int hubid)
177{
178 uint32_t tmp;
179
180 /* Setup L2 cache */
181 tmp = RREG32_SOC15_OFFSET(MMHUB, 0, mmVML2PF0_VM_L2_CNTL,
182 hubid * MMHUB_INSTANCE_REGISTER_OFFSET);
183 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL,
184 ENABLE_L2_CACHE, 1);
185 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL,
186 ENABLE_L2_FRAGMENT_PROCESSING, 1);
187 /* XXX for emulation, Refer to closed source code.*/
188 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL,
189 L2_PDE0_CACHE_TAG_GENERATION_MODE, 0);
190 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL,
191 PDE_FAULT_CLASSIFICATION, 1);
192 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL,
193 CONTEXT1_IDENTITY_ACCESS_MODE, 1);
194 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL,
195 IDENTITY_MODE_FRAGMENT_SIZE, 0);
196 WREG32_SOC15_OFFSET(MMHUB, 0, mmVML2PF0_VM_L2_CNTL,
197 hubid * MMHUB_INSTANCE_REGISTER_OFFSET, tmp);
198
199 tmp = RREG32_SOC15_OFFSET(MMHUB, 0, mmVML2PF0_VM_L2_CNTL2,
200 hubid * MMHUB_INSTANCE_REGISTER_OFFSET);
201 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL2,
202 INVALIDATE_ALL_L1_TLBS, 1);
203 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL2,
204 INVALIDATE_L2_CACHE, 1);
205 WREG32_SOC15_OFFSET(MMHUB, 0, mmVML2PF0_VM_L2_CNTL2,
206 hubid * MMHUB_INSTANCE_REGISTER_OFFSET, tmp);
207
208 tmp = mmVML2PF0_VM_L2_CNTL3_DEFAULT;
209 WREG32_SOC15_OFFSET(MMHUB, 0, mmVML2PF0_VM_L2_CNTL3,
210 hubid * MMHUB_INSTANCE_REGISTER_OFFSET, tmp);
211
212 tmp = mmVML2PF0_VM_L2_CNTL4_DEFAULT;
213 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL4,
214 VMC_TAP_PDE_REQUEST_PHYSICAL, 0);
215 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL4,
216 VMC_TAP_PTE_REQUEST_PHYSICAL, 0);
217 WREG32_SOC15_OFFSET(MMHUB, 0, mmVML2PF0_VM_L2_CNTL4,
218 hubid * MMHUB_INSTANCE_REGISTER_OFFSET, tmp);
219}
220
221static void mmhub_v9_4_enable_system_domain(struct amdgpu_device *adev,
222 int hubid)
223{
224 uint32_t tmp;
225
226 tmp = RREG32_SOC15_OFFSET(MMHUB, 0, mmVML2VC0_VM_CONTEXT0_CNTL,
227 hubid * MMHUB_INSTANCE_REGISTER_OFFSET);
228 tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
229 tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
230 WREG32_SOC15_OFFSET(MMHUB, 0, mmVML2VC0_VM_CONTEXT0_CNTL,
231 hubid * MMHUB_INSTANCE_REGISTER_OFFSET, tmp);
232}
233
234static void mmhub_v9_4_disable_identity_aperture(struct amdgpu_device *adev,
235 int hubid)
236{
237 WREG32_SOC15_OFFSET(MMHUB, 0,
238 mmVML2PF0_VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32,
239 hubid * MMHUB_INSTANCE_REGISTER_OFFSET, 0XFFFFFFFF);
240 WREG32_SOC15_OFFSET(MMHUB, 0,
241 mmVML2PF0_VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32,
242 hubid * MMHUB_INSTANCE_REGISTER_OFFSET, 0x0000000F);
243
244 WREG32_SOC15_OFFSET(MMHUB, 0,
245 mmVML2PF0_VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32,
246 hubid * MMHUB_INSTANCE_REGISTER_OFFSET, 0);
247 WREG32_SOC15_OFFSET(MMHUB, 0,
248 mmVML2PF0_VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32,
249 hubid * MMHUB_INSTANCE_REGISTER_OFFSET, 0);
250
251 WREG32_SOC15_OFFSET(MMHUB, 0,
252 mmVML2PF0_VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32,
253 hubid * MMHUB_INSTANCE_REGISTER_OFFSET, 0);
254 WREG32_SOC15_OFFSET(MMHUB, 0,
255 mmVML2PF0_VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32,
256 hubid * MMHUB_INSTANCE_REGISTER_OFFSET, 0);
257}
258
259static void mmhub_v9_4_setup_vmid_config(struct amdgpu_device *adev, int hubid)
260{
261 uint32_t tmp;
262 int i;
263
264 for (i = 0; i <= 14; i++) {
265 tmp = RREG32_SOC15_OFFSET(MMHUB, 0, mmVML2VC0_VM_CONTEXT1_CNTL,
266 hubid * MMHUB_INSTANCE_REGISTER_OFFSET + i);
267 tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL,
268 ENABLE_CONTEXT, 1);
269 tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL,
270 PAGE_TABLE_DEPTH,
271 adev->vm_manager.num_level);
272 tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL,
273 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
274 tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL,
275 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT,
276 1);
277 tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL,
278 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
279 tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL,
280 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
281 tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL,
282 READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
283 tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL,
284 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
285 tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL,
286 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
287 tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL,
288 PAGE_TABLE_BLOCK_SIZE,
289 adev->vm_manager.block_size - 9);
290 /* Send no-retry XNACK on fault to suppress VM fault storm. */
291 tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL,
292 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0);
293 WREG32_SOC15_OFFSET(MMHUB, 0, mmVML2VC0_VM_CONTEXT1_CNTL,
294 hubid * MMHUB_INSTANCE_REGISTER_OFFSET + i,
295 tmp);
296 WREG32_SOC15_OFFSET(MMHUB, 0,
297 mmVML2VC0_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32,
298 hubid * MMHUB_INSTANCE_REGISTER_OFFSET + i*2, 0);
299 WREG32_SOC15_OFFSET(MMHUB, 0,
300 mmVML2VC0_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32,
301 hubid * MMHUB_INSTANCE_REGISTER_OFFSET + i*2, 0);
302 WREG32_SOC15_OFFSET(MMHUB, 0,
303 mmVML2VC0_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32,
304 hubid * MMHUB_INSTANCE_REGISTER_OFFSET + i*2,
305 lower_32_bits(adev->vm_manager.max_pfn - 1));
306 WREG32_SOC15_OFFSET(MMHUB, 0,
307 mmVML2VC0_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32,
308 hubid * MMHUB_INSTANCE_REGISTER_OFFSET + i*2,
309 upper_32_bits(adev->vm_manager.max_pfn - 1));
310 }
311}
312
313static void mmhub_v9_4_program_invalidation(struct amdgpu_device *adev,
314 int hubid)
315{
316 unsigned i;
317
318 for (i = 0; i < 18; ++i) {
319 WREG32_SOC15_OFFSET(MMHUB, 0,
320 mmVML2VC0_VM_INVALIDATE_ENG0_ADDR_RANGE_LO32,
321 hubid * MMHUB_INSTANCE_REGISTER_OFFSET + 2 * i,
322 0xffffffff);
323 WREG32_SOC15_OFFSET(MMHUB, 0,
324 mmVML2VC0_VM_INVALIDATE_ENG0_ADDR_RANGE_HI32,
325 hubid * MMHUB_INSTANCE_REGISTER_OFFSET + 2 * i,
326 0x1f);
327 }
328}
329
330int mmhub_v9_4_gart_enable(struct amdgpu_device *adev)
331{
332 int i;
333
334 for (i = 0; i < MMHUB_NUM_INSTANCES; i++) {
335 if (amdgpu_sriov_vf(adev)) {
336 /*
337 * MC_VM_FB_LOCATION_BASE/TOP is NULL for VF, becuase
338 * they are VF copy registers so vbios post doesn't
339 * program them, for SRIOV driver need to program them
340 */
341 WREG32_SOC15_OFFSET(MMHUB, 0,
342 mmVMSHAREDVC0_MC_VM_FB_LOCATION_BASE,
343 i * MMHUB_INSTANCE_REGISTER_OFFSET,
344 adev->gmc.vram_start >> 24);
345 WREG32_SOC15_OFFSET(MMHUB, 0,
346 mmVMSHAREDVC0_MC_VM_FB_LOCATION_TOP,
347 i * MMHUB_INSTANCE_REGISTER_OFFSET,
348 adev->gmc.vram_end >> 24);
349 }
350
351 /* GART Enable. */
352 mmhub_v9_4_init_gart_aperture_regs(adev, i);
353 mmhub_v9_4_init_system_aperture_regs(adev, i);
354 mmhub_v9_4_init_tlb_regs(adev, i);
355 mmhub_v9_4_init_cache_regs(adev, i);
356
357 mmhub_v9_4_enable_system_domain(adev, i);
358 mmhub_v9_4_disable_identity_aperture(adev, i);
359 mmhub_v9_4_setup_vmid_config(adev, i);
360 mmhub_v9_4_program_invalidation(adev, i);
361 }
362
363 return 0;
364}
365
366void mmhub_v9_4_gart_disable(struct amdgpu_device *adev)
367{
368 u32 tmp;
369 u32 i, j;
370
371 for (j = 0; j < MMHUB_NUM_INSTANCES; j++) {
372 /* Disable all tables */
373 for (i = 0; i < 16; i++)
374 WREG32_SOC15_OFFSET(MMHUB, 0,
375 mmVML2VC0_VM_CONTEXT0_CNTL,
376 j * MMHUB_INSTANCE_REGISTER_OFFSET +
377 i, 0);
378
379 /* Setup TLB control */
380 tmp = RREG32_SOC15_OFFSET(MMHUB, 0,
381 mmVMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL,
382 j * MMHUB_INSTANCE_REGISTER_OFFSET);
383 tmp = REG_SET_FIELD(tmp, VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL,
384 ENABLE_L1_TLB, 0);
385 tmp = REG_SET_FIELD(tmp,
386 VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL,
387 ENABLE_ADVANCED_DRIVER_MODEL, 0);
388 WREG32_SOC15_OFFSET(MMHUB, 0,
389 mmVMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL,
390 j * MMHUB_INSTANCE_REGISTER_OFFSET, tmp);
391
392 /* Setup L2 cache */
393 tmp = RREG32_SOC15_OFFSET(MMHUB, 0, mmVML2PF0_VM_L2_CNTL,
394 j * MMHUB_INSTANCE_REGISTER_OFFSET);
395 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL,
396 ENABLE_L2_CACHE, 0);
397 WREG32_SOC15_OFFSET(MMHUB, 0, mmVML2PF0_VM_L2_CNTL,
398 j * MMHUB_INSTANCE_REGISTER_OFFSET, tmp);
399 WREG32_SOC15_OFFSET(MMHUB, 0, mmVML2PF0_VM_L2_CNTL3,
400 j * MMHUB_INSTANCE_REGISTER_OFFSET, 0);
401 }
402}
403
404/**
405 * mmhub_v1_0_set_fault_enable_default - update GART/VM fault handling
406 *
407 * @adev: amdgpu_device pointer
408 * @value: true redirects VM faults to the default page
409 */
410void mmhub_v9_4_set_fault_enable_default(struct amdgpu_device *adev, bool value)
411{
412 u32 tmp;
413 int i;
414
415 for (i = 0; i < MMHUB_NUM_INSTANCES; i++) {
416 tmp = RREG32_SOC15_OFFSET(MMHUB, 0,
417 mmVML2PF0_VM_L2_PROTECTION_FAULT_CNTL,
418 i * MMHUB_INSTANCE_REGISTER_OFFSET);
419 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL,
420 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT,
421 value);
422 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL,
423 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT,
424 value);
425 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL,
426 PDE1_PROTECTION_FAULT_ENABLE_DEFAULT,
427 value);
428 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL,
429 PDE2_PROTECTION_FAULT_ENABLE_DEFAULT,
430 value);
431 tmp = REG_SET_FIELD(tmp,
432 VML2PF0_VM_L2_PROTECTION_FAULT_CNTL,
433 TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT,
434 value);
435 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL,
436 NACK_PROTECTION_FAULT_ENABLE_DEFAULT,
437 value);
438 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL,
439 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT,
440 value);
441 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL,
442 VALID_PROTECTION_FAULT_ENABLE_DEFAULT,
443 value);
444 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL,
445 READ_PROTECTION_FAULT_ENABLE_DEFAULT,
446 value);
447 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL,
448 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT,
449 value);
450 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL,
451 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT,
452 value);
453 if (!value) {
454 tmp = REG_SET_FIELD(tmp,
455 VML2PF0_VM_L2_PROTECTION_FAULT_CNTL,
456 CRASH_ON_NO_RETRY_FAULT, 1);
457 tmp = REG_SET_FIELD(tmp,
458 VML2PF0_VM_L2_PROTECTION_FAULT_CNTL,
459 CRASH_ON_RETRY_FAULT, 1);
460 }
461
462 WREG32_SOC15_OFFSET(MMHUB, 0,
463 mmVML2PF0_VM_L2_PROTECTION_FAULT_CNTL,
464 i * MMHUB_INSTANCE_REGISTER_OFFSET, tmp);
465 }
466}
467
468void mmhub_v9_4_init(struct amdgpu_device *adev)
469{
470 struct amdgpu_vmhub *hub[MMHUB_NUM_INSTANCES] =
471 {&adev->vmhub[AMDGPU_MMHUB_0], &adev->vmhub[AMDGPU_MMHUB_1]};
472 int i;
473
474 for (i = 0; i < MMHUB_NUM_INSTANCES; i++) {
475 hub[i]->ctx0_ptb_addr_lo32 =
476 SOC15_REG_OFFSET(MMHUB, 0,
477 mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32) +
478 i * MMHUB_INSTANCE_REGISTER_OFFSET;
479 hub[i]->ctx0_ptb_addr_hi32 =
480 SOC15_REG_OFFSET(MMHUB, 0,
481 mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32) +
482 i * MMHUB_INSTANCE_REGISTER_OFFSET;
483 hub[i]->vm_inv_eng0_req =
484 SOC15_REG_OFFSET(MMHUB, 0,
485 mmVML2VC0_VM_INVALIDATE_ENG0_REQ) +
486 i * MMHUB_INSTANCE_REGISTER_OFFSET;
487 hub[i]->vm_inv_eng0_ack =
488 SOC15_REG_OFFSET(MMHUB, 0,
489 mmVML2VC0_VM_INVALIDATE_ENG0_ACK) +
490 i * MMHUB_INSTANCE_REGISTER_OFFSET;
491 hub[i]->vm_context0_cntl =
492 SOC15_REG_OFFSET(MMHUB, 0,
493 mmVML2VC0_VM_CONTEXT0_CNTL) +
494 i * MMHUB_INSTANCE_REGISTER_OFFSET;
495 hub[i]->vm_l2_pro_fault_status =
496 SOC15_REG_OFFSET(MMHUB, 0,
497 mmVML2PF0_VM_L2_PROTECTION_FAULT_STATUS) +
498 i * MMHUB_INSTANCE_REGISTER_OFFSET;
499 hub[i]->vm_l2_pro_fault_cntl =
500 SOC15_REG_OFFSET(MMHUB, 0,
501 mmVML2PF0_VM_L2_PROTECTION_FAULT_CNTL) +
502 i * MMHUB_INSTANCE_REGISTER_OFFSET;
503 }
504}
diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.h b/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.h
new file mode 100644
index 000000000000..9ba3dd808826
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.h
@@ -0,0 +1,33 @@
1/*
2 * Copyright 2018 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#ifndef __MMHUB_V9_4_H__
24#define __MMHUB_V9_4_H__
25
26u64 mmhub_v9_4_get_fb_location(struct amdgpu_device *adev);
27int mmhub_v9_4_gart_enable(struct amdgpu_device *adev);
28void mmhub_v9_4_gart_disable(struct amdgpu_device *adev);
29void mmhub_v9_4_set_fault_enable_default(struct amdgpu_device *adev,
30 bool value);
31void mmhub_v9_4_init(struct amdgpu_device *adev);
32
33#endif
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-12 13:48:53 -0400