diff options
author | Damien Lespiau <damien.lespiau@intel.com> | 2015-02-09 14:33:20 -0500 |
---|---|---|
committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2015-02-13 17:28:36 -0500 |
commit | 2caa3b260aa6a3d015352c07d1bce1461825fa6c (patch) | |
tree | 4148e39ea28bf1b9cec9fd721741cfc5feca216d | |
parent | 81e231afe7478f1bf14bbb17c26d6ebf054faece (diff) |
drm/i915/skl: Implement WaDisableChickenBitTSGBarrierAckForFFSliceCS
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Reviewed-by: Nick Hoath <nicholas.hoath@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
-rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 3 | ||||
-rw-r--r-- | drivers/gpu/drm/i915/intel_pm.c | 7 |
2 files changed, 9 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 75227009d0bb..ecc14f558744 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h | |||
@@ -5236,6 +5236,9 @@ enum skl_disp_power_wells { | |||
5236 | #define HSW_NDE_RSTWRN_OPT 0x46408 | 5236 | #define HSW_NDE_RSTWRN_OPT 0x46408 |
5237 | #define RESET_PCH_HANDSHAKE_ENABLE (1<<4) | 5237 | #define RESET_PCH_HANDSHAKE_ENABLE (1<<4) |
5238 | 5238 | ||
5239 | #define FF_SLICE_CS_CHICKEN2 0x02e4 | ||
5240 | #define GEN9_TSG_BARRIER_ACK_DISABLE (1<<8) | ||
5241 | |||
5239 | /* GEN7 chicken */ | 5242 | /* GEN7 chicken */ |
5240 | #define GEN7_COMMON_SLICE_CHICKEN1 0x7010 | 5243 | #define GEN7_COMMON_SLICE_CHICKEN1 0x7010 |
5241 | # define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC ((1<<10) | (1<<26)) | 5244 | # define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC ((1<<10) | (1<<26)) |
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index a2b9c3e213f9..325f640c16c4 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c | |||
@@ -66,11 +66,16 @@ static void skl_init_clock_gating(struct drm_device *dev) | |||
66 | GEN8_SDEUNIT_CLOCK_GATE_DISABLE); | 66 | GEN8_SDEUNIT_CLOCK_GATE_DISABLE); |
67 | } | 67 | } |
68 | 68 | ||
69 | if (INTEL_REVID(dev) <= SKL_REVID_D0) | 69 | if (INTEL_REVID(dev) <= SKL_REVID_D0) { |
70 | /* WaDisableHDCInvalidation:skl */ | 70 | /* WaDisableHDCInvalidation:skl */ |
71 | I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | | 71 | I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | |
72 | BDW_DISABLE_HDC_INVALIDATION); | 72 | BDW_DISABLE_HDC_INVALIDATION); |
73 | 73 | ||
74 | /* WaDisableChickenBitTSGBarrierAckForFFSliceCS:skl */ | ||
75 | I915_WRITE(FF_SLICE_CS_CHICKEN2, | ||
76 | I915_READ(FF_SLICE_CS_CHICKEN2) | | ||
77 | GEN9_TSG_BARRIER_ACK_DISABLE); | ||
78 | } | ||
74 | 79 | ||
75 | if (INTEL_REVID(dev) <= SKL_REVID_E0) | 80 | if (INTEL_REVID(dev) <= SKL_REVID_E0) |
76 | /* WaDisableLSQCROPERFforOCL:skl */ | 81 | /* WaDisableLSQCROPERFforOCL:skl */ |