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authorImre Deak <imre.deak@intel.com>2018-08-31 13:47:39 -0400
committerImre Deak <imre.deak@intel.com>2018-09-01 02:13:01 -0400
commit2b5cf4ef541f1b2facaca58cae5e8e0b5f19ad4c (patch)
tree2cc5f7ae6e65baa8125f7cad1b0da7cf54e5e30d
parent35ab4fd2b98b8ad11d67606dd209e0947e448074 (diff)
drm/i915/dp_mst: Fix enabling pipe clock for all streams
commit afb2c4437dae ("drm/i915/ddi: Push pipe clock enabling to encoders") inadvertently stopped enabling the pipe clock for any DP-MST stream after the first one. It also rearranged the pipe clock enabling wrt. initial MST payload allocation step (which may or may not be a problem, but it's contrary to the spec.). Fix things by making the above commit truly a non-functional change. Fixes: afb2c4437dae ("drm/i915/ddi: Push pipe clock enabling to encoders") Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107365 Reported-by: Lyude Paul <lyude@redhat.com> Reported-by: dmummenschanz@web.de Tested-by: dmummenschanz@web.de Tested-by: Lyude Paul <lyude@redhat.com> Cc: Lyude Paul <lyude@redhat.com> Cc: dmummenschanz@web.de Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Lyude Paul <lyude@redhat.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180831174739.30387-1-imre.deak@intel.com
-rw-r--r--drivers/gpu/drm/i915/intel_ddi.c17
-rw-r--r--drivers/gpu/drm/i915/intel_dp_mst.c4
2 files changed, 13 insertions, 8 deletions
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index f3b115ce4029..dcb1a98d624d 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -2912,7 +2912,8 @@ static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
2912 2912
2913 icl_enable_phy_clock_gating(dig_port); 2913 icl_enable_phy_clock_gating(dig_port);
2914 2914
2915 intel_ddi_enable_pipe_clock(crtc_state); 2915 if (!is_mst)
2916 intel_ddi_enable_pipe_clock(crtc_state);
2916} 2917}
2917 2918
2918static void intel_ddi_pre_enable_hdmi(struct intel_encoder *encoder, 2919static void intel_ddi_pre_enable_hdmi(struct intel_encoder *encoder,
@@ -3015,14 +3016,14 @@ static void intel_ddi_post_disable_dp(struct intel_encoder *encoder,
3015 bool is_mst = intel_crtc_has_type(old_crtc_state, 3016 bool is_mst = intel_crtc_has_type(old_crtc_state,
3016 INTEL_OUTPUT_DP_MST); 3017 INTEL_OUTPUT_DP_MST);
3017 3018
3018 intel_ddi_disable_pipe_clock(old_crtc_state); 3019 if (!is_mst) {
3019 3020 intel_ddi_disable_pipe_clock(old_crtc_state);
3020 /* 3021 /*
3021 * Power down sink before disabling the port, otherwise we end 3022 * Power down sink before disabling the port, otherwise we end
3022 * up getting interrupts from the sink on detecting link loss. 3023 * up getting interrupts from the sink on detecting link loss.
3023 */ 3024 */
3024 if (!is_mst)
3025 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF); 3025 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
3026 }
3026 3027
3027 intel_disable_ddi_buf(encoder); 3028 intel_disable_ddi_buf(encoder);
3028 3029
diff --git a/drivers/gpu/drm/i915/intel_dp_mst.c b/drivers/gpu/drm/i915/intel_dp_mst.c
index 352e5216cc65..77920f1a3da1 100644
--- a/drivers/gpu/drm/i915/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/intel_dp_mst.c
@@ -166,6 +166,8 @@ static void intel_mst_post_disable_dp(struct intel_encoder *encoder,
166 struct intel_connector *connector = 166 struct intel_connector *connector =
167 to_intel_connector(old_conn_state->connector); 167 to_intel_connector(old_conn_state->connector);
168 168
169 intel_ddi_disable_pipe_clock(old_crtc_state);
170
169 /* this can fail */ 171 /* this can fail */
170 drm_dp_check_act_status(&intel_dp->mst_mgr); 172 drm_dp_check_act_status(&intel_dp->mst_mgr);
171 /* and this can also fail */ 173 /* and this can also fail */
@@ -249,6 +251,8 @@ static void intel_mst_pre_enable_dp(struct intel_encoder *encoder,
249 I915_WRITE(DP_TP_STATUS(port), temp); 251 I915_WRITE(DP_TP_STATUS(port), temp);
250 252
251 ret = drm_dp_update_payload_part1(&intel_dp->mst_mgr); 253 ret = drm_dp_update_payload_part1(&intel_dp->mst_mgr);
254
255 intel_ddi_enable_pipe_clock(pipe_config);
252} 256}
253 257
254static void intel_mst_enable_dp(struct intel_encoder *encoder, 258static void intel_mst_enable_dp(struct intel_encoder *encoder,