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authorOlof Johansson <olof@lixom.net>2017-06-18 23:46:30 -0400
committerOlof Johansson <olof@lixom.net>2017-06-18 23:46:30 -0400
commit2b1ee3061f09bd90a5c659b9cb45fcbf49c5fd4c (patch)
tree37fc6c42bc227468e0c60869fd60e59685726135
parent6198c74939c085fbd31fab3ba6f1eb2ce2820b39 (diff)
parent1df5eaa6bced2d8a9de305d4a5f587adf57ddf35 (diff)
Merge tag 'omap-for-v4.13/soc-v4-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/soc
SoC changes for omap variants for v4.13 merge window: - PM clean-up in preparation of adding am335x/am437x PM support - Fixes for issues found by Coccinelle - Legacy code removal now that everything boots in device tree only mode - Interconnect changes in preparation of moving clkctrl clocks to be managed by clkctrl clock driver - Interconnect changes to add omap4 crypto acceclerator support * tag 'omap-for-v4.13/soc-v4-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: (27 commits) ARM: OMAP4: hwmod_data: add SHAM crypto accelerator ARM: OMAP4: hwmod data: add des ARM: OMAP4: hwmod data: add aes2 ARM: OMAP4: hwmod data: add aes1 ARM: OMAP2+: Remove unused legacy code for n8x0 ARM: OMAP2+: Remove unused legacy code for watchdog ARM: OMAP2+: Remove unused legacy code for interconnects ARM: OMAP2+: Remove unused legacy code for PRM ARM: OMAP2+: Remove unused legacy code for io.c ARM: OMAP2+: Remove unused legacy code for McBSP ARM: OMAP2+: SmartReflex: Delete an error message for a failed memory allocation in two functions ARM: OMAP2+: Use kcalloc() in sr_set_nvalues() ARM: OMAP2+: Improve a size determination in sr_dev_init() ARM: OMAP2+: Delete an error message for a failed memory allocation in two functions ARM: OMAP2+: Remove unused legacy code for device init ARM: OMAP2+: Remove unused legacy code for PMU ARM: OMAP2+: Remove unused legacy code for opp ARM: OMAP2+: hwmod: populate clkctrl clocks for hwmods if available ARM: OMAP4: cminst: add support for clkdm_xlate_address ARM: omap2+: clockdomain: add clkdm_xlate_address ... Signed-off-by: Olof Johansson <olof@lixom.net>
Diffstat
-rw-r--r--arch/arm/mach-omap2/Makefile4
-rw-r--r--arch/arm/mach-omap2/board-n8x0.c14
-rw-r--r--arch/arm/mach-omap2/clockdomain.c8
-rw-r--r--arch/arm/mach-omap2/clockdomain.h2
-rw-r--r--arch/arm/mach-omap2/cm.h7
-rw-r--r--arch/arm/mach-omap2/cm2xxx_3xxx.h4
-rw-r--r--arch/arm/mach-omap2/cm33xx.c4
-rw-r--r--arch/arm/mach-omap2/cm3xxx.c3
-rw-r--r--arch/arm/mach-omap2/cm_common.c31
-rw-r--r--arch/arm/mach-omap2/cminst44xx.c29
-rw-r--r--arch/arm/mach-omap2/devices.c175
-rw-r--r--arch/arm/mach-omap2/hsmmc.c5
-rw-r--r--arch/arm/mach-omap2/io.c59
-rw-r--r--arch/arm/mach-omap2/mcbsp.c70
-rw-r--r--arch/arm/mach-omap2/omap-wakeupgen.c68
-rw-r--r--arch/arm/mach-omap2/omap_device.c5
-rw-r--r--arch/arm/mach-omap2/omap_hwmod.c168
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_3xxx_data.c3
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_44xx_data.c146
-rw-r--r--arch/arm/mach-omap2/opp.c104
-rw-r--r--arch/arm/mach-omap2/opp3xxx_data.c86
-rw-r--r--arch/arm/mach-omap2/opp4xxx_data.c79
-rw-r--r--arch/arm/mach-omap2/pm.c2
-rw-r--r--arch/arm/mach-omap2/pmu.c97
-rw-r--r--arch/arm/mach-omap2/prcm-common.h7
-rw-r--r--arch/arm/mach-omap2/prcm_mpu44xx.c4
-rw-r--r--arch/arm/mach-omap2/prcm_mpu_44xx_54xx.h4
-rw-r--r--arch/arm/mach-omap2/prm.h2
-rw-r--r--arch/arm/mach-omap2/prm2xxx_3xxx.h4
-rw-r--r--arch/arm/mach-omap2/prm33xx.c4
-rw-r--r--arch/arm/mach-omap2/prm3xxx.c19
-rw-r--r--arch/arm/mach-omap2/prm44xx.c63
-rw-r--r--arch/arm/mach-omap2/prm_common.c32
-rw-r--r--arch/arm/mach-omap2/prminst44xx.c16
-rw-r--r--arch/arm/mach-omap2/sr_device.c15
-rw-r--r--arch/arm/mach-omap2/timer.c200
-rw-r--r--arch/arm/mach-omap2/wd_timer.c28
37 files changed, 537 insertions, 1034 deletions
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index c89757abb0ae..779fb1f680b3 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -69,7 +69,6 @@ obj-$(CONFIG_ARCH_OMAP2) += sdrc2xxx.o
69 69
70# OPP table initialization 70# OPP table initialization
71ifeq ($(CONFIG_PM_OPP),y) 71ifeq ($(CONFIG_PM_OPP),y)
72obj-y += opp.o
73obj-$(CONFIG_ARCH_OMAP3) += opp3xxx_data.o 72obj-$(CONFIG_ARCH_OMAP3) += opp3xxx_data.o
74obj-$(CONFIG_ARCH_OMAP4) += opp4xxx_data.o 73obj-$(CONFIG_ARCH_OMAP4) += opp4xxx_data.o
75endif 74endif
@@ -220,9 +219,6 @@ obj-$(CONFIG_ARCH_OMAP4) += omap_hwmod_44xx_data.o
220obj-$(CONFIG_SOC_OMAP5) += omap_hwmod_54xx_data.o 219obj-$(CONFIG_SOC_OMAP5) += omap_hwmod_54xx_data.o
221obj-$(CONFIG_SOC_DRA7XX) += omap_hwmod_7xx_data.o 220obj-$(CONFIG_SOC_DRA7XX) += omap_hwmod_7xx_data.o
222 221
223# EMU peripherals
224obj-$(CONFIG_HW_PERF_EVENTS) += pmu.o
225
226# OMAP2420 MSDI controller integration support ("MMC") 222# OMAP2420 MSDI controller integration support ("MMC")
227obj-$(CONFIG_SOC_OMAP2420) += msdi.o 223obj-$(CONFIG_SOC_OMAP2420) += msdi.o
228 224
diff --git a/arch/arm/mach-omap2/board-n8x0.c b/arch/arm/mach-omap2/board-n8x0.c
index 91272db09fa3..20f25539d572 100644
--- a/arch/arm/mach-omap2/board-n8x0.c
+++ b/arch/arm/mach-omap2/board-n8x0.c
@@ -53,14 +53,12 @@ static u32 board_caps;
53 53
54static void board_check_revision(void) 54static void board_check_revision(void)
55{ 55{
56 if (of_have_populated_dt()) { 56 if (of_machine_is_compatible("nokia,n800"))
57 if (of_machine_is_compatible("nokia,n800")) 57 board_caps = NOKIA_N800;
58 board_caps = NOKIA_N800; 58 else if (of_machine_is_compatible("nokia,n810"))
59 else if (of_machine_is_compatible("nokia,n810")) 59 board_caps = NOKIA_N810;
60 board_caps = NOKIA_N810; 60 else if (of_machine_is_compatible("nokia,n810-wimax"))
61 else if (of_machine_is_compatible("nokia,n810-wimax")) 61 board_caps = NOKIA_N810_WIMAX;
62 board_caps = NOKIA_N810_WIMAX;
63 }
64 62
65 if (!board_caps) 63 if (!board_caps)
66 pr_err("Unknown board\n"); 64 pr_err("Unknown board\n");
diff --git a/arch/arm/mach-omap2/clockdomain.c b/arch/arm/mach-omap2/clockdomain.c
index b79b1ca9aee9..518926410b62 100644
--- a/arch/arm/mach-omap2/clockdomain.c
+++ b/arch/arm/mach-omap2/clockdomain.c
@@ -1224,6 +1224,14 @@ ccd_exit:
1224 return 0; 1224 return 0;
1225} 1225}
1226 1226
1227u32 clkdm_xlate_address(struct clockdomain *clkdm)
1228{
1229 if (arch_clkdm->clkdm_xlate_address)
1230 return arch_clkdm->clkdm_xlate_address(clkdm);
1231
1232 return 0;
1233}
1234
1227/** 1235/**
1228 * clkdm_hwmod_enable - add an enabled downstream hwmod to this clkdm 1236 * clkdm_hwmod_enable - add an enabled downstream hwmod to this clkdm
1229 * @clkdm: struct clockdomain * 1237 * @clkdm: struct clockdomain *
diff --git a/arch/arm/mach-omap2/clockdomain.h b/arch/arm/mach-omap2/clockdomain.h
index 24667a5a9dc0..827f01e2d0af 100644
--- a/arch/arm/mach-omap2/clockdomain.h
+++ b/arch/arm/mach-omap2/clockdomain.h
@@ -175,6 +175,7 @@ struct clkdm_ops {
175 void (*clkdm_deny_idle)(struct clockdomain *clkdm); 175 void (*clkdm_deny_idle)(struct clockdomain *clkdm);
176 int (*clkdm_clk_enable)(struct clockdomain *clkdm); 176 int (*clkdm_clk_enable)(struct clockdomain *clkdm);
177 int (*clkdm_clk_disable)(struct clockdomain *clkdm); 177 int (*clkdm_clk_disable)(struct clockdomain *clkdm);
178 u32 (*clkdm_xlate_address)(struct clockdomain *clkdm);
178}; 179};
179 180
180int clkdm_register_platform_funcs(struct clkdm_ops *co); 181int clkdm_register_platform_funcs(struct clkdm_ops *co);
@@ -213,6 +214,7 @@ int clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk);
213int clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk); 214int clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk);
214int clkdm_hwmod_enable(struct clockdomain *clkdm, struct omap_hwmod *oh); 215int clkdm_hwmod_enable(struct clockdomain *clkdm, struct omap_hwmod *oh);
215int clkdm_hwmod_disable(struct clockdomain *clkdm, struct omap_hwmod *oh); 216int clkdm_hwmod_disable(struct clockdomain *clkdm, struct omap_hwmod *oh);
217u32 clkdm_xlate_address(struct clockdomain *clkdm);
216 218
217extern void __init omap242x_clockdomains_init(void); 219extern void __init omap242x_clockdomains_init(void);
218extern void __init omap243x_clockdomains_init(void); 220extern void __init omap243x_clockdomains_init(void);
diff --git a/arch/arm/mach-omap2/cm.h b/arch/arm/mach-omap2/cm.h
index de75cbcdc9d1..e833984cc85e 100644
--- a/arch/arm/mach-omap2/cm.h
+++ b/arch/arm/mach-omap2/cm.h
@@ -24,8 +24,11 @@
24 24
25# ifndef __ASSEMBLER__ 25# ifndef __ASSEMBLER__
26#include <linux/clk/ti.h> 26#include <linux/clk/ti.h>
27extern void __iomem *cm_base; 27
28extern void __iomem *cm2_base; 28#include "prcm-common.h"
29
30extern struct omap_domain_base cm_base;
31extern struct omap_domain_base cm2_base;
29extern void omap2_set_globals_cm(void __iomem *cm, void __iomem *cm2); 32extern void omap2_set_globals_cm(void __iomem *cm, void __iomem *cm2);
30# endif 33# endif
31 34
diff --git a/arch/arm/mach-omap2/cm2xxx_3xxx.h b/arch/arm/mach-omap2/cm2xxx_3xxx.h
index 72928a3ce2aa..aa148cd57cc1 100644
--- a/arch/arm/mach-omap2/cm2xxx_3xxx.h
+++ b/arch/arm/mach-omap2/cm2xxx_3xxx.h
@@ -52,12 +52,12 @@
52 52
53static inline u32 omap2_cm_read_mod_reg(s16 module, u16 idx) 53static inline u32 omap2_cm_read_mod_reg(s16 module, u16 idx)
54{ 54{
55 return readl_relaxed(cm_base + module + idx); 55 return readl_relaxed(cm_base.va + module + idx);
56} 56}
57 57
58static inline void omap2_cm_write_mod_reg(u32 val, s16 module, u16 idx) 58static inline void omap2_cm_write_mod_reg(u32 val, s16 module, u16 idx)
59{ 59{
60 writel_relaxed(val, cm_base + module + idx); 60 writel_relaxed(val, cm_base.va + module + idx);
61} 61}
62 62
63/* Read-modify-write a register in a CM module. Caller must lock */ 63/* Read-modify-write a register in a CM module. Caller must lock */
diff --git a/arch/arm/mach-omap2/cm33xx.c b/arch/arm/mach-omap2/cm33xx.c
index 6f2d0aec0513..a9e08d89104e 100644
--- a/arch/arm/mach-omap2/cm33xx.c
+++ b/arch/arm/mach-omap2/cm33xx.c
@@ -50,13 +50,13 @@
50/* Read a register in a CM instance */ 50/* Read a register in a CM instance */
51static inline u32 am33xx_cm_read_reg(u16 inst, u16 idx) 51static inline u32 am33xx_cm_read_reg(u16 inst, u16 idx)
52{ 52{
53 return readl_relaxed(cm_base + inst + idx); 53 return readl_relaxed(cm_base.va + inst + idx);
54} 54}
55 55
56/* Write into a register in a CM */ 56/* Write into a register in a CM */
57static inline void am33xx_cm_write_reg(u32 val, u16 inst, u16 idx) 57static inline void am33xx_cm_write_reg(u32 val, u16 inst, u16 idx)
58{ 58{
59 writel_relaxed(val, cm_base + inst + idx); 59 writel_relaxed(val, cm_base.va + inst + idx);
60} 60}
61 61
62/* Read-modify-write a register in CM */ 62/* Read-modify-write a register in CM */
diff --git a/arch/arm/mach-omap2/cm3xxx.c b/arch/arm/mach-omap2/cm3xxx.c
index 55b046a719dc..961bc478b9de 100644
--- a/arch/arm/mach-omap2/cm3xxx.c
+++ b/arch/arm/mach-omap2/cm3xxx.c
@@ -669,7 +669,8 @@ static struct cm_ll_data omap3xxx_cm_ll_data = {
669 669
670int __init omap3xxx_cm_init(const struct omap_prcm_init_data *data) 670int __init omap3xxx_cm_init(const struct omap_prcm_init_data *data)
671{ 671{
672 omap2_clk_legacy_provider_init(TI_CLKM_CM, cm_base + OMAP3430_IVA2_MOD); 672 omap2_clk_legacy_provider_init(TI_CLKM_CM, cm_base.va +
673 OMAP3430_IVA2_MOD);
673 return cm_register(&omap3xxx_cm_ll_data); 674 return cm_register(&omap3xxx_cm_ll_data);
674} 675}
675 676
diff --git a/arch/arm/mach-omap2/cm_common.c b/arch/arm/mach-omap2/cm_common.c
index bbe41f4c9dc8..d555791cf349 100644
--- a/arch/arm/mach-omap2/cm_common.c
+++ b/arch/arm/mach-omap2/cm_common.c
@@ -32,10 +32,10 @@ static struct cm_ll_data null_cm_ll_data;
32static struct cm_ll_data *cm_ll_data = &null_cm_ll_data; 32static struct cm_ll_data *cm_ll_data = &null_cm_ll_data;
33 33
34/* cm_base: base virtual address of the CM IP block */ 34/* cm_base: base virtual address of the CM IP block */
35void __iomem *cm_base; 35struct omap_domain_base cm_base;
36 36
37/* cm2_base: base virtual address of the CM2 IP block (OMAP44xx only) */ 37/* cm2_base: base virtual address of the CM2 IP block (OMAP44xx only) */
38void __iomem *cm2_base; 38struct omap_domain_base cm2_base;
39 39
40#define CM_NO_CLOCKS 0x1 40#define CM_NO_CLOCKS 0x1
41#define CM_SINGLE_INSTANCE 0x2 41#define CM_SINGLE_INSTANCE 0x2
@@ -49,8 +49,8 @@ void __iomem *cm2_base;
49 */ 49 */
50void __init omap2_set_globals_cm(void __iomem *cm, void __iomem *cm2) 50void __init omap2_set_globals_cm(void __iomem *cm, void __iomem *cm2)
51{ 51{
52 cm_base = cm; 52 cm_base.va = cm;
53 cm2_base = cm2; 53 cm2_base.va = cm2;
54} 54}
55 55
56/** 56/**
@@ -315,27 +315,34 @@ int __init omap2_cm_base_init(void)
315 struct device_node *np; 315 struct device_node *np;
316 const struct of_device_id *match; 316 const struct of_device_id *match;
317 struct omap_prcm_init_data *data; 317 struct omap_prcm_init_data *data;
318 void __iomem *mem; 318 struct resource res;
319 int ret;
320 struct omap_domain_base *mem = NULL;
319 321
320 for_each_matching_node_and_match(np, omap_cm_dt_match_table, &match) { 322 for_each_matching_node_and_match(np, omap_cm_dt_match_table, &match) {
321 data = (struct omap_prcm_init_data *)match->data; 323 data = (struct omap_prcm_init_data *)match->data;
322 324
323 mem = of_iomap(np, 0); 325 ret = of_address_to_resource(np, 0, &res);
324 if (!mem) 326 if (ret)
325 return -ENOMEM; 327 return ret;
326 328
327 if (data->index == TI_CLKM_CM) 329 if (data->index == TI_CLKM_CM)
328 cm_base = mem + data->offset; 330 mem = &cm_base;
329 331
330 if (data->index == TI_CLKM_CM2) 332 if (data->index == TI_CLKM_CM2)
331 cm2_base = mem + data->offset; 333 mem = &cm2_base;
334
335 data->mem = ioremap(res.start, resource_size(&res));
332 336
333 data->mem = mem; 337 if (mem) {
338 mem->pa = res.start + data->offset;
339 mem->va = data->mem + data->offset;
340 }
334 341
335 data->np = np; 342 data->np = np;
336 343
337 if (data->init && (data->flags & CM_SINGLE_INSTANCE || 344 if (data->init && (data->flags & CM_SINGLE_INSTANCE ||
338 (cm_base && cm2_base))) 345 (cm_base.va && cm2_base.va)))
339 data->init(data); 346 data->init(data);
340 } 347 }
341 348
diff --git a/arch/arm/mach-omap2/cminst44xx.c b/arch/arm/mach-omap2/cminst44xx.c
index 2ab27ade136a..8774e983bea1 100644
--- a/arch/arm/mach-omap2/cminst44xx.c
+++ b/arch/arm/mach-omap2/cminst44xx.c
@@ -55,7 +55,7 @@
55#define CLKCTRL_IDLEST_INTERFACE_IDLE 0x2 55#define CLKCTRL_IDLEST_INTERFACE_IDLE 0x2
56#define CLKCTRL_IDLEST_DISABLED 0x3 56#define CLKCTRL_IDLEST_DISABLED 0x3
57 57
58static void __iomem *_cm_bases[OMAP4_MAX_PRCM_PARTITIONS]; 58static struct omap_domain_base _cm_bases[OMAP4_MAX_PRCM_PARTITIONS];
59 59
60/** 60/**
61 * omap_cm_base_init - Populates the cm partitions 61 * omap_cm_base_init - Populates the cm partitions
@@ -65,10 +65,11 @@ static void __iomem *_cm_bases[OMAP4_MAX_PRCM_PARTITIONS];
65 */ 65 */
66static void omap_cm_base_init(void) 66static void omap_cm_base_init(void)
67{ 67{
68 _cm_bases[OMAP4430_PRM_PARTITION] = prm_base; 68 memcpy(&_cm_bases[OMAP4430_PRM_PARTITION], &prm_base, sizeof(prm_base));
69 _cm_bases[OMAP4430_CM1_PARTITION] = cm_base; 69 memcpy(&_cm_bases[OMAP4430_CM1_PARTITION], &cm_base, sizeof(cm_base));
70 _cm_bases[OMAP4430_CM2_PARTITION] = cm2_base; 70 memcpy(&_cm_bases[OMAP4430_CM2_PARTITION], &cm2_base, sizeof(cm2_base));
71 _cm_bases[OMAP4430_PRCM_MPU_PARTITION] = prcm_mpu_base; 71 memcpy(&_cm_bases[OMAP4430_PRCM_MPU_PARTITION], &prcm_mpu_base,
72 sizeof(prcm_mpu_base));
72} 73}
73 74
74/* Private functions */ 75/* Private functions */
@@ -116,8 +117,8 @@ static u32 omap4_cminst_read_inst_reg(u8 part, u16 inst, u16 idx)
116{ 117{
117 BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS || 118 BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS ||
118 part == OMAP4430_INVALID_PRCM_PARTITION || 119 part == OMAP4430_INVALID_PRCM_PARTITION ||
119 !_cm_bases[part]); 120 !_cm_bases[part].va);
120 return readl_relaxed(_cm_bases[part] + inst + idx); 121 return readl_relaxed(_cm_bases[part].va + inst + idx);
121} 122}
122 123
123/* Write into a register in a CM instance */ 124/* Write into a register in a CM instance */
@@ -125,8 +126,8 @@ static void omap4_cminst_write_inst_reg(u32 val, u8 part, u16 inst, u16 idx)
125{ 126{
126 BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS || 127 BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS ||
127 part == OMAP4430_INVALID_PRCM_PARTITION || 128 part == OMAP4430_INVALID_PRCM_PARTITION ||
128 !_cm_bases[part]); 129 !_cm_bases[part].va);
129 writel_relaxed(val, _cm_bases[part] + inst + idx); 130 writel_relaxed(val, _cm_bases[part].va + inst + idx);
130} 131}
131 132
132/* Read-modify-write a register in CM1. Caller must lock */ 133/* Read-modify-write a register in CM1. Caller must lock */
@@ -475,6 +476,14 @@ static int omap4_clkdm_clk_disable(struct clockdomain *clkdm)
475 return 0; 476 return 0;
476} 477}
477 478
479static u32 omap4_clkdm_xlate_address(struct clockdomain *clkdm)
480{
481 u32 addr = _cm_bases[clkdm->prcm_partition].pa + clkdm->cm_inst +
482 clkdm->clkdm_offs;
483
484 return addr;
485}
486
478struct clkdm_ops omap4_clkdm_operations = { 487struct clkdm_ops omap4_clkdm_operations = {
479 .clkdm_add_wkdep = omap4_clkdm_add_wkup_sleep_dep, 488 .clkdm_add_wkdep = omap4_clkdm_add_wkup_sleep_dep,
480 .clkdm_del_wkdep = omap4_clkdm_del_wkup_sleep_dep, 489 .clkdm_del_wkdep = omap4_clkdm_del_wkup_sleep_dep,
@@ -490,6 +499,7 @@ struct clkdm_ops omap4_clkdm_operations = {
490 .clkdm_deny_idle = omap4_clkdm_deny_idle, 499 .clkdm_deny_idle = omap4_clkdm_deny_idle,
491 .clkdm_clk_enable = omap4_clkdm_clk_enable, 500 .clkdm_clk_enable = omap4_clkdm_clk_enable,
492 .clkdm_clk_disable = omap4_clkdm_clk_disable, 501 .clkdm_clk_disable = omap4_clkdm_clk_disable,
502 .clkdm_xlate_address = omap4_clkdm_xlate_address,
493}; 503};
494 504
495struct clkdm_ops am43xx_clkdm_operations = { 505struct clkdm_ops am43xx_clkdm_operations = {
@@ -499,6 +509,7 @@ struct clkdm_ops am43xx_clkdm_operations = {
499 .clkdm_deny_idle = omap4_clkdm_deny_idle, 509 .clkdm_deny_idle = omap4_clkdm_deny_idle,
500 .clkdm_clk_enable = omap4_clkdm_clk_enable, 510 .clkdm_clk_enable = omap4_clkdm_clk_enable,
501 .clkdm_clk_disable = omap4_clkdm_clk_disable, 511 .clkdm_clk_disable = omap4_clkdm_clk_disable,
512 .clkdm_xlate_address = omap4_clkdm_xlate_address,
502}; 513};
503 514
504static struct cm_ll_data omap4xxx_cm_ll_data = { 515static struct cm_ll_data omap4xxx_cm_ll_data = {
diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
index 473951203104..93057fb65f44 100644
--- a/arch/arm/mach-omap2/devices.c
+++ b/arch/arm/mach-omap2/devices.c
@@ -36,130 +36,6 @@
36#define L3_MODULES_MAX_LEN 12 36#define L3_MODULES_MAX_LEN 12
37#define L3_MODULES 3 37#define L3_MODULES 3
38 38
39static int __init omap3_l3_init(void)
40{
41 struct omap_hwmod *oh;
42 struct platform_device *pdev;
43 char oh_name[L3_MODULES_MAX_LEN];
44
45 /*
46 * To avoid code running on other OMAPs in
47 * multi-omap builds
48 */
49 if (!(cpu_is_omap34xx()) || of_have_populated_dt())
50 return -ENODEV;
51
52 snprintf(oh_name, L3_MODULES_MAX_LEN, "l3_main");
53
54 oh = omap_hwmod_lookup(oh_name);
55
56 if (!oh)
57 pr_err("could not look up %s\n", oh_name);
58
59 pdev = omap_device_build("omap_l3_smx", 0, oh, NULL, 0);
60
61 WARN(IS_ERR(pdev), "could not build omap_device for %s\n", oh_name);
62
63 return PTR_ERR_OR_ZERO(pdev);
64}
65omap_postcore_initcall(omap3_l3_init);
66
67static inline void omap_init_sti(void) {}
68
69#if IS_ENABLED(CONFIG_SPI_OMAP24XX)
70
71#include <linux/platform_data/spi-omap2-mcspi.h>
72
73static int __init omap_mcspi_init(struct omap_hwmod *oh, void *unused)
74{
75 struct platform_device *pdev;
76 char *name = "omap2_mcspi";
77 struct omap2_mcspi_platform_config *pdata;
78 static int spi_num;
79 struct omap2_mcspi_dev_attr *mcspi_attrib = oh->dev_attr;
80
81 pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
82 if (!pdata) {
83 pr_err("Memory allocation for McSPI device failed\n");
84 return -ENOMEM;
85 }
86
87 pdata->num_cs = mcspi_attrib->num_chipselect;
88 switch (oh->class->rev) {
89 case OMAP2_MCSPI_REV:
90 case OMAP3_MCSPI_REV:
91 pdata->regs_offset = 0;
92 break;
93 case OMAP4_MCSPI_REV:
94 pdata->regs_offset = OMAP4_MCSPI_REG_OFFSET;
95 break;
96 default:
97 pr_err("Invalid McSPI Revision value\n");
98 kfree(pdata);
99 return -EINVAL;
100 }
101
102 spi_num++;
103 pdev = omap_device_build(name, spi_num, oh, pdata, sizeof(*pdata));
104 WARN(IS_ERR(pdev), "Can't build omap_device for %s:%s\n",
105 name, oh->name);
106 kfree(pdata);
107 return 0;
108}
109
110static void omap_init_mcspi(void)
111{
112 omap_hwmod_for_each_by_class("mcspi", omap_mcspi_init, NULL);
113}
114
115#else
116static inline void omap_init_mcspi(void) {}
117#endif
118
119/**
120 * omap_init_rng - bind the RNG hwmod to the RNG omap_device
121 *
122 * Bind the RNG hwmod to the RNG omap_device. No return value.
123 */
124static void __init omap_init_rng(void)
125{
126 struct omap_hwmod *oh;
127 struct platform_device *pdev;
128
129 oh = omap_hwmod_lookup("rng");
130 if (!oh)
131 return;
132
133 pdev = omap_device_build("omap_rng", -1, oh, NULL, 0);
134 WARN(IS_ERR(pdev), "Can't build omap_device for omap_rng\n");
135}
136
137static void __init omap_init_sham(void)
138{
139 struct omap_hwmod *oh;
140 struct platform_device *pdev;
141
142 oh = omap_hwmod_lookup("sham");
143 if (!oh)
144 return;
145
146 pdev = omap_device_build("omap-sham", -1, oh, NULL, 0);
147 WARN(IS_ERR(pdev), "Can't build omap_device for omap-sham\n");
148}
149
150static void __init omap_init_aes(void)
151{
152 struct omap_hwmod *oh;
153 struct platform_device *pdev;
154
155 oh = omap_hwmod_lookup("aes");
156 if (!oh)
157 return;
158
159 pdev = omap_device_build("omap-aes", -1, oh, NULL, 0);
160 WARN(IS_ERR(pdev), "Can't build omap_device for omap-aes\n");
161}
162
163/*-------------------------------------------------------------------------*/ 39/*-------------------------------------------------------------------------*/
164 40
165#if IS_ENABLED(CONFIG_VIDEO_OMAP2_VOUT) 41#if IS_ENABLED(CONFIG_VIDEO_OMAP2_VOUT)
@@ -185,54 +61,3 @@ int __init omap_init_vout(void)
185#else 61#else
186int __init omap_init_vout(void) { return 0; } 62int __init omap_init_vout(void) { return 0; }
187#endif 63#endif
188
189/*-------------------------------------------------------------------------*/
190
191static int __init omap2_init_devices(void)
192{
193 /* Enable dummy states for those platforms without pinctrl support */
194 if (!of_have_populated_dt())
195 pinctrl_provide_dummies();
196
197 /* If dtb is there, the devices will be created dynamically */
198 if (!of_have_populated_dt()) {
199 /*
200 * please keep these calls, and their implementations above,
201 * in alphabetical order so they're easier to sort through.
202 */
203 omap_init_mcspi();
204 omap_init_sham();
205 omap_init_aes();
206 omap_init_rng();
207 }
208 omap_init_sti();
209
210 return 0;
211}
212omap_arch_initcall(omap2_init_devices);
213
214static int __init omap_gpmc_init(void)
215{
216 struct omap_hwmod *oh;
217 struct platform_device *pdev;
218 char *oh_name = "gpmc";
219
220 /*
221 * if the board boots up with a populated DT, do not
222 * manually add the device from this initcall
223 */
224 if (of_have_populated_dt())
225 return -ENODEV;
226
227 oh = omap_hwmod_lookup(oh_name);
228 if (!oh) {
229 pr_err("Could not look up %s\n", oh_name);
230 return -ENODEV;
231 }
232
233 pdev = omap_device_build("omap-gpmc", -1, oh, NULL, 0);
234 WARN(IS_ERR(pdev), "could not build omap_device for %s\n", oh_name);
235
236 return PTR_ERR_OR_ZERO(pdev);
237}
238omap_postcore_initcall(omap_gpmc_init);
diff --git a/arch/arm/mach-omap2/hsmmc.c b/arch/arm/mach-omap2/hsmmc.c
index cb754c46747e..be517b048762 100644
--- a/arch/arm/mach-omap2/hsmmc.c
+++ b/arch/arm/mach-omap2/hsmmc.c
@@ -153,7 +153,6 @@ static int __init omap_hsmmc_pdata_init(struct omap2_hsmmc_info *c,
153 153
154 hc_name = kzalloc(sizeof(char) * (HSMMC_NAME_LEN + 1), GFP_KERNEL); 154 hc_name = kzalloc(sizeof(char) * (HSMMC_NAME_LEN + 1), GFP_KERNEL);
155 if (!hc_name) { 155 if (!hc_name) {
156 pr_err("Cannot allocate memory for controller slot name\n");
157 kfree(hc_name); 156 kfree(hc_name);
158 return -ENOMEM; 157 return -ENOMEM;
159 } 158 }
@@ -315,10 +314,8 @@ static void __init omap_hsmmc_init_one(struct omap2_hsmmc_info *hsmmcinfo,
315 int res; 314 int res;
316 315
317 mmc_data = kzalloc(sizeof(*mmc_data), GFP_KERNEL); 316 mmc_data = kzalloc(sizeof(*mmc_data), GFP_KERNEL);
318 if (!mmc_data) { 317 if (!mmc_data)
319 pr_err("Cannot allocate memory for mmc device!\n");
320 return; 318 return;
321 }
322 319
323 res = omap_hsmmc_pdata_init(hsmmcinfo, mmc_data); 320 res = omap_hsmmc_pdata_init(hsmmcinfo, mmc_data);
324 if (res < 0) 321 if (res < 0)
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 5aafb8449c40..1d739d1a0a65 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -493,67 +493,39 @@ void __init omap3_init_early(void)
493 omap2_set_globals_tap(OMAP343X_CLASS, OMAP2_L4_IO_ADDRESS(0x4830A000)); 493 omap2_set_globals_tap(OMAP343X_CLASS, OMAP2_L4_IO_ADDRESS(0x4830A000));
494 omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP343X_SDRC_BASE), 494 omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP343X_SDRC_BASE),
495 OMAP2_L3_IO_ADDRESS(OMAP343X_SMS_BASE)); 495 OMAP2_L3_IO_ADDRESS(OMAP343X_SMS_BASE));
496 /* XXX: remove these once OMAP3 is DT only */
497 if (!of_have_populated_dt()) {
498 omap2_set_globals_control(
499 OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE));
500 omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP3430_PRM_BASE));
501 omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP3430_CM_BASE),
502 NULL);
503 }
504 omap2_control_base_init(); 496 omap2_control_base_init();
505 omap3xxx_check_revision(); 497 omap3xxx_check_revision();
506 omap3xxx_check_features(); 498 omap3xxx_check_features();
507 omap2_prcm_base_init(); 499 omap2_prcm_base_init();
508 /* XXX: remove these once OMAP3 is DT only */
509 if (!of_have_populated_dt()) {
510 omap3xxx_prm_init(NULL);
511 omap3xxx_cm_init(NULL);
512 }
513 omap3xxx_voltagedomains_init(); 500 omap3xxx_voltagedomains_init();
514 omap3xxx_powerdomains_init(); 501 omap3xxx_powerdomains_init();
515 omap3xxx_clockdomains_init(); 502 omap3xxx_clockdomains_init();
516 omap3xxx_hwmod_init(); 503 omap3xxx_hwmod_init();
517 omap_hwmod_init_postsetup(); 504 omap_hwmod_init_postsetup();
518 if (!of_have_populated_dt()) {
519 omap3_control_legacy_iomap_init();
520 if (soc_is_am35xx())
521 omap_clk_soc_init = am35xx_clk_legacy_init;
522 else if (cpu_is_omap3630())
523 omap_clk_soc_init = omap36xx_clk_legacy_init;
524 else if (omap_rev() == OMAP3430_REV_ES1_0)
525 omap_clk_soc_init = omap3430es1_clk_legacy_init;
526 else
527 omap_clk_soc_init = omap3430_clk_legacy_init;
528 }
529} 505}
530 506
531void __init omap3430_init_early(void) 507void __init omap3430_init_early(void)
532{ 508{
533 omap3_init_early(); 509 omap3_init_early();
534 if (of_have_populated_dt()) 510 omap_clk_soc_init = omap3430_dt_clk_init;
535 omap_clk_soc_init = omap3430_dt_clk_init;
536} 511}
537 512
538void __init omap35xx_init_early(void) 513void __init omap35xx_init_early(void)
539{ 514{
540 omap3_init_early(); 515 omap3_init_early();
541 if (of_have_populated_dt()) 516 omap_clk_soc_init = omap3430_dt_clk_init;
542 omap_clk_soc_init = omap3430_dt_clk_init;
543} 517}
544 518
545void __init omap3630_init_early(void) 519void __init omap3630_init_early(void)
546{ 520{
547 omap3_init_early(); 521 omap3_init_early();
548 if (of_have_populated_dt()) 522 omap_clk_soc_init = omap3630_dt_clk_init;
549 omap_clk_soc_init = omap3630_dt_clk_init;
550} 523}
551 524
552void __init am35xx_init_early(void) 525void __init am35xx_init_early(void)
553{ 526{
554 omap3_init_early(); 527 omap3_init_early();
555 if (of_have_populated_dt()) 528 omap_clk_soc_init = am35xx_dt_clk_init;
556 omap_clk_soc_init = am35xx_dt_clk_init;
557} 529}
558 530
559void __init omap3_init_late(void) 531void __init omap3_init_late(void)
@@ -628,8 +600,7 @@ void __init ti816x_init_early(void)
628 ti816x_clockdomains_init(); 600 ti816x_clockdomains_init();
629 dm816x_hwmod_init(); 601 dm816x_hwmod_init();
630 omap_hwmod_init_postsetup(); 602 omap_hwmod_init_postsetup();
631 if (of_have_populated_dt()) 603 omap_clk_soc_init = dm816x_dt_clk_init;
632 omap_clk_soc_init = dm816x_dt_clk_init;
633} 604}
634#endif 605#endif
635 606
@@ -785,21 +756,19 @@ int __init omap_clk_init(void)
785 756
786 omap2_clk_setup_ll_ops(); 757 omap2_clk_setup_ll_ops();
787 758
788 if (of_have_populated_dt()) { 759 ret = omap_control_init();
789 ret = omap_control_init(); 760 if (ret)
790 if (ret) 761 return ret;
791 return ret;
792 762
793 ret = omap_prcm_init(); 763 ret = omap_prcm_init();
794 if (ret) 764 if (ret)
795 return ret; 765 return ret;
796 766
797 of_clk_init(NULL); 767 of_clk_init(NULL);
798 768
799 ti_dt_clk_init_retry_clks(); 769 ti_dt_clk_init_retry_clks();
800 770
801 ti_dt_clockdomains_setup(); 771 ti_dt_clockdomains_setup();
802 }
803 772
804 ret = omap_clk_soc_init(); 773 ret = omap_clk_soc_init();
805 774
diff --git a/arch/arm/mach-omap2/mcbsp.c b/arch/arm/mach-omap2/mcbsp.c
index fc04be74e064..4acc0dae27e0 100644
--- a/arch/arm/mach-omap2/mcbsp.c
+++ b/arch/arm/mach-omap2/mcbsp.c
@@ -53,73 +53,3 @@ void __init omap3_mcbsp_init_pdata_callback(
53 53
54 pdata->force_ick_on = omap3_mcbsp_force_ick_on; 54 pdata->force_ick_on = omap3_mcbsp_force_ick_on;
55} 55}
56
57static int __init omap_init_mcbsp(struct omap_hwmod *oh, void *unused)
58{
59 int id, count = 1;
60 char *name = "omap-mcbsp";
61 struct omap_hwmod *oh_device[2];
62 struct omap_mcbsp_platform_data *pdata = NULL;
63 struct platform_device *pdev;
64
65 sscanf(oh->name, "mcbsp%d", &id);
66
67 pdata = kzalloc(sizeof(struct omap_mcbsp_platform_data), GFP_KERNEL);
68 if (!pdata) {
69 pr_err("%s: No memory for mcbsp\n", __func__);
70 return -ENOMEM;
71 }
72
73 pdata->reg_step = 4;
74 if (oh->class->rev < MCBSP_CONFIG_TYPE2) {
75 pdata->reg_size = 2;
76 } else {
77 pdata->reg_size = 4;
78 pdata->has_ccr = true;
79 }
80
81 if (oh->class->rev == MCBSP_CONFIG_TYPE2) {
82 /* The FIFO has 128 locations */
83 pdata->buffer_size = 0x80;
84 } else if (oh->class->rev == MCBSP_CONFIG_TYPE3) {
85 if (id == 2)
86 /* The FIFO has 1024 + 256 locations */
87 pdata->buffer_size = 0x500;
88 else
89 /* The FIFO has 128 locations */
90 pdata->buffer_size = 0x80;
91 } else if (oh->class->rev == MCBSP_CONFIG_TYPE4) {
92 /* The FIFO has 128 locations for all instances */
93 pdata->buffer_size = 0x80;
94 }
95
96 if (oh->class->rev >= MCBSP_CONFIG_TYPE3)
97 pdata->has_wakeup = true;
98
99 oh_device[0] = oh;
100
101 if (oh->dev_attr) {
102 oh_device[1] = omap_hwmod_lookup((
103 (struct omap_mcbsp_dev_attr *)(oh->dev_attr))->sidetone);
104 pdata->force_ick_on = omap3_mcbsp_force_ick_on;
105 count++;
106 }
107 pdev = omap_device_build_ss(name, id, oh_device, count, pdata,
108 sizeof(*pdata));
109 kfree(pdata);
110 if (IS_ERR(pdev)) {
111 pr_err("%s: Can't build omap_device for %s:%s.\n", __func__,
112 name, oh->name);
113 return PTR_ERR(pdev);
114 }
115 return 0;
116}
117
118static int __init omap2_mcbsp_init(void)
119{
120 if (!of_have_populated_dt())
121 omap_hwmod_for_each_by_class("mcbsp", omap_init_mcbsp, NULL);
122
123 return 0;
124}
125omap_arch_initcall(omap2_mcbsp_init);
diff --git a/arch/arm/mach-omap2/omap-wakeupgen.c b/arch/arm/mach-omap2/omap-wakeupgen.c
index 369f95a703ac..33ed5d53fa45 100644
--- a/arch/arm/mach-omap2/omap-wakeupgen.c
+++ b/arch/arm/mach-omap2/omap-wakeupgen.c
@@ -58,6 +58,17 @@ static unsigned int irq_banks = DEFAULT_NR_REG_BANKS;
58static unsigned int max_irqs = DEFAULT_IRQS; 58static unsigned int max_irqs = DEFAULT_IRQS;
59static unsigned int omap_secure_apis; 59static unsigned int omap_secure_apis;
60 60
61#ifdef CONFIG_CPU_PM
62static unsigned int wakeupgen_context[MAX_NR_REG_BANKS];
63#endif
64
65struct omap_wakeupgen_ops {
66 void (*save_context)(void);
67 void (*restore_context)(void);
68};
69
70static struct omap_wakeupgen_ops *wakeupgen_ops;
71
61/* 72/*
62 * Static helper functions. 73 * Static helper functions.
63 */ 74 */
@@ -264,6 +275,16 @@ static inline void omap5_irq_save_context(void)
264 275
265} 276}
266 277
278static inline void am43xx_irq_save_context(void)
279{
280 u32 i;
281
282 for (i = 0; i < irq_banks; i++) {
283 wakeupgen_context[i] = wakeupgen_readl(i, 0);
284 wakeupgen_writel(0, i, CPU0_ID);
285 }
286}
287
267/* 288/*
268 * Save WakeupGen interrupt context in SAR BANK3. Restore is done by 289 * Save WakeupGen interrupt context in SAR BANK3. Restore is done by
269 * ROM code. WakeupGen IP is integrated along with GIC to manage the 290 * ROM code. WakeupGen IP is integrated along with GIC to manage the
@@ -280,11 +301,8 @@ static void irq_save_context(void)
280 301
281 if (!sar_base) 302 if (!sar_base)
282 sar_base = omap4_get_sar_ram_base(); 303 sar_base = omap4_get_sar_ram_base();
283 304 if (wakeupgen_ops && wakeupgen_ops->save_context)
284 if (soc_is_omap54xx()) 305 wakeupgen_ops->save_context();
285 omap5_irq_save_context();
286 else
287 omap4_irq_save_context();
288} 306}
289 307
290/* 308/*
@@ -306,6 +324,20 @@ static void irq_sar_clear(void)
306 writel_relaxed(val, sar_base + offset); 324 writel_relaxed(val, sar_base + offset);
307} 325}
308 326
327static void am43xx_irq_restore_context(void)
328{
329 u32 i;
330
331 for (i = 0; i < irq_banks; i++)
332 wakeupgen_writel(wakeupgen_context[i], i, CPU0_ID);
333}
334
335static void irq_restore_context(void)
336{
337 if (wakeupgen_ops && wakeupgen_ops->restore_context)
338 wakeupgen_ops->restore_context();
339}
340
309/* 341/*
310 * Save GIC and Wakeupgen interrupt context using secure API 342 * Save GIC and Wakeupgen interrupt context using secure API
311 * for HS/EMU devices. 343 * for HS/EMU devices.
@@ -319,6 +351,26 @@ static void irq_save_secure_context(void)
319 if (ret != API_HAL_RET_VALUE_OK) 351 if (ret != API_HAL_RET_VALUE_OK)
320 pr_err("GIC and Wakeupgen context save failed\n"); 352 pr_err("GIC and Wakeupgen context save failed\n");
321} 353}
354
355/* Define ops for context save and restore for each SoC */
356static struct omap_wakeupgen_ops omap4_wakeupgen_ops = {
357 .save_context = omap4_irq_save_context,
358 .restore_context = irq_sar_clear,
359};
360
361static struct omap_wakeupgen_ops omap5_wakeupgen_ops = {
362 .save_context = omap5_irq_save_context,
363 .restore_context = irq_sar_clear,
364};
365
366static struct omap_wakeupgen_ops am43xx_wakeupgen_ops = {
367 .save_context = am43xx_irq_save_context,
368 .restore_context = am43xx_irq_restore_context,
369};
370#else
371static struct omap_wakeupgen_ops omap4_wakeupgen_ops = {};
372static struct omap_wakeupgen_ops omap5_wakeupgen_ops = {};
373static struct omap_wakeupgen_ops am43xx_wakeupgen_ops = {};
322#endif 374#endif
323 375
324#ifdef CONFIG_HOTPLUG_CPU 376#ifdef CONFIG_HOTPLUG_CPU
@@ -359,7 +411,7 @@ static int irq_notifier(struct notifier_block *self, unsigned long cmd, void *v)
359 break; 411 break;
360 case CPU_CLUSTER_PM_EXIT: 412 case CPU_CLUSTER_PM_EXIT:
361 if (omap_type() == OMAP2_DEVICE_TYPE_GP) 413 if (omap_type() == OMAP2_DEVICE_TYPE_GP)
362 irq_sar_clear(); 414 irq_restore_context();
363 break; 415 break;
364 } 416 }
365 return NOTIFY_OK; 417 return NOTIFY_OK;
@@ -494,9 +546,13 @@ static int __init wakeupgen_init(struct device_node *node,
494 irq_banks = OMAP4_NR_BANKS; 546 irq_banks = OMAP4_NR_BANKS;
495 max_irqs = OMAP4_NR_IRQS; 547 max_irqs = OMAP4_NR_IRQS;
496 omap_secure_apis = 1; 548 omap_secure_apis = 1;
549 wakeupgen_ops = &omap4_wakeupgen_ops;
550 } else if (soc_is_omap54xx()) {
551 wakeupgen_ops = &omap5_wakeupgen_ops;
497 } else if (soc_is_am43xx()) { 552 } else if (soc_is_am43xx()) {
498 irq_banks = AM43XX_NR_REG_BANKS; 553 irq_banks = AM43XX_NR_REG_BANKS;
499 max_irqs = AM43XX_IRQS; 554 max_irqs = AM43XX_IRQS;
555 wakeupgen_ops = &am43xx_wakeupgen_ops;
500 } 556 }
501 557
502 domain = irq_domain_add_hierarchy(parent_domain, 0, max_irqs, 558 domain = irq_domain_add_hierarchy(parent_domain, 0, max_irqs,
diff --git a/arch/arm/mach-omap2/omap_device.c b/arch/arm/mach-omap2/omap_device.c
index f989145480c8..ef9ffb8ac912 100644
--- a/arch/arm/mach-omap2/omap_device.c
+++ b/arch/arm/mach-omap2/omap_device.c
@@ -65,7 +65,7 @@ static void _add_clkdev(struct omap_device *od, const char *clk_alias,
65 65
66 r = clk_get_sys(NULL, clk_name); 66 r = clk_get_sys(NULL, clk_name);
67 67
68 if (IS_ERR(r) && of_have_populated_dt()) { 68 if (IS_ERR(r)) {
69 struct of_phandle_args clkspec; 69 struct of_phandle_args clkspec;
70 70
71 clkspec.np = of_find_node_by_name(NULL, clk_name); 71 clkspec.np = of_find_node_by_name(NULL, clk_name);
@@ -953,9 +953,6 @@ static int __init omap_device_late_init(void)
953{ 953{
954 bus_for_each_dev(&platform_bus_type, NULL, NULL, omap_device_late_idle); 954 bus_for_each_dev(&platform_bus_type, NULL, NULL, omap_device_late_idle);
955 955
956 WARN(!of_have_populated_dt(),
957 "legacy booting deprecated, please update to boot with .dts\n");
958
959 return 0; 956 return 0;
960} 957}
961omap_late_initcall_sync(omap_device_late_init); 958omap_late_initcall_sync(omap_device_late_init);
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index 8bcea0d83fa0..3b47ded5fa0c 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -141,6 +141,7 @@
141#include <linux/cpu.h> 141#include <linux/cpu.h>
142#include <linux/of.h> 142#include <linux/of.h>
143#include <linux/of_address.h> 143#include <linux/of_address.h>
144#include <linux/bootmem.h>
144 145
145#include <asm/system_misc.h> 146#include <asm/system_misc.h>
146 147
@@ -182,6 +183,24 @@
182#define MOD_CLK_MAX_NAME_LEN 32 183#define MOD_CLK_MAX_NAME_LEN 32
183 184
184/** 185/**
186 * struct clkctrl_provider - clkctrl provider mapping data
187 * @addr: base address for the provider
188 * @offset: base offset for the provider
189 * @clkdm: base clockdomain for provider
190 * @node: device node associated with the provider
191 * @link: list link
192 */
193struct clkctrl_provider {
194 u32 addr;
195 u16 offset;
196 struct clockdomain *clkdm;
197 struct device_node *node;
198 struct list_head link;
199};
200
201static LIST_HEAD(clkctrl_providers);
202
203/**
185 * struct omap_hwmod_soc_ops - fn ptrs for some SoC-specific operations 204 * struct omap_hwmod_soc_ops - fn ptrs for some SoC-specific operations
186 * @enable_module: function to enable a module (via MODULEMODE) 205 * @enable_module: function to enable a module (via MODULEMODE)
187 * @disable_module: function to disable a module (via MODULEMODE) 206 * @disable_module: function to disable a module (via MODULEMODE)
@@ -204,6 +223,8 @@ struct omap_hwmod_soc_ops {
204 void (*update_context_lost)(struct omap_hwmod *oh); 223 void (*update_context_lost)(struct omap_hwmod *oh);
205 int (*get_context_lost)(struct omap_hwmod *oh); 224 int (*get_context_lost)(struct omap_hwmod *oh);
206 int (*disable_direct_prcm)(struct omap_hwmod *oh); 225 int (*disable_direct_prcm)(struct omap_hwmod *oh);
226 u32 (*xlate_clkctrl)(struct omap_hwmod *oh,
227 struct clkctrl_provider *provider);
207}; 228};
208 229
209/* soc_ops: adapts the omap_hwmod code to the currently-booted SoC */ 230/* soc_ops: adapts the omap_hwmod code to the currently-booted SoC */
@@ -690,6 +711,103 @@ static int _del_initiator_dep(struct omap_hwmod *oh, struct omap_hwmod *init_oh)
690 return clkdm_del_sleepdep(clkdm, init_clkdm); 711 return clkdm_del_sleepdep(clkdm, init_clkdm);
691} 712}
692 713
714static const struct of_device_id ti_clkctrl_match_table[] __initconst = {
715 { .compatible = "ti,clkctrl" },
716 { }
717};
718
719static int _match_clkdm(struct clockdomain *clkdm, void *user)
720{
721 struct clkctrl_provider *provider = user;
722
723 if (clkdm_xlate_address(clkdm) == provider->addr) {
724 pr_debug("%s: Matched clkdm %s for addr %x (%s)\n", __func__,
725 clkdm->name, provider->addr,
726 provider->node->parent->name);
727 provider->clkdm = clkdm;
728
729 return -1;
730 }
731
732 return 0;
733}
734
735static int _setup_clkctrl_provider(struct device_node *np)
736{
737 const __be32 *addrp;
738 struct clkctrl_provider *provider;
739
740 provider = memblock_virt_alloc(sizeof(*provider), 0);
741 if (!provider)
742 return -ENOMEM;
743
744 addrp = of_get_address(np, 0, NULL, NULL);
745 provider->addr = (u32)of_translate_address(np, addrp);
746 provider->offset = provider->addr & 0xff;
747 provider->addr &= ~0xff;
748 provider->node = np;
749
750 clkdm_for_each(_match_clkdm, provider);
751
752 if (!provider->clkdm) {
753 pr_err("%s: nothing matched for node %s (%x)\n",
754 __func__, np->parent->name, provider->addr);
755 memblock_free_early(__pa(provider), sizeof(*provider));
756 return -EINVAL;
757 }
758
759 list_add(&provider->link, &clkctrl_providers);
760
761 return 0;
762}
763
764static int _init_clkctrl_providers(void)
765{
766 struct device_node *np;
767 int ret = 0;
768
769 for_each_matching_node(np, ti_clkctrl_match_table) {
770 ret = _setup_clkctrl_provider(np);
771 if (ret)
772 break;
773 }
774
775 return ret;
776}
777
778static u32 _omap4_xlate_clkctrl(struct omap_hwmod *oh,
779 struct clkctrl_provider *provider)
780{
781 return oh->prcm.omap4.clkctrl_offs -
782 provider->offset - provider->clkdm->clkdm_offs;
783}
784
785static struct clk *_lookup_clkctrl_clk(struct omap_hwmod *oh)
786{
787 struct clkctrl_provider *provider;
788 struct clk *clk;
789
790 if (!soc_ops.xlate_clkctrl)
791 return NULL;
792
793 list_for_each_entry(provider, &clkctrl_providers, link) {
794 if (provider->clkdm == oh->clkdm) {
795 struct of_phandle_args clkspec;
796
797 clkspec.np = provider->node;
798 clkspec.args_count = 2;
799 clkspec.args[0] = soc_ops.xlate_clkctrl(oh, provider);
800 clkspec.args[1] = 0;
801
802 clk = of_clk_get_from_provider(&clkspec);
803
804 return clk;
805 }
806 }
807
808 return NULL;
809}
810
693/** 811/**
694 * _init_main_clk - get a struct clk * for the the hwmod's main functional clk 812 * _init_main_clk - get a struct clk * for the the hwmod's main functional clk
695 * @oh: struct omap_hwmod * 813 * @oh: struct omap_hwmod *
@@ -701,22 +819,16 @@ static int _del_initiator_dep(struct omap_hwmod *oh, struct omap_hwmod *init_oh)
701static int _init_main_clk(struct omap_hwmod *oh) 819static int _init_main_clk(struct omap_hwmod *oh)
702{ 820{
703 int ret = 0; 821 int ret = 0;
704 char name[MOD_CLK_MAX_NAME_LEN]; 822 struct clk *clk = NULL;
705 struct clk *clk;
706 static const char modck[] = "_mod_ck";
707 823
708 if (strlen(oh->name) >= MOD_CLK_MAX_NAME_LEN - strlen(modck)) 824 clk = _lookup_clkctrl_clk(oh);
709 pr_warn("%s: warning: cropping name for %s\n", __func__,
710 oh->name);
711
712 strlcpy(name, oh->name, MOD_CLK_MAX_NAME_LEN - strlen(modck));
713 strlcat(name, modck, MOD_CLK_MAX_NAME_LEN);
714 825
715 clk = clk_get(NULL, name); 826 if (!IS_ERR_OR_NULL(clk)) {
716 if (!IS_ERR(clk)) { 827 pr_debug("%s: mapped main_clk %s for %s\n", __func__,
828 __clk_get_name(clk), oh->name);
829 oh->main_clk = __clk_get_name(clk);
717 oh->_clk = clk; 830 oh->_clk = clk;
718 soc_ops.disable_direct_prcm(oh); 831 soc_ops.disable_direct_prcm(oh);
719 oh->main_clk = kstrdup(name, GFP_KERNEL);
720 } else { 832 } else {
721 if (!oh->main_clk) 833 if (!oh->main_clk)
722 return 0; 834 return 0;
@@ -1482,13 +1594,13 @@ static int _init_clkdm(struct omap_hwmod *oh)
1482 * _init_clocks - clk_get() all clocks associated with this hwmod. Retrieve as 1594 * _init_clocks - clk_get() all clocks associated with this hwmod. Retrieve as
1483 * well the clockdomain. 1595 * well the clockdomain.
1484 * @oh: struct omap_hwmod * 1596 * @oh: struct omap_hwmod *
1485 * @data: not used; pass NULL 1597 * @np: device_node mapped to this hwmod
1486 * 1598 *
1487 * Called by omap_hwmod_setup_*() (after omap2_clk_init()). 1599 * Called by omap_hwmod_setup_*() (after omap2_clk_init()).
1488 * Resolves all clock names embedded in the hwmod. Returns 0 on 1600 * Resolves all clock names embedded in the hwmod. Returns 0 on
1489 * success, or a negative error code on failure. 1601 * success, or a negative error code on failure.
1490 */ 1602 */
1491static int _init_clocks(struct omap_hwmod *oh, void *data) 1603static int _init_clocks(struct omap_hwmod *oh, struct device_node *np)
1492{ 1604{
1493 int ret = 0; 1605 int ret = 0;
1494 1606
@@ -2334,24 +2446,21 @@ static int __init _init(struct omap_hwmod *oh, void *data)
2334{ 2446{
2335 int r, index; 2447 int r, index;
2336 struct device_node *np = NULL; 2448 struct device_node *np = NULL;
2449 struct device_node *bus;
2337 2450
2338 if (oh->_state != _HWMOD_STATE_REGISTERED) 2451 if (oh->_state != _HWMOD_STATE_REGISTERED)
2339 return 0; 2452 return 0;
2340 2453
2341 if (of_have_populated_dt()) { 2454 bus = of_find_node_by_name(NULL, "ocp");
2342 struct device_node *bus; 2455 if (!bus)
2456 return -ENODEV;
2343 2457
2344 bus = of_find_node_by_name(NULL, "ocp"); 2458 r = of_dev_hwmod_lookup(bus, oh, &index, &np);
2345 if (!bus) 2459 if (r)
2346 return -ENODEV; 2460 pr_debug("omap_hwmod: %s missing dt data\n", oh->name);
2347 2461 else if (np && index)
2348 r = of_dev_hwmod_lookup(bus, oh, &index, &np); 2462 pr_warn("omap_hwmod: %s using broken dt data from %s\n",
2349 if (r) 2463 oh->name, np->name);
2350 pr_debug("omap_hwmod: %s missing dt data\n", oh->name);
2351 else if (np && index)
2352 pr_warn("omap_hwmod: %s using broken dt data from %s\n",
2353 oh->name, np->name);
2354 }
2355 2464
2356 r = _init_mpu_rt_base(oh, NULL, index, np); 2465 r = _init_mpu_rt_base(oh, NULL, index, np);
2357 if (r < 0) { 2466 if (r < 0) {
@@ -2360,7 +2469,7 @@ static int __init _init(struct omap_hwmod *oh, void *data)
2360 return 0; 2469 return 0;
2361 } 2470 }
2362 2471
2363 r = _init_clocks(oh, NULL); 2472 r = _init_clocks(oh, np);
2364 if (r < 0) { 2473 if (r < 0) {
2365 WARN(1, "omap_hwmod: %s: couldn't init clocks\n", oh->name); 2474 WARN(1, "omap_hwmod: %s: couldn't init clocks\n", oh->name);
2366 return -EINVAL; 2475 return -EINVAL;
@@ -3722,6 +3831,7 @@ void __init omap_hwmod_init(void)
3722 soc_ops.update_context_lost = _omap4_update_context_lost; 3831 soc_ops.update_context_lost = _omap4_update_context_lost;
3723 soc_ops.get_context_lost = _omap4_get_context_lost; 3832 soc_ops.get_context_lost = _omap4_get_context_lost;
3724 soc_ops.disable_direct_prcm = _omap4_disable_direct_prcm; 3833 soc_ops.disable_direct_prcm = _omap4_disable_direct_prcm;
3834 soc_ops.xlate_clkctrl = _omap4_xlate_clkctrl;
3725 } else if (cpu_is_ti814x() || cpu_is_ti816x() || soc_is_am33xx() || 3835 } else if (cpu_is_ti814x() || cpu_is_ti816x() || soc_is_am33xx() ||
3726 soc_is_am43xx()) { 3836 soc_is_am43xx()) {
3727 soc_ops.enable_module = _omap4_enable_module; 3837 soc_ops.enable_module = _omap4_enable_module;
@@ -3736,6 +3846,8 @@ void __init omap_hwmod_init(void)
3736 WARN(1, "omap_hwmod: unknown SoC type\n"); 3846 WARN(1, "omap_hwmod: unknown SoC type\n");
3737 } 3847 }
3738 3848
3849 _init_clkctrl_providers();
3850
3739 inited = true; 3851 inited = true;
3740} 3852}
3741 3853
diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
index 1c6ca4d5fa2d..c3276436b0ae 100644
--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
@@ -3204,8 +3204,7 @@ int __init omap3xxx_hwmod_init(void)
3204 * If DT information is missing, enable them only for GP devices. 3204 * If DT information is missing, enable them only for GP devices.
3205 */ 3205 */
3206 3206
3207 if (of_have_populated_dt()) 3207 bus = of_find_node_by_name(NULL, "ocp");
3208 bus = of_find_node_by_name(NULL, "ocp");
3209 3208
3210 if (h_sham && omap3xxx_hwmod_is_hs_ip_block_usable(bus, "sham")) { 3209 if (h_sham && omap3xxx_hwmod_is_hs_ip_block_usable(bus, "sham")) {
3211 r = omap_hwmod_register_links(h_sham); 3210 r = omap_hwmod_register_links(h_sham);
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index 94f09c720f29..3e2d792fd9df 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -775,6 +775,7 @@ static struct omap_hwmod_dma_info omap44xx_dss_hdmi_sdma_reqs[] = {
775 775
776static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = { 776static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
777 { .role = "sys_clk", .clk = "dss_sys_clk" }, 777 { .role = "sys_clk", .clk = "dss_sys_clk" },
778 { .role = "hdmi_clk", .clk = "dss_48mhz_clk" },
778}; 779};
779 780
780static struct omap_hwmod omap44xx_dss_hdmi_hwmod = { 781static struct omap_hwmod omap44xx_dss_hdmi_hwmod = {
@@ -785,7 +786,7 @@ static struct omap_hwmod omap44xx_dss_hdmi_hwmod = {
785 * HDMI audio requires to use no-idle mode. Hence, 786 * HDMI audio requires to use no-idle mode. Hence,
786 * set idle mode by software. 787 * set idle mode by software.
787 */ 788 */
788 .flags = HWMOD_SWSUP_SIDLE, 789 .flags = HWMOD_SWSUP_SIDLE | HWMOD_OPT_CLKS_NEEDED,
789 .mpu_irqs = omap44xx_dss_hdmi_irqs, 790 .mpu_irqs = omap44xx_dss_hdmi_irqs,
790 .xlate_irq = omap4_xlate_irq, 791 .xlate_irq = omap4_xlate_irq,
791 .sdma_reqs = omap44xx_dss_hdmi_sdma_reqs, 792 .sdma_reqs = omap44xx_dss_hdmi_sdma_reqs,
@@ -858,11 +859,16 @@ static struct omap_hwmod_class omap44xx_venc_hwmod_class = {
858}; 859};
859 860
860/* dss_venc */ 861/* dss_venc */
862static struct omap_hwmod_opt_clk dss_venc_opt_clks[] = {
863 { .role = "tv_clk", .clk = "dss_tv_clk" },
864};
865
861static struct omap_hwmod omap44xx_dss_venc_hwmod = { 866static struct omap_hwmod omap44xx_dss_venc_hwmod = {
862 .name = "dss_venc", 867 .name = "dss_venc",
863 .class = &omap44xx_venc_hwmod_class, 868 .class = &omap44xx_venc_hwmod_class,
864 .clkdm_name = "l3_dss_clkdm", 869 .clkdm_name = "l3_dss_clkdm",
865 .main_clk = "dss_tv_clk", 870 .main_clk = "dss_tv_clk",
871 .flags = HWMOD_OPT_CLKS_NEEDED,
866 .prcm = { 872 .prcm = {
867 .omap4 = { 873 .omap4 = {
868 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET, 874 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
@@ -870,6 +876,35 @@ static struct omap_hwmod omap44xx_dss_venc_hwmod = {
870 }, 876 },
871 }, 877 },
872 .parent_hwmod = &omap44xx_dss_hwmod, 878 .parent_hwmod = &omap44xx_dss_hwmod,
879 .opt_clks = dss_venc_opt_clks,
880 .opt_clks_cnt = ARRAY_SIZE(dss_venc_opt_clks),
881};
882
883/* sha0 HIB2 (the 'P' (public) device) */
884static struct omap_hwmod_class_sysconfig omap44xx_sha0_sysc = {
885 .rev_offs = 0x100,
886 .sysc_offs = 0x110,
887 .syss_offs = 0x114,
888 .sysc_flags = SYSS_HAS_RESET_STATUS,
889};
890
891static struct omap_hwmod_class omap44xx_sha0_hwmod_class = {
892 .name = "sham",
893 .sysc = &omap44xx_sha0_sysc,
894};
895
896struct omap_hwmod omap44xx_sha0_hwmod = {
897 .name = "sham",
898 .class = &omap44xx_sha0_hwmod_class,
899 .clkdm_name = "l4_secure_clkdm",
900 .main_clk = "l3_div_ck",
901 .prcm = {
902 .omap4 = {
903 .clkctrl_offs = OMAP4_CM_L4SEC_SHA2MD51_CLKCTRL_OFFSET,
904 .context_offs = OMAP4_RM_L4SEC_SHA2MD51_CONTEXT_OFFSET,
905 .modulemode = MODULEMODE_SWCTRL,
906 },
907 },
873}; 908};
874 909
875/* 910/*
@@ -953,6 +988,103 @@ static struct omap_hwmod omap44xx_emif2_hwmod = {
953}; 988};
954 989
955/* 990/*
991 Crypto modules AES0/1 belong to:
992 PD_L4_PER power domain
993 CD_L4_SEC clock domain
994 On the L3, the AES modules are mapped to
995 L3_CLK2: Peripherals and multimedia sub clock domain
996*/
997static struct omap_hwmod_class_sysconfig omap44xx_aes_sysc = {
998 .rev_offs = 0x80,
999 .sysc_offs = 0x84,
1000 .syss_offs = 0x88,
1001 .sysc_flags = SYSS_HAS_RESET_STATUS,
1002};
1003
1004static struct omap_hwmod_class omap44xx_aes_hwmod_class = {
1005 .name = "aes",
1006 .sysc = &omap44xx_aes_sysc,
1007};
1008
1009static struct omap_hwmod omap44xx_aes1_hwmod = {
1010 .name = "aes1",
1011 .class = &omap44xx_aes_hwmod_class,
1012 .clkdm_name = "l4_secure_clkdm",
1013 .main_clk = "l3_div_ck",
1014 .prcm = {
1015 .omap4 = {
1016 .context_offs = OMAP4_RM_L4SEC_AES1_CONTEXT_OFFSET,
1017 .clkctrl_offs = OMAP4_CM_L4SEC_AES1_CLKCTRL_OFFSET,
1018 .modulemode = MODULEMODE_SWCTRL,
1019 },
1020 },
1021};
1022
1023static struct omap_hwmod_ocp_if omap44xx_l3_main_2__aes1 = {
1024 .master = &omap44xx_l4_per_hwmod,
1025 .slave = &omap44xx_aes1_hwmod,
1026 .clk = "l3_div_ck",
1027 .user = OCP_USER_MPU | OCP_USER_SDMA,
1028};
1029
1030static struct omap_hwmod omap44xx_aes2_hwmod = {
1031 .name = "aes2",
1032 .class = &omap44xx_aes_hwmod_class,
1033 .clkdm_name = "l4_secure_clkdm",
1034 .main_clk = "l3_div_ck",
1035 .prcm = {
1036 .omap4 = {
1037 .context_offs = OMAP4_RM_L4SEC_AES2_CONTEXT_OFFSET,
1038 .clkctrl_offs = OMAP4_CM_L4SEC_AES2_CLKCTRL_OFFSET,
1039 .modulemode = MODULEMODE_SWCTRL,
1040 },
1041 },
1042};
1043
1044static struct omap_hwmod_ocp_if omap44xx_l3_main_2__aes2 = {
1045 .master = &omap44xx_l4_per_hwmod,
1046 .slave = &omap44xx_aes2_hwmod,
1047 .clk = "l3_div_ck",
1048 .user = OCP_USER_MPU | OCP_USER_SDMA,
1049};
1050
1051/*
1052 * 'des' class for DES3DES module
1053 */
1054static struct omap_hwmod_class_sysconfig omap44xx_des_sysc = {
1055 .rev_offs = 0x30,
1056 .sysc_offs = 0x34,
1057 .syss_offs = 0x38,
1058 .sysc_flags = SYSS_HAS_RESET_STATUS,
1059};
1060
1061static struct omap_hwmod_class omap44xx_des_hwmod_class = {
1062 .name = "des",
1063 .sysc = &omap44xx_des_sysc,
1064};
1065
1066static struct omap_hwmod omap44xx_des_hwmod = {
1067 .name = "des",
1068 .class = &omap44xx_des_hwmod_class,
1069 .clkdm_name = "l4_secure_clkdm",
1070 .main_clk = "l3_div_ck",
1071 .prcm = {
1072 .omap4 = {
1073 .context_offs = OMAP4_RM_L4SEC_DES3DES_CONTEXT_OFFSET,
1074 .clkctrl_offs = OMAP4_CM_L4SEC_DES3DES_CLKCTRL_OFFSET,
1075 .modulemode = MODULEMODE_SWCTRL,
1076 },
1077 },
1078};
1079
1080struct omap_hwmod_ocp_if omap44xx_l3_main_2__des = {
1081 .master = &omap44xx_l3_main_2_hwmod,
1082 .slave = &omap44xx_des_hwmod,
1083 .clk = "l3_div_ck",
1084 .user = OCP_USER_MPU | OCP_USER_SDMA,
1085};
1086
1087/*
956 * 'fdif' class 1088 * 'fdif' class
957 * face detection hw accelerator module 1089 * face detection hw accelerator module
958 */ 1090 */
@@ -3882,6 +4014,14 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc = {
3882 .user = OCP_USER_MPU, 4014 .user = OCP_USER_MPU,
3883}; 4015};
3884 4016
4017/* l3_main_2 -> sham */
4018static struct omap_hwmod_ocp_if omap44xx_l3_main_2__sha0 = {
4019 .master = &omap44xx_l3_main_2_hwmod,
4020 .slave = &omap44xx_sha0_hwmod,
4021 .clk = "l3_div_ck",
4022 .user = OCP_USER_MPU | OCP_USER_SDMA,
4023};
4024
3885/* l4_per -> elm */ 4025/* l4_per -> elm */
3886static struct omap_hwmod_ocp_if omap44xx_l4_per__elm = { 4026static struct omap_hwmod_ocp_if omap44xx_l4_per__elm = {
3887 .master = &omap44xx_l4_per_hwmod, 4027 .master = &omap44xx_l4_per_hwmod,
@@ -4793,6 +4933,10 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
4793 &omap44xx_l4_abe__wd_timer3_dma, 4933 &omap44xx_l4_abe__wd_timer3_dma,
4794 &omap44xx_mpu__emif1, 4934 &omap44xx_mpu__emif1,
4795 &omap44xx_mpu__emif2, 4935 &omap44xx_mpu__emif2,
4936 &omap44xx_l3_main_2__aes1,
4937 &omap44xx_l3_main_2__aes2,
4938 &omap44xx_l3_main_2__des,
4939 &omap44xx_l3_main_2__sha0,
4796 NULL, 4940 NULL,
4797}; 4941};
4798 4942
diff --git a/arch/arm/mach-omap2/opp.c b/arch/arm/mach-omap2/opp.c
deleted file mode 100644
index a358a07e18f2..000000000000
--- a/arch/arm/mach-omap2/opp.c
+++ /dev/null
@@ -1,104 +0,0 @@
1/*
2 * OMAP SoC specific OPP wrapper function
3 *
4 * Copyright (C) 2009-2010 Texas Instruments Incorporated - http://www.ti.com/
5 * Nishanth Menon
6 * Kevin Hilman
7 * Copyright (C) 2010 Nokia Corporation.
8 * Eduardo Valentin
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 *
14 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
15 * kind, whether express or implied; without even the implied warranty
16 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 */
19#include <linux/module.h>
20#include <linux/of.h>
21#include <linux/pm_opp.h>
22#include <linux/cpu.h>
23
24#include "omap_device.h"
25
26#include "omap_opp_data.h"
27
28/* Temp variable to allow multiple calls */
29static u8 __initdata omap_table_init;
30
31/**
32 * omap_init_opp_table() - Initialize opp table as per the CPU type
33 * @opp_def: opp default list for this silicon
34 * @opp_def_size: number of opp entries for this silicon
35 *
36 * Register the initial OPP table with the OPP library based on the CPU
37 * type. This is meant to be used only by SoC specific registration.
38 */
39int __init omap_init_opp_table(struct omap_opp_def *opp_def,
40 u32 opp_def_size)
41{
42 int i, r;
43
44 if (of_have_populated_dt())
45 return -EINVAL;
46
47 if (!opp_def || !opp_def_size) {
48 pr_err("%s: invalid params!\n", __func__);
49 return -EINVAL;
50 }
51
52 /*
53 * Initialize only if not already initialized even if the previous
54 * call failed, because, no reason we'd succeed again.
55 */
56 if (omap_table_init)
57 return -EEXIST;
58 omap_table_init = 1;
59
60 /* Lets now register with OPP library */
61 for (i = 0; i < opp_def_size; i++, opp_def++) {
62 struct omap_hwmod *oh;
63 struct device *dev;
64
65 if (!opp_def->hwmod_name) {
66 pr_err("%s: NULL name of omap_hwmod, failing [%d].\n",
67 __func__, i);
68 return -EINVAL;
69 }
70
71 if (!strncmp(opp_def->hwmod_name, "mpu", 3)) {
72 /*
73 * All current OMAPs share voltage rail and
74 * clock source, so CPU0 is used to represent
75 * the MPU-SS.
76 */
77 dev = get_cpu_device(0);
78 } else {
79 oh = omap_hwmod_lookup(opp_def->hwmod_name);
80 if (!oh || !oh->od) {
81 pr_debug("%s: no hwmod or odev for %s, [%d] cannot add OPPs.\n",
82 __func__, opp_def->hwmod_name, i);
83 continue;
84 }
85 dev = &oh->od->pdev->dev;
86 }
87
88 r = dev_pm_opp_add(dev, opp_def->freq, opp_def->u_volt);
89 if (r) {
90 dev_err(dev, "%s: add OPP %ld failed for %s [%d] result=%d\n",
91 __func__, opp_def->freq,
92 opp_def->hwmod_name, i, r);
93 } else {
94 if (!opp_def->default_available)
95 r = dev_pm_opp_disable(dev, opp_def->freq);
96 if (r)
97 dev_err(dev, "%s: disable %ld failed for %s [%d] result=%d\n",
98 __func__, opp_def->freq,
99 opp_def->hwmod_name, i, r);
100 }
101 }
102
103 return 0;
104}
diff --git a/arch/arm/mach-omap2/opp3xxx_data.c b/arch/arm/mach-omap2/opp3xxx_data.c
index fc67add76444..c2d459f5b0da 100644
--- a/arch/arm/mach-omap2/opp3xxx_data.c
+++ b/arch/arm/mach-omap2/opp3xxx_data.c
@@ -83,89 +83,3 @@ struct omap_volt_data omap36xx_vddcore_volt_data[] = {
83 VOLT_DATA_DEFINE(OMAP3630_VDD_CORE_OPP100_UV, OMAP3630_CONTROL_FUSE_OPP100_VDD2, 0xf9, 0x16), 83 VOLT_DATA_DEFINE(OMAP3630_VDD_CORE_OPP100_UV, OMAP3630_CONTROL_FUSE_OPP100_VDD2, 0xf9, 0x16),
84 VOLT_DATA_DEFINE(0, 0, 0, 0), 84 VOLT_DATA_DEFINE(0, 0, 0, 0),
85}; 85};
86
87/* OPP data */
88
89static struct omap_opp_def __initdata omap34xx_opp_def_list[] = {
90 /* MPU OPP1 */
91 OPP_INITIALIZER("mpu", true, 125000000, OMAP3430_VDD_MPU_OPP1_UV),
92 /* MPU OPP2 */
93 OPP_INITIALIZER("mpu", true, 250000000, OMAP3430_VDD_MPU_OPP2_UV),
94 /* MPU OPP3 */
95 OPP_INITIALIZER("mpu", true, 500000000, OMAP3430_VDD_MPU_OPP3_UV),
96 /* MPU OPP4 */
97 OPP_INITIALIZER("mpu", true, 550000000, OMAP3430_VDD_MPU_OPP4_UV),
98 /* MPU OPP5 */
99 OPP_INITIALIZER("mpu", true, 600000000, OMAP3430_VDD_MPU_OPP5_UV),
100
101 /*
102 * L3 OPP1 - 41.5 MHz is disabled because: The voltage for that OPP is
103 * almost the same than the one at 83MHz thus providing very little
104 * gain for the power point of view. In term of energy it will even
105 * increase the consumption due to the very negative performance
106 * impact that frequency will do to the MPU and the whole system in
107 * general.
108 */
109 OPP_INITIALIZER("l3_main", false, 41500000, OMAP3430_VDD_CORE_OPP1_UV),
110 /* L3 OPP2 */
111 OPP_INITIALIZER("l3_main", true, 83000000, OMAP3430_VDD_CORE_OPP2_UV),
112 /* L3 OPP3 */
113 OPP_INITIALIZER("l3_main", true, 166000000, OMAP3430_VDD_CORE_OPP3_UV),
114
115 /* DSP OPP1 */
116 OPP_INITIALIZER("iva", true, 90000000, OMAP3430_VDD_MPU_OPP1_UV),
117 /* DSP OPP2 */
118 OPP_INITIALIZER("iva", true, 180000000, OMAP3430_VDD_MPU_OPP2_UV),
119 /* DSP OPP3 */
120 OPP_INITIALIZER("iva", true, 360000000, OMAP3430_VDD_MPU_OPP3_UV),
121 /* DSP OPP4 */
122 OPP_INITIALIZER("iva", true, 400000000, OMAP3430_VDD_MPU_OPP4_UV),
123 /* DSP OPP5 */
124 OPP_INITIALIZER("iva", true, 430000000, OMAP3430_VDD_MPU_OPP5_UV),
125};
126
127static struct omap_opp_def __initdata omap36xx_opp_def_list[] = {
128 /* MPU OPP1 - OPP50 */
129 OPP_INITIALIZER("mpu", true, 300000000, OMAP3630_VDD_MPU_OPP50_UV),
130 /* MPU OPP2 - OPP100 */
131 OPP_INITIALIZER("mpu", true, 600000000, OMAP3630_VDD_MPU_OPP100_UV),
132 /* MPU OPP3 - OPP-Turbo */
133 OPP_INITIALIZER("mpu", false, 800000000, OMAP3630_VDD_MPU_OPP120_UV),
134 /* MPU OPP4 - OPP-SB */
135 OPP_INITIALIZER("mpu", false, 1000000000, OMAP3630_VDD_MPU_OPP1G_UV),
136
137 /* L3 OPP1 - OPP50 */
138 OPP_INITIALIZER("l3_main", true, 100000000, OMAP3630_VDD_CORE_OPP50_UV),
139 /* L3 OPP2 - OPP100, OPP-Turbo, OPP-SB */
140 OPP_INITIALIZER("l3_main", true, 200000000, OMAP3630_VDD_CORE_OPP100_UV),
141
142 /* DSP OPP1 - OPP50 */
143 OPP_INITIALIZER("iva", true, 260000000, OMAP3630_VDD_MPU_OPP50_UV),
144 /* DSP OPP2 - OPP100 */
145 OPP_INITIALIZER("iva", true, 520000000, OMAP3630_VDD_MPU_OPP100_UV),
146 /* DSP OPP3 - OPP-Turbo */
147 OPP_INITIALIZER("iva", false, 660000000, OMAP3630_VDD_MPU_OPP120_UV),
148 /* DSP OPP4 - OPP-SB */
149 OPP_INITIALIZER("iva", false, 800000000, OMAP3630_VDD_MPU_OPP1G_UV),
150};
151
152/**
153 * omap3_opp_init() - initialize omap3 opp table
154 */
155int __init omap3_opp_init(void)
156{
157 int r = -ENODEV;
158
159 if (!cpu_is_omap34xx())
160 return r;
161
162 if (cpu_is_omap3630())
163 r = omap_init_opp_table(omap36xx_opp_def_list,
164 ARRAY_SIZE(omap36xx_opp_def_list));
165 else
166 r = omap_init_opp_table(omap34xx_opp_def_list,
167 ARRAY_SIZE(omap34xx_opp_def_list));
168
169 return r;
170}
171omap_device_initcall(omap3_opp_init);
diff --git a/arch/arm/mach-omap2/opp4xxx_data.c b/arch/arm/mach-omap2/opp4xxx_data.c
index 1ef7a3e5ce4a..adea43ea1c60 100644
--- a/arch/arm/mach-omap2/opp4xxx_data.c
+++ b/arch/arm/mach-omap2/opp4xxx_data.c
@@ -63,29 +63,6 @@ struct omap_volt_data omap443x_vdd_core_volt_data[] = {
63 VOLT_DATA_DEFINE(0, 0, 0, 0), 63 VOLT_DATA_DEFINE(0, 0, 0, 0),
64}; 64};
65 65
66
67static struct omap_opp_def __initdata omap443x_opp_def_list[] = {
68 /* MPU OPP1 - OPP50 */
69 OPP_INITIALIZER("mpu", true, 300000000, OMAP4430_VDD_MPU_OPP50_UV),
70 /* MPU OPP2 - OPP100 */
71 OPP_INITIALIZER("mpu", true, 600000000, OMAP4430_VDD_MPU_OPP100_UV),
72 /* MPU OPP3 - OPP-Turbo */
73 OPP_INITIALIZER("mpu", true, 800000000, OMAP4430_VDD_MPU_OPPTURBO_UV),
74 /* MPU OPP4 - OPP-SB */
75 OPP_INITIALIZER("mpu", true, 1008000000, OMAP4430_VDD_MPU_OPPNITRO_UV),
76 /* L3 OPP1 - OPP50 */
77 OPP_INITIALIZER("l3_main_1", true, 100000000, OMAP4430_VDD_CORE_OPP50_UV),
78 /* L3 OPP2 - OPP100, OPP-Turbo, OPP-SB */
79 OPP_INITIALIZER("l3_main_1", true, 200000000, OMAP4430_VDD_CORE_OPP100_UV),
80 /* IVA OPP1 - OPP50 */
81 OPP_INITIALIZER("iva", true, 133000000, OMAP4430_VDD_IVA_OPP50_UV),
82 /* IVA OPP2 - OPP100 */
83 OPP_INITIALIZER("iva", true, 266100000, OMAP4430_VDD_IVA_OPP100_UV),
84 /* IVA OPP3 - OPP-Turbo */
85 OPP_INITIALIZER("iva", false, 332000000, OMAP4430_VDD_IVA_OPPTURBO_UV),
86 /* TODO: add DSP, aess, fdif, gpu */
87};
88
89#define OMAP4460_VDD_MPU_OPP50_UV 1025000 66#define OMAP4460_VDD_MPU_OPP50_UV 1025000
90#define OMAP4460_VDD_MPU_OPP100_UV 1200000 67#define OMAP4460_VDD_MPU_OPP100_UV 1200000
91#define OMAP4460_VDD_MPU_OPPTURBO_UV 1313000 68#define OMAP4460_VDD_MPU_OPPTURBO_UV 1313000
@@ -122,59 +99,3 @@ struct omap_volt_data omap446x_vdd_core_volt_data[] = {
122 VOLT_DATA_DEFINE(OMAP4460_VDD_CORE_OPP100_OV_UV, OMAP44XX_CONTROL_FUSE_CORE_OPP100OV, 0xf9, 0x16), 99 VOLT_DATA_DEFINE(OMAP4460_VDD_CORE_OPP100_OV_UV, OMAP44XX_CONTROL_FUSE_CORE_OPP100OV, 0xf9, 0x16),
123 VOLT_DATA_DEFINE(0, 0, 0, 0), 100 VOLT_DATA_DEFINE(0, 0, 0, 0),
124}; 101};
125
126static struct omap_opp_def __initdata omap446x_opp_def_list[] = {
127 /* MPU OPP1 - OPP50 */
128 OPP_INITIALIZER("mpu", true, 350000000, OMAP4460_VDD_MPU_OPP50_UV),
129 /* MPU OPP2 - OPP100 */
130 OPP_INITIALIZER("mpu", true, 700000000, OMAP4460_VDD_MPU_OPP100_UV),
131 /* MPU OPP3 - OPP-Turbo */
132 OPP_INITIALIZER("mpu", true, 920000000, OMAP4460_VDD_MPU_OPPTURBO_UV),
133 /*
134 * MPU OPP4 - OPP-Nitro + Disabled as the reference schematics
135 * recommends TPS623631 - confirm and enable the opp in board file
136 * XXX: May be we should enable these based on mpu capability and
137 * Exception board files disable it...
138 */
139 OPP_INITIALIZER("mpu", false, 1200000000, OMAP4460_VDD_MPU_OPPNITRO_UV),
140 /* MPU OPP4 - OPP-Nitro SpeedBin */
141 OPP_INITIALIZER("mpu", false, 1500000000, OMAP4460_VDD_MPU_OPPNITRO_UV),
142 /* L3 OPP1 - OPP50 */
143 OPP_INITIALIZER("l3_main_1", true, 100000000, OMAP4460_VDD_CORE_OPP50_UV),
144 /* L3 OPP2 - OPP100 */
145 OPP_INITIALIZER("l3_main_1", true, 200000000, OMAP4460_VDD_CORE_OPP100_UV),
146 /* IVA OPP1 - OPP50 */
147 OPP_INITIALIZER("iva", true, 133000000, OMAP4460_VDD_IVA_OPP50_UV),
148 /* IVA OPP2 - OPP100 */
149 OPP_INITIALIZER("iva", true, 266100000, OMAP4460_VDD_IVA_OPP100_UV),
150 /*
151 * IVA OPP3 - OPP-Turbo + Disabled as the reference schematics
152 * recommends Phoenix VCORE2 which can supply only 600mA - so the ones
153 * above this OPP frequency, even though OMAP is capable, should be
154 * enabled by board file which is sure of the chip power capability
155 */
156 OPP_INITIALIZER("iva", false, 332000000, OMAP4460_VDD_IVA_OPPTURBO_UV),
157 /* IVA OPP4 - OPP-Nitro */
158 OPP_INITIALIZER("iva", false, 430000000, OMAP4460_VDD_IVA_OPPNITRO_UV),
159 /* IVA OPP5 - OPP-Nitro SpeedBin*/
160 OPP_INITIALIZER("iva", false, 500000000, OMAP4460_VDD_IVA_OPPNITRO_UV),
161
162 /* TODO: add DSP, aess, fdif, gpu */
163};
164
165/**
166 * omap4_opp_init() - initialize omap4 opp table
167 */
168int __init omap4_opp_init(void)
169{
170 int r = -ENODEV;
171
172 if (cpu_is_omap443x())
173 r = omap_init_opp_table(omap443x_opp_def_list,
174 ARRAY_SIZE(omap443x_opp_def_list));
175 else if (cpu_is_omap446x())
176 r = omap_init_opp_table(omap446x_opp_def_list,
177 ARRAY_SIZE(omap446x_opp_def_list));
178 return r;
179}
180omap_device_initcall(omap4_opp_init);
diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c
index 63027e60cc20..366158a54fcd 100644
--- a/arch/arm/mach-omap2/pm.c
+++ b/arch/arm/mach-omap2/pm.c
@@ -71,7 +71,7 @@ void omap_pm_get_oscillator(u32 *tstart, u32 *tshut)
71} 71}
72#endif 72#endif
73 73
74int __init omap_pm_clkdms_setup(struct clockdomain *clkdm, void *unused) 74int omap_pm_clkdms_setup(struct clockdomain *clkdm, void *unused)
75{ 75{
76 clkdm_allow_idle(clkdm); 76 clkdm_allow_idle(clkdm);
77 return 0; 77 return 0;
diff --git a/arch/arm/mach-omap2/pmu.c b/arch/arm/mach-omap2/pmu.c
deleted file mode 100644
index d2adfebd3b3f..000000000000
--- a/arch/arm/mach-omap2/pmu.c
+++ /dev/null
@@ -1,97 +0,0 @@
1/*
2 * OMAP2 ARM Performance Monitoring Unit (PMU) Support
3 *
4 * Copyright (C) 2012 Texas Instruments, Inc.
5 *
6 * Contacts:
7 * Jon Hunter <jon-hunter@ti.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 */
14#include <linux/of.h>
15
16#include <asm/system_info.h>
17
18#include "soc.h"
19#include "omap_hwmod.h"
20#include "omap_device.h"
21
22static char *omap2_pmu_oh_names[] = {"mpu"};
23static char *omap3_pmu_oh_names[] = {"mpu", "debugss"};
24static char *omap4430_pmu_oh_names[] = {"l3_main_3", "l3_instr", "debugss"};
25static struct platform_device *omap_pmu_dev;
26
27/**
28 * omap2_init_pmu - creates and registers PMU platform device
29 * @oh_num: Number of OMAP HWMODs required to create PMU device
30 * @oh_names: Array of OMAP HWMODS names required to create PMU device
31 *
32 * Uses OMAP HWMOD framework to create and register an ARM PMU device
33 * from a list of HWMOD names passed. Currently supports OMAP2, OMAP3
34 * and OMAP4 devices.
35 */
36static int __init omap2_init_pmu(unsigned oh_num, char *oh_names[])
37{
38 int i;
39 struct omap_hwmod *oh[3];
40 char *dev_name = cpu_architecture() == CPU_ARCH_ARMv6 ?
41 "armv6-pmu" : "armv7-pmu";
42
43 if ((!oh_num) || (oh_num > 3))
44 return -EINVAL;
45
46 for (i = 0; i < oh_num; i++) {
47 oh[i] = omap_hwmod_lookup(oh_names[i]);
48 if (!oh[i]) {
49 pr_err("Could not look up %s hwmod\n", oh_names[i]);
50 return -ENODEV;
51 }
52 }
53
54 omap_pmu_dev = omap_device_build_ss(dev_name, -1, oh, oh_num, NULL, 0);
55 WARN(IS_ERR(omap_pmu_dev), "Can't build omap_device for %s.\n",
56 dev_name);
57
58 return PTR_ERR_OR_ZERO(omap_pmu_dev);
59}
60
61static int __init omap_init_pmu(void)
62{
63 unsigned oh_num;
64 char **oh_names;
65
66 /* XXX Remove this check when the CTI driver is available */
67 if (cpu_is_omap443x()) {
68 pr_info("ARM PMU: not yet supported on OMAP4430 due to missing CTI driver\n");
69 return 0;
70 }
71
72 if (of_have_populated_dt())
73 return 0;
74
75 /*
76 * To create an ARM-PMU device the following HWMODs
77 * are required for the various OMAP2+ devices.
78 *
79 * OMAP24xx: mpu
80 * OMAP3xxx: mpu, debugss
81 * OMAP4430: l3_main_3, l3_instr, debugss
82 * OMAP4460/70: mpu, debugss
83 */
84 if (cpu_is_omap443x()) {
85 oh_num = ARRAY_SIZE(omap4430_pmu_oh_names);
86 oh_names = omap4430_pmu_oh_names;
87 } else if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
88 oh_num = ARRAY_SIZE(omap3_pmu_oh_names);
89 oh_names = omap3_pmu_oh_names;
90 } else {
91 oh_num = ARRAY_SIZE(omap2_pmu_oh_names);
92 oh_names = omap2_pmu_oh_names;
93 }
94
95 return omap2_init_pmu(oh_num, oh_names);
96}
97omap_subsys_initcall(omap_init_pmu);
diff --git a/arch/arm/mach-omap2/prcm-common.h b/arch/arm/mach-omap2/prcm-common.h
index c8f590b7c32d..ee7041d523cf 100644
--- a/arch/arm/mach-omap2/prcm-common.h
+++ b/arch/arm/mach-omap2/prcm-common.h
@@ -526,10 +526,16 @@ struct omap_prcm_irq_setup {
526 .priority = _priority \ 526 .priority = _priority \
527 } 527 }
528 528
529struct omap_domain_base {
530 u32 pa;
531 void __iomem *va;
532};
533
529/** 534/**
530 * struct omap_prcm_init_data - PRCM driver init data 535 * struct omap_prcm_init_data - PRCM driver init data
531 * @index: clock memory mapping index to be used 536 * @index: clock memory mapping index to be used
532 * @mem: IO mem pointer for this module 537 * @mem: IO mem pointer for this module
538 * @phys: IO mem physical base address for this module
533 * @offset: module base address offset from the IO base 539 * @offset: module base address offset from the IO base
534 * @flags: PRCM module init flags 540 * @flags: PRCM module init flags
535 * @device_inst_offset: device instance offset within the module address space 541 * @device_inst_offset: device instance offset within the module address space
@@ -539,6 +545,7 @@ struct omap_prcm_irq_setup {
539struct omap_prcm_init_data { 545struct omap_prcm_init_data {
540 int index; 546 int index;
541 void __iomem *mem; 547 void __iomem *mem;
548 u32 phys;
542 s16 offset; 549 s16 offset;
543 u16 flags; 550 u16 flags;
544 s32 device_inst_offset; 551 s32 device_inst_offset;
diff --git a/arch/arm/mach-omap2/prcm_mpu44xx.c b/arch/arm/mach-omap2/prcm_mpu44xx.c
index cdbee6326d29..9c782f5c3f94 100644
--- a/arch/arm/mach-omap2/prcm_mpu44xx.c
+++ b/arch/arm/mach-omap2/prcm_mpu44xx.c
@@ -24,7 +24,7 @@
24 * prcm_mpu_base: the virtual address of the start of the PRCM_MPU IP 24 * prcm_mpu_base: the virtual address of the start of the PRCM_MPU IP
25 * block registers 25 * block registers
26 */ 26 */
27void __iomem *prcm_mpu_base; 27struct omap_domain_base prcm_mpu_base;
28 28
29/* PRCM_MPU low-level functions */ 29/* PRCM_MPU low-level functions */
30 30
@@ -58,5 +58,5 @@ u32 omap4_prcm_mpu_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 reg)
58 */ 58 */
59void __init omap2_set_globals_prcm_mpu(void __iomem *prcm_mpu) 59void __init omap2_set_globals_prcm_mpu(void __iomem *prcm_mpu)
60{ 60{
61 prcm_mpu_base = prcm_mpu; 61 prcm_mpu_base.va = prcm_mpu;
62} 62}
diff --git a/arch/arm/mach-omap2/prcm_mpu_44xx_54xx.h b/arch/arm/mach-omap2/prcm_mpu_44xx_54xx.h
index ca149e70bed0..f565f7f73175 100644
--- a/arch/arm/mach-omap2/prcm_mpu_44xx_54xx.h
+++ b/arch/arm/mach-omap2/prcm_mpu_44xx_54xx.h
@@ -24,7 +24,9 @@
24#define __ARCH_ARM_MACH_OMAP2_PRCM_MPU_44XX_54XX_H 24#define __ARCH_ARM_MACH_OMAP2_PRCM_MPU_44XX_54XX_H
25 25
26#ifndef __ASSEMBLER__ 26#ifndef __ASSEMBLER__
27extern void __iomem *prcm_mpu_base; 27#include "prcm-common.h"
28
29extern struct omap_domain_base prcm_mpu_base;
28 30
29extern u32 omap4_prcm_mpu_read_inst_reg(s16 inst, u16 idx); 31extern u32 omap4_prcm_mpu_read_inst_reg(s16 inst, u16 idx);
30extern void omap4_prcm_mpu_write_inst_reg(u32 val, s16 inst, u16 idx); 32extern void omap4_prcm_mpu_write_inst_reg(u32 val, s16 inst, u16 idx);
diff --git a/arch/arm/mach-omap2/prm.h b/arch/arm/mach-omap2/prm.h
index 233bc84fbc0e..94dc3565add8 100644
--- a/arch/arm/mach-omap2/prm.h
+++ b/arch/arm/mach-omap2/prm.h
@@ -16,7 +16,7 @@
16#include "prcm-common.h" 16#include "prcm-common.h"
17 17
18# ifndef __ASSEMBLER__ 18# ifndef __ASSEMBLER__
19extern void __iomem *prm_base; 19extern struct omap_domain_base prm_base;
20extern u16 prm_features; 20extern u16 prm_features;
21extern void omap2_set_globals_prm(void __iomem *prm); 21extern void omap2_set_globals_prm(void __iomem *prm);
22int omap_prcm_init(void); 22int omap_prcm_init(void);
diff --git a/arch/arm/mach-omap2/prm2xxx_3xxx.h b/arch/arm/mach-omap2/prm2xxx_3xxx.h
index f57e29b0e041..6775e10883fb 100644
--- a/arch/arm/mach-omap2/prm2xxx_3xxx.h
+++ b/arch/arm/mach-omap2/prm2xxx_3xxx.h
@@ -55,12 +55,12 @@
55/* Power/reset management domain register get/set */ 55/* Power/reset management domain register get/set */
56static inline u32 omap2_prm_read_mod_reg(s16 module, u16 idx) 56static inline u32 omap2_prm_read_mod_reg(s16 module, u16 idx)
57{ 57{
58 return readl_relaxed(prm_base + module + idx); 58 return readl_relaxed(prm_base.va + module + idx);
59} 59}
60 60
61static inline void omap2_prm_write_mod_reg(u32 val, s16 module, u16 idx) 61static inline void omap2_prm_write_mod_reg(u32 val, s16 module, u16 idx)
62{ 62{
63 writel_relaxed(val, prm_base + module + idx); 63 writel_relaxed(val, prm_base.va + module + idx);
64} 64}
65 65
66/* Read-modify-write a register in a PRM module. Caller must lock */ 66/* Read-modify-write a register in a PRM module. Caller must lock */
diff --git a/arch/arm/mach-omap2/prm33xx.c b/arch/arm/mach-omap2/prm33xx.c
index dcb5001d77da..d2c5bcabdbeb 100644
--- a/arch/arm/mach-omap2/prm33xx.c
+++ b/arch/arm/mach-omap2/prm33xx.c
@@ -30,13 +30,13 @@
30/* Read a register in a PRM instance */ 30/* Read a register in a PRM instance */
31static u32 am33xx_prm_read_reg(s16 inst, u16 idx) 31static u32 am33xx_prm_read_reg(s16 inst, u16 idx)
32{ 32{
33 return readl_relaxed(prm_base + inst + idx); 33 return readl_relaxed(prm_base.va + inst + idx);
34} 34}
35 35
36/* Write into a register in a PRM instance */ 36/* Write into a register in a PRM instance */
37static void am33xx_prm_write_reg(u32 val, s16 inst, u16 idx) 37static void am33xx_prm_write_reg(u32 val, s16 inst, u16 idx)
38{ 38{
39 writel_relaxed(val, prm_base + inst + idx); 39 writel_relaxed(val, prm_base.va + inst + idx);
40} 40}
41 41
42/* Read-modify-write a register in PRM. Caller must lock */ 42/* Read-modify-write a register in PRM. Caller must lock */
diff --git a/arch/arm/mach-omap2/prm3xxx.c b/arch/arm/mach-omap2/prm3xxx.c
index 718981bb80cd..382e236fbfd9 100644
--- a/arch/arm/mach-omap2/prm3xxx.c
+++ b/arch/arm/mach-omap2/prm3xxx.c
@@ -676,7 +676,7 @@ static struct prm_ll_data omap3xxx_prm_ll_data = {
676int __init omap3xxx_prm_init(const struct omap_prcm_init_data *data) 676int __init omap3xxx_prm_init(const struct omap_prcm_init_data *data)
677{ 677{
678 omap2_clk_legacy_provider_init(TI_CLKM_PRM, 678 omap2_clk_legacy_provider_init(TI_CLKM_PRM,
679 prm_base + OMAP3430_IVA2_MOD); 679 prm_base.va + OMAP3430_IVA2_MOD);
680 if (omap3_has_io_wakeup()) 680 if (omap3_has_io_wakeup())
681 prm_features |= PRM_HAS_IO_WAKEUP; 681 prm_features |= PRM_HAS_IO_WAKEUP;
682 682
@@ -690,6 +690,8 @@ static const struct of_device_id omap3_prm_dt_match_table[] = {
690 690
691static int omap3xxx_prm_late_init(void) 691static int omap3xxx_prm_late_init(void)
692{ 692{
693 struct device_node *np;
694 int irq_num;
693 int ret; 695 int ret;
694 696
695 if (!(prm_features & PRM_HAS_IO_WAKEUP)) 697 if (!(prm_features & PRM_HAS_IO_WAKEUP))
@@ -702,16 +704,11 @@ static int omap3xxx_prm_late_init(void)
702 omap3_prcm_irq_setup.reconfigure_io_chain = 704 omap3_prcm_irq_setup.reconfigure_io_chain =
703 omap3430_pre_es3_1_reconfigure_io_chain; 705 omap3430_pre_es3_1_reconfigure_io_chain;
704 706
705 if (of_have_populated_dt()) { 707 np = of_find_matching_node(NULL, omap3_prm_dt_match_table);
706 struct device_node *np; 708 if (np) {
707 int irq_num; 709 irq_num = of_irq_get(np, 0);
708 710 if (irq_num >= 0)
709 np = of_find_matching_node(NULL, omap3_prm_dt_match_table); 711 omap3_prcm_irq_setup.irq = irq_num;
710 if (np) {
711 irq_num = of_irq_get(np, 0);
712 if (irq_num >= 0)
713 omap3_prcm_irq_setup.irq = irq_num;
714 }
715 } 712 }
716 713
717 omap3xxx_prm_enable_io_wakeup(); 714 omap3xxx_prm_enable_io_wakeup();
diff --git a/arch/arm/mach-omap2/prm44xx.c b/arch/arm/mach-omap2/prm44xx.c
index 30768003f854..87e86a4a9ead 100644
--- a/arch/arm/mach-omap2/prm44xx.c
+++ b/arch/arm/mach-omap2/prm44xx.c
@@ -91,13 +91,13 @@ static struct prm_reset_src_map omap44xx_prm_reset_src_map[] = {
91/* Read a register in a CM/PRM instance in the PRM module */ 91/* Read a register in a CM/PRM instance in the PRM module */
92static u32 omap4_prm_read_inst_reg(s16 inst, u16 reg) 92static u32 omap4_prm_read_inst_reg(s16 inst, u16 reg)
93{ 93{
94 return readl_relaxed(prm_base + inst + reg); 94 return readl_relaxed(prm_base.va + inst + reg);
95} 95}
96 96
97/* Write into a register in a CM/PRM instance in the PRM module */ 97/* Write into a register in a CM/PRM instance in the PRM module */
98static void omap4_prm_write_inst_reg(u32 val, s16 inst, u16 reg) 98static void omap4_prm_write_inst_reg(u32 val, s16 inst, u16 reg)
99{ 99{
100 writel_relaxed(val, prm_base + inst + reg); 100 writel_relaxed(val, prm_base.va + inst + reg);
101} 101}
102 102
103/* Read-modify-write a register in a PRM module. Caller must lock */ 103/* Read-modify-write a register in a PRM module. Caller must lock */
@@ -337,27 +337,6 @@ static void omap44xx_prm_reconfigure_io_chain(void)
337} 337}
338 338
339/** 339/**
340 * omap44xx_prm_enable_io_wakeup - enable wakeup events from I/O wakeup latches
341 *
342 * Activates the I/O wakeup event latches and allows events logged by
343 * those latches to signal a wakeup event to the PRCM. For I/O wakeups
344 * to occur, WAKEUPENABLE bits must be set in the pad mux registers, and
345 * omap44xx_prm_reconfigure_io_chain() must be called. No return value.
346 */
347static void __init omap44xx_prm_enable_io_wakeup(void)
348{
349 s32 inst = omap4_prmst_get_prm_dev_inst();
350
351 if (inst == PRM_INSTANCE_UNKNOWN)
352 return;
353
354 omap4_prm_rmw_inst_reg_bits(OMAP4430_GLOBAL_WUEN_MASK,
355 OMAP4430_GLOBAL_WUEN_MASK,
356 inst,
357 omap4_prcm_irq_setup.pm_ctrl);
358}
359
360/**
361 * omap44xx_prm_read_reset_sources - return the last SoC reset source 340 * omap44xx_prm_read_reset_sources - return the last SoC reset source
362 * 341 *
363 * Return a u32 representing the last reset sources of the SoC. The 342 * Return a u32 representing the last reset sources of the SoC. The
@@ -689,8 +668,6 @@ struct pwrdm_ops omap4_pwrdm_operations = {
689 .pwrdm_has_voltdm = omap4_check_vcvp, 668 .pwrdm_has_voltdm = omap4_check_vcvp,
690}; 669};
691 670
692static int omap44xx_prm_late_init(void);
693
694/* 671/*
695 * XXX document 672 * XXX document
696 */ 673 */
@@ -698,7 +675,6 @@ static struct prm_ll_data omap44xx_prm_ll_data = {
698 .read_reset_sources = &omap44xx_prm_read_reset_sources, 675 .read_reset_sources = &omap44xx_prm_read_reset_sources,
699 .was_any_context_lost_old = &omap44xx_prm_was_any_context_lost_old, 676 .was_any_context_lost_old = &omap44xx_prm_was_any_context_lost_old,
700 .clear_context_loss_flags_old = &omap44xx_prm_clear_context_loss_flags_old, 677 .clear_context_loss_flags_old = &omap44xx_prm_clear_context_loss_flags_old,
701 .late_init = &omap44xx_prm_late_init,
702 .assert_hardreset = omap4_prminst_assert_hardreset, 678 .assert_hardreset = omap4_prminst_assert_hardreset,
703 .deassert_hardreset = omap4_prminst_deassert_hardreset, 679 .deassert_hardreset = omap4_prminst_deassert_hardreset,
704 .is_hardreset_asserted = omap4_prminst_is_hardreset_asserted, 680 .is_hardreset_asserted = omap4_prminst_is_hardreset_asserted,
@@ -735,41 +711,6 @@ int __init omap44xx_prm_init(const struct omap_prcm_init_data *data)
735 return prm_register(&omap44xx_prm_ll_data); 711 return prm_register(&omap44xx_prm_ll_data);
736} 712}
737 713
738static int omap44xx_prm_late_init(void)
739{
740 int irq_num;
741
742 if (!(prm_features & PRM_HAS_IO_WAKEUP))
743 return 0;
744
745 /* OMAP4+ is DT only now */
746 if (!of_have_populated_dt())
747 return 0;
748
749 irq_num = of_irq_get(prm_init_data->np, 0);
750 /*
751 * Already have OMAP4 IRQ num. For all other platforms, we need
752 * IRQ numbers from DT
753 */
754 if (irq_num < 0 && !(prm_init_data->flags & PRM_IRQ_DEFAULT)) {
755 if (irq_num == -EPROBE_DEFER)
756 return irq_num;
757
758 /* Have nothing to do */
759 return 0;
760 }
761
762 /* Once OMAP4 DT is filled as well */
763 if (irq_num >= 0) {
764 omap4_prcm_irq_setup.irq = irq_num;
765 omap4_prcm_irq_setup.xlate_irq = NULL;
766 }
767
768 omap44xx_prm_enable_io_wakeup();
769
770 return omap_prcm_register_chain_handler(&omap4_prcm_irq_setup);
771}
772
773static void __exit omap44xx_prm_exit(void) 714static void __exit omap44xx_prm_exit(void)
774{ 715{
775 prm_unregister(&omap44xx_prm_ll_data); 716 prm_unregister(&omap44xx_prm_ll_data);
diff --git a/arch/arm/mach-omap2/prm_common.c b/arch/arm/mach-omap2/prm_common.c
index dc11841ca334..09180a59b1c9 100644
--- a/arch/arm/mach-omap2/prm_common.c
+++ b/arch/arm/mach-omap2/prm_common.c
@@ -66,7 +66,7 @@ static struct irq_chip_generic **prcm_irq_chips;
66static struct omap_prcm_irq_setup *prcm_irq_setup; 66static struct omap_prcm_irq_setup *prcm_irq_setup;
67 67
68/* prm_base: base virtual address of the PRM IP block */ 68/* prm_base: base virtual address of the PRM IP block */
69void __iomem *prm_base; 69struct omap_domain_base prm_base;
70 70
71u16 prm_features; 71u16 prm_features;
72 72
@@ -267,10 +267,9 @@ int omap_prcm_register_chain_handler(struct omap_prcm_irq_setup *irq_setup)
267{ 267{
268 int nr_regs; 268 int nr_regs;
269 u32 mask[OMAP_PRCM_MAX_NR_PENDING_REG]; 269 u32 mask[OMAP_PRCM_MAX_NR_PENDING_REG];
270 int offset, i; 270 int offset, i, irq;
271 struct irq_chip_generic *gc; 271 struct irq_chip_generic *gc;
272 struct irq_chip_type *ct; 272 struct irq_chip_type *ct;
273 unsigned int irq;
274 273
275 if (!irq_setup) 274 if (!irq_setup)
276 return -EINVAL; 275 return -EINVAL;
@@ -325,7 +324,7 @@ int omap_prcm_register_chain_handler(struct omap_prcm_irq_setup *irq_setup)
325 324
326 for (i = 0; i < irq_setup->nr_regs; i++) { 325 for (i = 0; i < irq_setup->nr_regs; i++) {
327 gc = irq_alloc_generic_chip("PRCM", 1, 326 gc = irq_alloc_generic_chip("PRCM", 1,
328 irq_setup->base_irq + i * 32, prm_base, 327 irq_setup->base_irq + i * 32, prm_base.va,
329 handle_level_irq); 328 handle_level_irq);
330 329
331 if (!gc) { 330 if (!gc) {
@@ -344,10 +343,8 @@ int omap_prcm_register_chain_handler(struct omap_prcm_irq_setup *irq_setup)
344 prcm_irq_chips[i] = gc; 343 prcm_irq_chips[i] = gc;
345 } 344 }
346 345
347 if (of_have_populated_dt()) { 346 irq = omap_prcm_event_to_irq("io");
348 int irq = omap_prcm_event_to_irq("io"); 347 omap_pcs_legacy_init(irq, irq_setup->reconfigure_io_chain);
349 omap_pcs_legacy_init(irq, irq_setup->reconfigure_io_chain);
350 }
351 348
352 return 0; 349 return 0;
353 350
@@ -364,7 +361,7 @@ err:
364 */ 361 */
365void __init omap2_set_globals_prm(void __iomem *prm) 362void __init omap2_set_globals_prm(void __iomem *prm)
366{ 363{
367 prm_base = prm; 364 prm_base.va = prm;
368} 365}
369 366
370/** 367/**
@@ -755,19 +752,22 @@ int __init omap2_prm_base_init(void)
755 struct device_node *np; 752 struct device_node *np;
756 const struct of_device_id *match; 753 const struct of_device_id *match;
757 struct omap_prcm_init_data *data; 754 struct omap_prcm_init_data *data;
758 void __iomem *mem; 755 struct resource res;
756 int ret;
759 757
760 for_each_matching_node_and_match(np, omap_prcm_dt_match_table, &match) { 758 for_each_matching_node_and_match(np, omap_prcm_dt_match_table, &match) {
761 data = (struct omap_prcm_init_data *)match->data; 759 data = (struct omap_prcm_init_data *)match->data;
762 760
763 mem = of_iomap(np, 0); 761 ret = of_address_to_resource(np, 0, &res);
764 if (!mem) 762 if (ret)
765 return -ENOMEM; 763 return ret;
766 764
767 if (data->index == TI_CLKM_PRM) 765 data->mem = ioremap(res.start, resource_size(&res));
768 prm_base = mem + data->offset;
769 766
770 data->mem = mem; 767 if (data->index == TI_CLKM_PRM) {
768 prm_base.va = data->mem + data->offset;
769 prm_base.pa = res.start + data->offset;
770 }
771 771
772 data->np = np; 772 data->np = np;
773 773
diff --git a/arch/arm/mach-omap2/prminst44xx.c b/arch/arm/mach-omap2/prminst44xx.c
index d0b15dbafa2e..48b8127b4e99 100644
--- a/arch/arm/mach-omap2/prminst44xx.c
+++ b/arch/arm/mach-omap2/prminst44xx.c
@@ -29,7 +29,7 @@
29#include "prcm_mpu44xx.h" 29#include "prcm_mpu44xx.h"
30#include "soc.h" 30#include "soc.h"
31 31
32static void __iomem *_prm_bases[OMAP4_MAX_PRCM_PARTITIONS]; 32static struct omap_domain_base _prm_bases[OMAP4_MAX_PRCM_PARTITIONS];
33 33
34static s32 prm_dev_inst = PRM_INSTANCE_UNKNOWN; 34static s32 prm_dev_inst = PRM_INSTANCE_UNKNOWN;
35 35
@@ -41,8 +41,10 @@ static s32 prm_dev_inst = PRM_INSTANCE_UNKNOWN;
41 */ 41 */
42void omap_prm_base_init(void) 42void omap_prm_base_init(void)
43{ 43{
44 _prm_bases[OMAP4430_PRM_PARTITION] = prm_base; 44 memcpy(&_prm_bases[OMAP4430_PRM_PARTITION], &prm_base,
45 _prm_bases[OMAP4430_PRCM_MPU_PARTITION] = prcm_mpu_base; 45 sizeof(prm_base));
46 memcpy(&_prm_bases[OMAP4430_PRCM_MPU_PARTITION], &prcm_mpu_base,
47 sizeof(prcm_mpu_base));
46} 48}
47 49
48s32 omap4_prmst_get_prm_dev_inst(void) 50s32 omap4_prmst_get_prm_dev_inst(void)
@@ -60,8 +62,8 @@ u32 omap4_prminst_read_inst_reg(u8 part, s16 inst, u16 idx)
60{ 62{
61 BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS || 63 BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS ||
62 part == OMAP4430_INVALID_PRCM_PARTITION || 64 part == OMAP4430_INVALID_PRCM_PARTITION ||
63 !_prm_bases[part]); 65 !_prm_bases[part].va);
64 return readl_relaxed(_prm_bases[part] + inst + idx); 66 return readl_relaxed(_prm_bases[part].va + inst + idx);
65} 67}
66 68
67/* Write into a register in a PRM instance */ 69/* Write into a register in a PRM instance */
@@ -69,8 +71,8 @@ void omap4_prminst_write_inst_reg(u32 val, u8 part, s16 inst, u16 idx)
69{ 71{
70 BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS || 72 BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS ||
71 part == OMAP4430_INVALID_PRCM_PARTITION || 73 part == OMAP4430_INVALID_PRCM_PARTITION ||
72 !_prm_bases[part]); 74 !_prm_bases[part].va);
73 writel_relaxed(val, _prm_bases[part] + inst + idx); 75 writel_relaxed(val, _prm_bases[part].va + inst + idx);
74} 76}
75 77
76/* Read-modify-write a register in PRM. Caller must lock */ 78/* Read-modify-write a register in PRM. Caller must lock */
diff --git a/arch/arm/mach-omap2/sr_device.c b/arch/arm/mach-omap2/sr_device.c
index d7cff2632d1e..eef6935e0403 100644
--- a/arch/arm/mach-omap2/sr_device.c
+++ b/arch/arm/mach-omap2/sr_device.c
@@ -44,13 +44,9 @@ static void __init sr_set_nvalues(struct omap_volt_data *volt_data,
44 while (volt_data[count].volt_nominal) 44 while (volt_data[count].volt_nominal)
45 count++; 45 count++;
46 46
47 nvalue_table = kzalloc(sizeof(struct omap_sr_nvalue_table)*count, 47 nvalue_table = kcalloc(count, sizeof(*nvalue_table), GFP_KERNEL);
48 GFP_KERNEL); 48 if (!nvalue_table)
49
50 if (!nvalue_table) {
51 pr_err("OMAP: SmartReflex: cannot allocate memory for n-value table\n");
52 return; 49 return;
53 }
54 50
55 for (i = 0, j = 0; i < count; i++) { 51 for (i = 0, j = 0; i < count; i++) {
56 u32 v; 52 u32 v;
@@ -102,12 +98,9 @@ static int __init sr_dev_init(struct omap_hwmod *oh, void *user)
102 char *name = "smartreflex"; 98 char *name = "smartreflex";
103 static int i; 99 static int i;
104 100
105 sr_data = kzalloc(sizeof(struct omap_sr_data), GFP_KERNEL); 101 sr_data = kzalloc(sizeof(*sr_data), GFP_KERNEL);
106 if (!sr_data) { 102 if (!sr_data)
107 pr_err("%s: Unable to allocate memory for %s sr_data\n",
108 __func__, oh->name);
109 return -ENOMEM; 103 return -ENOMEM;
110 }
111 104
112 sr_dev_attr = (struct omap_smartreflex_dev_attr *)oh->dev_attr; 105 sr_dev_attr = (struct omap_smartreflex_dev_attr *)oh->dev_attr;
113 if (!sr_dev_attr || !sr_dev_attr->sensor_voltdm_name) { 106 if (!sr_dev_attr || !sr_dev_attr->sensor_voltdm_name) {
diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
index 07dd692c4737..6a861c0ac343 100644
--- a/arch/arm/mach-omap2/timer.c
+++ b/arch/arm/mach-omap2/timer.c
@@ -68,6 +68,9 @@
68static struct omap_dm_timer clkev; 68static struct omap_dm_timer clkev;
69static struct clock_event_device clockevent_gpt; 69static struct clock_event_device clockevent_gpt;
70 70
71/* Clockevent hwmod for am335x and am437x suspend */
72static struct omap_hwmod *clockevent_gpt_hwmod;
73
71#ifdef CONFIG_SOC_HAS_REALTIME_COUNTER 74#ifdef CONFIG_SOC_HAS_REALTIME_COUNTER
72static unsigned long arch_timer_freq; 75static unsigned long arch_timer_freq;
73 76
@@ -125,6 +128,23 @@ static int omap2_gp_timer_set_periodic(struct clock_event_device *evt)
125 return 0; 128 return 0;
126} 129}
127 130
131static void omap_clkevt_idle(struct clock_event_device *unused)
132{
133 if (!clockevent_gpt_hwmod)
134 return;
135
136 omap_hwmod_idle(clockevent_gpt_hwmod);
137}
138
139static void omap_clkevt_unidle(struct clock_event_device *unused)
140{
141 if (!clockevent_gpt_hwmod)
142 return;
143
144 omap_hwmod_enable(clockevent_gpt_hwmod);
145 __omap_dm_timer_int_enable(&clkev, OMAP_TIMER_INT_OVERFLOW);
146}
147
128static struct clock_event_device clockevent_gpt = { 148static struct clock_event_device clockevent_gpt = {
129 .features = CLOCK_EVT_FEAT_PERIODIC | 149 .features = CLOCK_EVT_FEAT_PERIODIC |
130 CLOCK_EVT_FEAT_ONESHOT, 150 CLOCK_EVT_FEAT_ONESHOT,
@@ -232,37 +252,29 @@ static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer,
232 const char **timer_name, 252 const char **timer_name,
233 int posted) 253 int posted)
234{ 254{
235 char name[10]; /* 10 = sizeof("gptXX_Xck0") */
236 const char *oh_name = NULL; 255 const char *oh_name = NULL;
237 struct device_node *np; 256 struct device_node *np;
238 struct omap_hwmod *oh; 257 struct omap_hwmod *oh;
239 struct resource irq, mem;
240 struct clk *src; 258 struct clk *src;
241 int r = 0; 259 int r = 0;
242 260
243 if (of_have_populated_dt()) { 261 np = omap_get_timer_dt(omap_timer_match, property);
244 np = omap_get_timer_dt(omap_timer_match, property); 262 if (!np)
245 if (!np) 263 return -ENODEV;
246 return -ENODEV;
247 264
248 of_property_read_string_index(np, "ti,hwmods", 0, &oh_name); 265 of_property_read_string_index(np, "ti,hwmods", 0, &oh_name);
249 if (!oh_name) 266 if (!oh_name)
250 return -ENODEV; 267 return -ENODEV;
251 268
252 timer->irq = irq_of_parse_and_map(np, 0); 269 timer->irq = irq_of_parse_and_map(np, 0);
253 if (!timer->irq) 270 if (!timer->irq)
254 return -ENXIO; 271 return -ENXIO;
255 272
256 timer->io_base = of_iomap(np, 0); 273 timer->io_base = of_iomap(np, 0);
257 274
258 of_node_put(np); 275 timer->fclk = of_clk_get_by_name(np, "fck");
259 } else {
260 if (omap_dm_timer_reserve_systimer(timer->id))
261 return -ENODEV;
262 276
263 sprintf(name, "timer%d", timer->id); 277 of_node_put(np);
264 oh_name = name;
265 }
266 278
267 oh = omap_hwmod_lookup(oh_name); 279 oh = omap_hwmod_lookup(oh_name);
268 if (!oh) 280 if (!oh)
@@ -270,29 +282,14 @@ static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer,
270 282
271 *timer_name = oh->name; 283 *timer_name = oh->name;
272 284
273 if (!of_have_populated_dt()) {
274 r = omap_hwmod_get_resource_byname(oh, IORESOURCE_IRQ, NULL,
275 &irq);
276 if (r)
277 return -ENXIO;
278 timer->irq = irq.start;
279
280 r = omap_hwmod_get_resource_byname(oh, IORESOURCE_MEM, NULL,
281 &mem);
282 if (r)
283 return -ENXIO;
284
285 /* Static mapping, never released */
286 timer->io_base = ioremap(mem.start, mem.end - mem.start);
287 }
288
289 if (!timer->io_base) 285 if (!timer->io_base)
290 return -ENXIO; 286 return -ENXIO;
291 287
292 omap_hwmod_setup_one(oh_name); 288 omap_hwmod_setup_one(oh_name);
293 289
294 /* After the dmtimer is using hwmod these clocks won't be needed */ 290 /* After the dmtimer is using hwmod these clocks won't be needed */
295 timer->fclk = clk_get(NULL, omap_hwmod_get_main_clk(oh)); 291 if (IS_ERR_OR_NULL(timer->fclk))
292 timer->fclk = clk_get(NULL, omap_hwmod_get_main_clk(oh));
296 if (IS_ERR(timer->fclk)) 293 if (IS_ERR(timer->fclk))
297 return PTR_ERR(timer->fclk); 294 return PTR_ERR(timer->fclk);
298 295
@@ -358,6 +355,14 @@ static void __init omap2_gp_clockevent_init(int gptimer_id,
358 3, /* Timer internal resynch latency */ 355 3, /* Timer internal resynch latency */
359 0xffffffff); 356 0xffffffff);
360 357
358 if (soc_is_am33xx() || soc_is_am43xx()) {
359 clockevent_gpt.suspend = omap_clkevt_idle;
360 clockevent_gpt.resume = omap_clkevt_unidle;
361
362 clockevent_gpt_hwmod =
363 omap_hwmod_lookup(clockevent_gpt.name);
364 }
365
361 pr_info("OMAP clockevent source: %s at %lu Hz\n", clockevent_gpt.name, 366 pr_info("OMAP clockevent source: %s at %lu Hz\n", clockevent_gpt.name,
362 clkev.rate); 367 clkev.rate);
363} 368}
@@ -405,18 +410,15 @@ static int __init __maybe_unused omap2_sync32k_clocksource_init(void)
405 const char *oh_name = "counter_32k"; 410 const char *oh_name = "counter_32k";
406 411
407 /* 412 /*
408 * If device-tree is present, then search the DT blob 413 * See if the 32kHz counter is supported.
409 * to see if the 32kHz counter is supported.
410 */ 414 */
411 if (of_have_populated_dt()) { 415 np = omap_get_timer_dt(omap_counter_match, NULL);
412 np = omap_get_timer_dt(omap_counter_match, NULL); 416 if (!np)
413 if (!np) 417 return -ENODEV;
414 return -ENODEV; 418
415 419 of_property_read_string_index(np, "ti,hwmods", 0, &oh_name);
416 of_property_read_string_index(np, "ti,hwmods", 0, &oh_name); 420 if (!oh_name)
417 if (!oh_name) 421 return -ENODEV;
418 return -ENODEV;
419 }
420 422
421 /* 423 /*
422 * First check hwmod data is available for sync32k counter 424 * First check hwmod data is available for sync32k counter
@@ -434,18 +436,6 @@ static int __init __maybe_unused omap2_sync32k_clocksource_init(void)
434 return ret; 436 return ret;
435 } 437 }
436 438
437 if (!of_have_populated_dt()) {
438 void __iomem *vbase;
439
440 vbase = omap_hwmod_get_mpu_rt_va(oh);
441
442 ret = omap_init_clocksource_32k(vbase);
443 if (ret) {
444 pr_warn("%s: failed to initialize counter_32k as a clocksource (%d)\n",
445 __func__, ret);
446 omap_hwmod_idle(oh);
447 }
448 }
449 return ret; 439 return ret;
450} 440}
451 441
@@ -661,96 +651,6 @@ void __init omap5_realtime_timer_init(void)
661#endif /* CONFIG_SOC_OMAP5 || CONFIG_SOC_DRA7XX */ 651#endif /* CONFIG_SOC_OMAP5 || CONFIG_SOC_DRA7XX */
662 652
663/** 653/**
664 * omap_timer_init - build and register timer device with an
665 * associated timer hwmod
666 * @oh: timer hwmod pointer to be used to build timer device
667 * @user: parameter that can be passed from calling hwmod API
668 *
669 * Called by omap_hwmod_for_each_by_class to register each of the timer
670 * devices present in the system. The number of timer devices is known
671 * by parsing through the hwmod database for a given class name. At the
672 * end of function call memory is allocated for timer device and it is
673 * registered to the framework ready to be proved by the driver.
674 */
675static int __init omap_timer_init(struct omap_hwmod *oh, void *unused)
676{
677 int id;
678 int ret = 0;
679 char *name = "omap_timer";
680 struct dmtimer_platform_data *pdata;
681 struct platform_device *pdev;
682 struct omap_timer_capability_dev_attr *timer_dev_attr;
683
684 pr_debug("%s: %s\n", __func__, oh->name);
685
686 /* on secure device, do not register secure timer */
687 timer_dev_attr = oh->dev_attr;
688 if (omap_type() != OMAP2_DEVICE_TYPE_GP && timer_dev_attr)
689 if (timer_dev_attr->timer_capability == OMAP_TIMER_SECURE)
690 return ret;
691
692 pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
693 if (!pdata) {
694 pr_err("%s: No memory for [%s]\n", __func__, oh->name);
695 return -ENOMEM;
696 }
697
698 /*
699 * Extract the IDs from name field in hwmod database
700 * and use the same for constructing ids' for the
701 * timer devices. In a way, we are avoiding usage of
702 * static variable witin the function to do the same.
703 * CAUTION: We have to be careful and make sure the
704 * name in hwmod database does not change in which case
705 * we might either make corresponding change here or
706 * switch back static variable mechanism.
707 */
708 sscanf(oh->name, "timer%2d", &id);
709
710 if (timer_dev_attr)
711 pdata->timer_capability = timer_dev_attr->timer_capability;
712
713 pdata->timer_errata = omap_dm_timer_get_errata();
714 pdata->get_context_loss_count = omap_pm_get_dev_context_loss_count;
715
716 pdev = omap_device_build(name, id, oh, pdata, sizeof(*pdata));
717
718 if (IS_ERR(pdev)) {
719 pr_err("%s: Can't build omap_device for %s: %s.\n",
720 __func__, name, oh->name);
721 ret = -EINVAL;
722 }
723
724 kfree(pdata);
725
726 return ret;
727}
728
729/**
730 * omap2_dm_timer_init - top level regular device initialization
731 *
732 * Uses dedicated hwmod api to parse through hwmod database for
733 * given class name and then build and register the timer device.
734 */
735static int __init omap2_dm_timer_init(void)
736{
737 int ret;
738
739 /* If dtb is there, the devices will be created dynamically */
740 if (of_have_populated_dt())
741 return -ENODEV;
742
743 ret = omap_hwmod_for_each_by_class("timer", omap_timer_init, NULL);
744 if (unlikely(ret)) {
745 pr_err("%s: device registration failed.\n", __func__);
746 return -EINVAL;
747 }
748
749 return 0;
750}
751omap_arch_initcall(omap2_dm_timer_init);
752
753/**
754 * omap2_override_clocksource - clocksource override with user configuration 654 * omap2_override_clocksource - clocksource override with user configuration
755 * 655 *
756 * Allows user to override default clocksource, using kernel parameter 656 * Allows user to override default clocksource, using kernel parameter
diff --git a/arch/arm/mach-omap2/wd_timer.c b/arch/arm/mach-omap2/wd_timer.c
index ff0a68cf7439..0084b6c77cf1 100644
--- a/arch/arm/mach-omap2/wd_timer.c
+++ b/arch/arm/mach-omap2/wd_timer.c
@@ -102,31 +102,3 @@ int omap2_wd_timer_reset(struct omap_hwmod *oh)
102 return (c == MAX_MODULE_SOFTRESET_WAIT) ? -ETIMEDOUT : 102 return (c == MAX_MODULE_SOFTRESET_WAIT) ? -ETIMEDOUT :
103 omap2_wd_timer_disable(oh); 103 omap2_wd_timer_disable(oh);
104} 104}
105
106static int __init omap_init_wdt(void)
107{
108 int id = -1;
109 struct platform_device *pdev;
110 struct omap_hwmod *oh;
111 char *oh_name = "wd_timer2";
112 char *dev_name = "omap_wdt";
113 struct omap_wd_timer_platform_data pdata;
114
115 if (!cpu_class_is_omap2() || of_have_populated_dt())
116 return 0;
117
118 oh = omap_hwmod_lookup(oh_name);
119 if (!oh) {
120 pr_err("Could not look up wd_timer%d hwmod\n", id);
121 return -EINVAL;
122 }
123
124 pdata.read_reset_sources = prm_read_reset_sources;
125
126 pdev = omap_device_build(dev_name, id, oh, &pdata,
127 sizeof(struct omap_wd_timer_platform_data));
128 WARN(IS_ERR(pdev), "Can't build omap_device for %s:%s.\n",
129 dev_name, oh->name);
130 return 0;
131}
132omap_subsys_initcall(omap_init_wdt);
generated by cgit v1.2.2 (git 2.25.0) at 2025-04-26 07:16:10 -0400