aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorAlexandre Torgue <alexandre.torgue@st.com>2017-10-04 09:34:48 -0400
committerAlexandre Torgue <alexandre.torgue@st.com>2017-10-04 09:34:48 -0400
commit2aaae13a9db7897a007c5d7bb46cacfb37dffacd (patch)
treee9c745aa9db3a2ea0fd48ad5c014e1f0ba2d81f6
parent4edd8121e555acbee63578abeaf73026d055bbb4 (diff)
ARM: dts: stm32: use right pinctrl compatible for stm32f469
Currently, same stm32f429-pinctrl driver is used for stm32f429 and stm32f469. As pin map is different between those 2 MCUs, a stm32f469-pinctrl driver has been recently added. This patch -allows to use stm32f469-pinctrl driver for stm32f469 boards -reworks stm32 devicetree files to fit with stm32f429 / stm32f469 In the same time it fixes an issue when only MACH_STM32F469 flag is selected in menuconfig. Fixes: d28bcd53fa90 ("ARM: stm32: Introduce MACH_STM32F469 flag") Reported-by: Nicolas Pitre <nicolas.pitre@linaro.org> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
Diffstat
-rw-r--r--arch/arm/boot/dts/stm32429i-eval.dts1
-rw-r--r--arch/arm/boot/dts/stm32f4-pinctrl.dtsi343
-rw-r--r--arch/arm/boot/dts/stm32f429-disco.dts1
-rw-r--r--arch/arm/boot/dts/stm32f429-pinctrl.dtsi95
-rw-r--r--arch/arm/boot/dts/stm32f429.dtsi297
-rw-r--r--arch/arm/boot/dts/stm32f469-disco.dts1
-rw-r--r--arch/arm/boot/dts/stm32f469-pinctrl.dtsi96
7 files changed, 537 insertions, 297 deletions
diff --git a/arch/arm/boot/dts/stm32429i-eval.dts b/arch/arm/boot/dts/stm32429i-eval.dts
index 5bdb90b2ae72..293ecb957227 100644
--- a/arch/arm/boot/dts/stm32429i-eval.dts
+++ b/arch/arm/boot/dts/stm32429i-eval.dts
@@ -47,6 +47,7 @@
47 47
48/dts-v1/; 48/dts-v1/;
49#include "stm32f429.dtsi" 49#include "stm32f429.dtsi"
50#include "stm32f429-pinctrl.dtsi"
50#include <dt-bindings/input/input.h> 51#include <dt-bindings/input/input.h>
51#include <dt-bindings/gpio/gpio.h> 52#include <dt-bindings/gpio/gpio.h>
52 53
diff --git a/arch/arm/boot/dts/stm32f4-pinctrl.dtsi b/arch/arm/boot/dts/stm32f4-pinctrl.dtsi
new file mode 100644
index 000000000000..7f3560c0211d
--- /dev/null
+++ b/arch/arm/boot/dts/stm32f4-pinctrl.dtsi
@@ -0,0 +1,343 @@
1/*
2 * Copyright 2017 - Alexandre Torgue <alexandre.torgue@st.com>
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
13 *
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * Or, alternatively,
20 *
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
28 * conditions:
29 *
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
32 *
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
41 */
42
43#include <dt-bindings/pinctrl/stm32f429-pinfunc.h>
44#include <dt-bindings/mfd/stm32f4-rcc.h>
45
46/ {
47 soc {
48 pinctrl: pin-controller {
49 #address-cells = <1>;
50 #size-cells = <1>;
51 ranges = <0 0x40020000 0x3000>;
52 interrupt-parent = <&exti>;
53 st,syscfg = <&syscfg 0x8>;
54 pins-are-numbered;
55
56 gpioa: gpio@40020000 {
57 gpio-controller;
58 #gpio-cells = <2>;
59 interrupt-controller;
60 #interrupt-cells = <2>;
61 reg = <0x0 0x400>;
62 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOA)>;
63 st,bank-name = "GPIOA";
64 };
65
66 gpiob: gpio@40020400 {
67 gpio-controller;
68 #gpio-cells = <2>;
69 interrupt-controller;
70 #interrupt-cells = <2>;
71 reg = <0x400 0x400>;
72 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOB)>;
73 st,bank-name = "GPIOB";
74 };
75
76 gpioc: gpio@40020800 {
77 gpio-controller;
78 #gpio-cells = <2>;
79 interrupt-controller;
80 #interrupt-cells = <2>;
81 reg = <0x800 0x400>;
82 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOC)>;
83 st,bank-name = "GPIOC";
84 };
85
86 gpiod: gpio@40020c00 {
87 gpio-controller;
88 #gpio-cells = <2>;
89 interrupt-controller;
90 #interrupt-cells = <2>;
91 reg = <0xc00 0x400>;
92 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOD)>;
93 st,bank-name = "GPIOD";
94 };
95
96 gpioe: gpio@40021000 {
97 gpio-controller;
98 #gpio-cells = <2>;
99 interrupt-controller;
100 #interrupt-cells = <2>;
101 reg = <0x1000 0x400>;
102 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOE)>;
103 st,bank-name = "GPIOE";
104 };
105
106 gpiof: gpio@40021400 {
107 gpio-controller;
108 #gpio-cells = <2>;
109 interrupt-controller;
110 #interrupt-cells = <2>;
111 reg = <0x1400 0x400>;
112 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOF)>;
113 st,bank-name = "GPIOF";
114 };
115
116 gpiog: gpio@40021800 {
117 gpio-controller;
118 #gpio-cells = <2>;
119 interrupt-controller;
120 #interrupt-cells = <2>;
121 reg = <0x1800 0x400>;
122 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOG)>;
123 st,bank-name = "GPIOG";
124 };
125
126 gpioh: gpio@40021c00 {
127 gpio-controller;
128 #gpio-cells = <2>;
129 interrupt-controller;
130 #interrupt-cells = <2>;
131 reg = <0x1c00 0x400>;
132 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOH)>;
133 st,bank-name = "GPIOH";
134 };
135
136 gpioi: gpio@40022000 {
137 gpio-controller;
138 #gpio-cells = <2>;
139 interrupt-controller;
140 #interrupt-cells = <2>;
141 reg = <0x2000 0x400>;
142 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOI)>;
143 st,bank-name = "GPIOI";
144 };
145
146 gpioj: gpio@40022400 {
147 gpio-controller;
148 #gpio-cells = <2>;
149 interrupt-controller;
150 #interrupt-cells = <2>;
151 reg = <0x2400 0x400>;
152 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOJ)>;
153 st,bank-name = "GPIOJ";
154 };
155
156 gpiok: gpio@40022800 {
157 gpio-controller;
158 #gpio-cells = <2>;
159 interrupt-controller;
160 #interrupt-cells = <2>;
161 reg = <0x2800 0x400>;
162 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOK)>;
163 st,bank-name = "GPIOK";
164 };
165
166 usart1_pins_a: usart1@0 {
167 pins1 {
168 pinmux = <STM32F429_PA9_FUNC_USART1_TX>;
169 bias-disable;
170 drive-push-pull;
171 slew-rate = <0>;
172 };
173 pins2 {
174 pinmux = <STM32F429_PA10_FUNC_USART1_RX>;
175 bias-disable;
176 };
177 };
178
179 usart3_pins_a: usart3@0 {
180 pins1 {
181 pinmux = <STM32F429_PB10_FUNC_USART3_TX>;
182 bias-disable;
183 drive-push-pull;
184 slew-rate = <0>;
185 };
186 pins2 {
187 pinmux = <STM32F429_PB11_FUNC_USART3_RX>;
188 bias-disable;
189 };
190 };
191
192 usbotg_fs_pins_a: usbotg_fs@0 {
193 pins {
194 pinmux = <STM32F429_PA10_FUNC_OTG_FS_ID>,
195 <STM32F429_PA11_FUNC_OTG_FS_DM>,
196 <STM32F429_PA12_FUNC_OTG_FS_DP>;
197 bias-disable;
198 drive-push-pull;
199 slew-rate = <2>;
200 };
201 };
202
203 usbotg_fs_pins_b: usbotg_fs@1 {
204 pins {
205 pinmux = <STM32F429_PB12_FUNC_OTG_HS_ID>,
206 <STM32F429_PB14_FUNC_OTG_HS_DM>,
207 <STM32F429_PB15_FUNC_OTG_HS_DP>;
208 bias-disable;
209 drive-push-pull;
210 slew-rate = <2>;
211 };
212 };
213
214 usbotg_hs_pins_a: usbotg_hs@0 {
215 pins {
216 pinmux = <STM32F429_PH4_FUNC_OTG_HS_ULPI_NXT>,
217 <STM32F429_PI11_FUNC_OTG_HS_ULPI_DIR>,
218 <STM32F429_PC0_FUNC_OTG_HS_ULPI_STP>,
219 <STM32F429_PA5_FUNC_OTG_HS_ULPI_CK>,
220 <STM32F429_PA3_FUNC_OTG_HS_ULPI_D0>,
221 <STM32F429_PB0_FUNC_OTG_HS_ULPI_D1>,
222 <STM32F429_PB1_FUNC_OTG_HS_ULPI_D2>,
223 <STM32F429_PB10_FUNC_OTG_HS_ULPI_D3>,
224 <STM32F429_PB11_FUNC_OTG_HS_ULPI_D4>,
225 <STM32F429_PB12_FUNC_OTG_HS_ULPI_D5>,
226 <STM32F429_PB13_FUNC_OTG_HS_ULPI_D6>,
227 <STM32F429_PB5_FUNC_OTG_HS_ULPI_D7>;
228 bias-disable;
229 drive-push-pull;
230 slew-rate = <2>;
231 };
232 };
233
234 ethernet_mii: mii@0 {
235 pins {
236 pinmux = <STM32F429_PG13_FUNC_ETH_MII_TXD0_ETH_RMII_TXD0>,
237 <STM32F429_PG14_FUNC_ETH_MII_TXD1_ETH_RMII_TXD1>,
238 <STM32F429_PC2_FUNC_ETH_MII_TXD2>,
239 <STM32F429_PB8_FUNC_ETH_MII_TXD3>,
240 <STM32F429_PC3_FUNC_ETH_MII_TX_CLK>,
241 <STM32F429_PG11_FUNC_ETH_MII_TX_EN_ETH_RMII_TX_EN>,
242 <STM32F429_PA2_FUNC_ETH_MDIO>,
243 <STM32F429_PC1_FUNC_ETH_MDC>,
244 <STM32F429_PA1_FUNC_ETH_MII_RX_CLK_ETH_RMII_REF_CLK>,
245 <STM32F429_PA7_FUNC_ETH_MII_RX_DV_ETH_RMII_CRS_DV>,
246 <STM32F429_PC4_FUNC_ETH_MII_RXD0_ETH_RMII_RXD0>,
247 <STM32F429_PC5_FUNC_ETH_MII_RXD1_ETH_RMII_RXD1>,
248 <STM32F429_PH6_FUNC_ETH_MII_RXD2>,
249 <STM32F429_PH7_FUNC_ETH_MII_RXD3>;
250 slew-rate = <2>;
251 };
252 };
253
254 adc3_in8_pin: adc@200 {
255 pins {
256 pinmux = <STM32F429_PF10_FUNC_ANALOG>;
257 };
258 };
259
260 pwm1_pins: pwm@1 {
261 pins {
262 pinmux = <STM32F429_PA8_FUNC_TIM1_CH1>,
263 <STM32F429_PB13_FUNC_TIM1_CH1N>,
264 <STM32F429_PB12_FUNC_TIM1_BKIN>;
265 };
266 };
267
268 pwm3_pins: pwm@3 {
269 pins {
270 pinmux = <STM32F429_PB4_FUNC_TIM3_CH1>,
271 <STM32F429_PB5_FUNC_TIM3_CH2>;
272 };
273 };
274
275 i2c1_pins: i2c1@0 {
276 pins {
277 pinmux = <STM32F429_PB9_FUNC_I2C1_SDA>,
278 <STM32F429_PB6_FUNC_I2C1_SCL>;
279 bias-disable;
280 drive-open-drain;
281 slew-rate = <3>;
282 };
283 };
284
285 ltdc_pins: ltdc@0 {
286 pins {
287 pinmux = <STM32F429_PI12_FUNC_LCD_HSYNC>,
288 <STM32F429_PI13_FUNC_LCD_VSYNC>,
289 <STM32F429_PI14_FUNC_LCD_CLK>,
290 <STM32F429_PI15_FUNC_LCD_R0>,
291 <STM32F429_PJ0_FUNC_LCD_R1>,
292 <STM32F429_PJ1_FUNC_LCD_R2>,
293 <STM32F429_PJ2_FUNC_LCD_R3>,
294 <STM32F429_PJ3_FUNC_LCD_R4>,
295 <STM32F429_PJ4_FUNC_LCD_R5>,
296 <STM32F429_PJ5_FUNC_LCD_R6>,
297 <STM32F429_PJ6_FUNC_LCD_R7>,
298 <STM32F429_PJ7_FUNC_LCD_G0>,
299 <STM32F429_PJ8_FUNC_LCD_G1>,
300 <STM32F429_PJ9_FUNC_LCD_G2>,
301 <STM32F429_PJ10_FUNC_LCD_G3>,
302 <STM32F429_PJ11_FUNC_LCD_G4>,
303 <STM32F429_PJ12_FUNC_LCD_B0>,
304 <STM32F429_PJ13_FUNC_LCD_B1>,
305 <STM32F429_PJ14_FUNC_LCD_B2>,
306 <STM32F429_PJ15_FUNC_LCD_B3>,
307 <STM32F429_PK0_FUNC_LCD_G5>,
308 <STM32F429_PK1_FUNC_LCD_G6>,
309 <STM32F429_PK2_FUNC_LCD_G7>,
310 <STM32F429_PK3_FUNC_LCD_B4>,
311 <STM32F429_PK4_FUNC_LCD_B5>,
312 <STM32F429_PK5_FUNC_LCD_B6>,
313 <STM32F429_PK6_FUNC_LCD_B7>,
314 <STM32F429_PK7_FUNC_LCD_DE>;
315 slew-rate = <2>;
316 };
317 };
318
319 dcmi_pins: dcmi@0 {
320 pins {
321 pinmux = <STM32F429_PA4_FUNC_DCMI_HSYNC>,
322 <STM32F429_PB7_FUNC_DCMI_VSYNC>,
323 <STM32F429_PA6_FUNC_DCMI_PIXCLK>,
324 <STM32F429_PC6_FUNC_DCMI_D0>,
325 <STM32F429_PC7_FUNC_DCMI_D1>,
326 <STM32F429_PC8_FUNC_DCMI_D2>,
327 <STM32F429_PC9_FUNC_DCMI_D3>,
328 <STM32F429_PC11_FUNC_DCMI_D4>,
329 <STM32F429_PD3_FUNC_DCMI_D5>,
330 <STM32F429_PB8_FUNC_DCMI_D6>,
331 <STM32F429_PE6_FUNC_DCMI_D7>,
332 <STM32F429_PC10_FUNC_DCMI_D8>,
333 <STM32F429_PC12_FUNC_DCMI_D9>,
334 <STM32F429_PD6_FUNC_DCMI_D10>,
335 <STM32F429_PD2_FUNC_DCMI_D11>;
336 bias-disable;
337 drive-push-pull;
338 slew-rate = <3>;
339 };
340 };
341 };
342 };
343};
diff --git a/arch/arm/boot/dts/stm32f429-disco.dts b/arch/arm/boot/dts/stm32f429-disco.dts
index c66d617e4245..5ceb2cf3777f 100644
--- a/arch/arm/boot/dts/stm32f429-disco.dts
+++ b/arch/arm/boot/dts/stm32f429-disco.dts
@@ -47,6 +47,7 @@
47 47
48/dts-v1/; 48/dts-v1/;
49#include "stm32f429.dtsi" 49#include "stm32f429.dtsi"
50#include "stm32f429-pinctrl.dtsi"
50#include <dt-bindings/input/input.h> 51#include <dt-bindings/input/input.h>
51 52
52/ { 53/ {
diff --git a/arch/arm/boot/dts/stm32f429-pinctrl.dtsi b/arch/arm/boot/dts/stm32f429-pinctrl.dtsi
new file mode 100644
index 000000000000..3e7a17d9112e
--- /dev/null
+++ b/arch/arm/boot/dts/stm32f429-pinctrl.dtsi
@@ -0,0 +1,95 @@
1/*
2 * Copyright 2017 - Alexandre Torgue <alexandre.torgue@st.com>
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
13 *
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * Or, alternatively,
20 *
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
28 * conditions:
29 *
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
32 *
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
41 */
42
43#include "stm32f4-pinctrl.dtsi"
44
45/ {
46 soc {
47 pinctrl: pin-controller {
48 compatible = "st,stm32f429-pinctrl";
49
50 gpioa: gpio@40020000 {
51 gpio-ranges = <&pinctrl 0 0 16>;
52 };
53
54 gpiob: gpio@40020400 {
55 gpio-ranges = <&pinctrl 0 16 16>;
56 };
57
58 gpioc: gpio@40020800 {
59 gpio-ranges = <&pinctrl 0 32 16>;
60 };
61
62 gpiod: gpio@40020c00 {
63 gpio-ranges = <&pinctrl 0 48 16>;
64 };
65
66 gpioe: gpio@40021000 {
67 gpio-ranges = <&pinctrl 0 64 16>;
68 };
69
70 gpiof: gpio@40021400 {
71 gpio-ranges = <&pinctrl 0 80 16>;
72 };
73
74 gpiog: gpio@40021800 {
75 gpio-ranges = <&pinctrl 0 96 16>;
76 };
77
78 gpioh: gpio@40021c00 {
79 gpio-ranges = <&pinctrl 0 112 16>;
80 };
81
82 gpioi: gpio@40022000 {
83 gpio-ranges = <&pinctrl 0 128 16>;
84 };
85
86 gpioj: gpio@40022400 {
87 gpio-ranges = <&pinctrl 0 144 16>;
88 };
89
90 gpiok: gpio@40022800 {
91 gpio-ranges = <&pinctrl 0 160 8>;
92 };
93 };
94 };
95};
diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi
index dd7e99b1f43b..5b36eb114ddc 100644
--- a/arch/arm/boot/dts/stm32f429.dtsi
+++ b/arch/arm/boot/dts/stm32f429.dtsi
@@ -47,7 +47,6 @@
47 47
48#include "skeleton.dtsi" 48#include "skeleton.dtsi"
49#include "armv7-m.dtsi" 49#include "armv7-m.dtsi"
50#include <dt-bindings/pinctrl/stm32f429-pinfunc.h>
51#include <dt-bindings/clock/stm32fx-clock.h> 50#include <dt-bindings/clock/stm32fx-clock.h>
52#include <dt-bindings/mfd/stm32f4-rcc.h> 51#include <dt-bindings/mfd/stm32f4-rcc.h>
53 52
@@ -591,302 +590,6 @@
591 status = "disabled"; 590 status = "disabled";
592 }; 591 };
593 592
594 pinctrl: pin-controller {
595 #address-cells = <1>;
596 #size-cells = <1>;
597 compatible = "st,stm32f429-pinctrl";
598 ranges = <0 0x40020000 0x3000>;
599 interrupt-parent = <&exti>;
600 st,syscfg = <&syscfg 0x8>;
601 pins-are-numbered;
602
603 gpioa: gpio@40020000 {
604 gpio-controller;
605 #gpio-cells = <2>;
606 interrupt-controller;
607 #interrupt-cells = <2>;
608 reg = <0x0 0x400>;
609 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOA)>;
610 st,bank-name = "GPIOA";
611 };
612
613 gpiob: gpio@40020400 {
614 gpio-controller;
615 #gpio-cells = <2>;
616 interrupt-controller;
617 #interrupt-cells = <2>;
618 reg = <0x400 0x400>;
619 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOB)>;
620 st,bank-name = "GPIOB";
621 };
622
623 gpioc: gpio@40020800 {
624 gpio-controller;
625 #gpio-cells = <2>;
626 interrupt-controller;
627 #interrupt-cells = <2>;
628 reg = <0x800 0x400>;
629 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOC)>;
630 st,bank-name = "GPIOC";
631 };
632
633 gpiod: gpio@40020c00 {
634 gpio-controller;
635 #gpio-cells = <2>;
636 interrupt-controller;
637 #interrupt-cells = <2>;
638 reg = <0xc00 0x400>;
639 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOD)>;
640 st,bank-name = "GPIOD";
641 };
642
643 gpioe: gpio@40021000 {
644 gpio-controller;
645 #gpio-cells = <2>;
646 interrupt-controller;
647 #interrupt-cells = <2>;
648 reg = <0x1000 0x400>;
649 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOE)>;
650 st,bank-name = "GPIOE";
651 };
652
653 gpiof: gpio@40021400 {
654 gpio-controller;
655 #gpio-cells = <2>;
656 interrupt-controller;
657 #interrupt-cells = <2>;
658 reg = <0x1400 0x400>;
659 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOF)>;
660 st,bank-name = "GPIOF";
661 };
662
663 gpiog: gpio@40021800 {
664 gpio-controller;
665 #gpio-cells = <2>;
666 interrupt-controller;
667 #interrupt-cells = <2>;
668 reg = <0x1800 0x400>;
669 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOG)>;
670 st,bank-name = "GPIOG";
671 };
672
673 gpioh: gpio@40021c00 {
674 gpio-controller;
675 #gpio-cells = <2>;
676 interrupt-controller;
677 #interrupt-cells = <2>;
678 reg = <0x1c00 0x400>;
679 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOH)>;
680 st,bank-name = "GPIOH";
681 };
682
683 gpioi: gpio@40022000 {
684 gpio-controller;
685 #gpio-cells = <2>;
686 interrupt-controller;
687 #interrupt-cells = <2>;
688 reg = <0x2000 0x400>;
689 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOI)>;
690 st,bank-name = "GPIOI";
691 };
692
693 gpioj: gpio@40022400 {
694 gpio-controller;
695 #gpio-cells = <2>;
696 interrupt-controller;
697 #interrupt-cells = <2>;
698 reg = <0x2400 0x400>;
699 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOJ)>;
700 st,bank-name = "GPIOJ";
701 };
702
703 gpiok: gpio@40022800 {
704 gpio-controller;
705 #gpio-cells = <2>;
706 interrupt-controller;
707 #interrupt-cells = <2>;
708 reg = <0x2800 0x400>;
709 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOK)>;
710 st,bank-name = "GPIOK";
711 };
712
713 usart1_pins_a: usart1@0 {
714 pins1 {
715 pinmux = <STM32F429_PA9_FUNC_USART1_TX>;
716 bias-disable;
717 drive-push-pull;
718 slew-rate = <0>;
719 };
720 pins2 {
721 pinmux = <STM32F429_PA10_FUNC_USART1_RX>;
722 bias-disable;
723 };
724 };
725
726 usart3_pins_a: usart3@0 {
727 pins1 {
728 pinmux = <STM32F429_PB10_FUNC_USART3_TX>;
729 bias-disable;
730 drive-push-pull;
731 slew-rate = <0>;
732 };
733 pins2 {
734 pinmux = <STM32F429_PB11_FUNC_USART3_RX>;
735 bias-disable;
736 };
737 };
738
739 usbotg_fs_pins_a: usbotg_fs@0 {
740 pins {
741 pinmux = <STM32F429_PA10_FUNC_OTG_FS_ID>,
742 <STM32F429_PA11_FUNC_OTG_FS_DM>,
743 <STM32F429_PA12_FUNC_OTG_FS_DP>;
744 bias-disable;
745 drive-push-pull;
746 slew-rate = <2>;
747 };
748 };
749
750 usbotg_fs_pins_b: usbotg_fs@1 {
751 pins {
752 pinmux = <STM32F429_PB12_FUNC_OTG_HS_ID>,
753 <STM32F429_PB14_FUNC_OTG_HS_DM>,
754 <STM32F429_PB15_FUNC_OTG_HS_DP>;
755 bias-disable;
756 drive-push-pull;
757 slew-rate = <2>;
758 };
759 };
760
761 usbotg_hs_pins_a: usbotg_hs@0 {
762 pins {
763 pinmux = <STM32F429_PH4_FUNC_OTG_HS_ULPI_NXT>,
764 <STM32F429_PI11_FUNC_OTG_HS_ULPI_DIR>,
765 <STM32F429_PC0_FUNC_OTG_HS_ULPI_STP>,
766 <STM32F429_PA5_FUNC_OTG_HS_ULPI_CK>,
767 <STM32F429_PA3_FUNC_OTG_HS_ULPI_D0>,
768 <STM32F429_PB0_FUNC_OTG_HS_ULPI_D1>,
769 <STM32F429_PB1_FUNC_OTG_HS_ULPI_D2>,
770 <STM32F429_PB10_FUNC_OTG_HS_ULPI_D3>,
771 <STM32F429_PB11_FUNC_OTG_HS_ULPI_D4>,
772 <STM32F429_PB12_FUNC_OTG_HS_ULPI_D5>,
773 <STM32F429_PB13_FUNC_OTG_HS_ULPI_D6>,
774 <STM32F429_PB5_FUNC_OTG_HS_ULPI_D7>;
775 bias-disable;
776 drive-push-pull;
777 slew-rate = <2>;
778 };
779 };
780
781 ethernet_mii: mii@0 {
782 pins {
783 pinmux = <STM32F429_PG13_FUNC_ETH_MII_TXD0_ETH_RMII_TXD0>,
784 <STM32F429_PG14_FUNC_ETH_MII_TXD1_ETH_RMII_TXD1>,
785 <STM32F429_PC2_FUNC_ETH_MII_TXD2>,
786 <STM32F429_PB8_FUNC_ETH_MII_TXD3>,
787 <STM32F429_PC3_FUNC_ETH_MII_TX_CLK>,
788 <STM32F429_PG11_FUNC_ETH_MII_TX_EN_ETH_RMII_TX_EN>,
789 <STM32F429_PA2_FUNC_ETH_MDIO>,
790 <STM32F429_PC1_FUNC_ETH_MDC>,
791 <STM32F429_PA1_FUNC_ETH_MII_RX_CLK_ETH_RMII_REF_CLK>,
792 <STM32F429_PA7_FUNC_ETH_MII_RX_DV_ETH_RMII_CRS_DV>,
793 <STM32F429_PC4_FUNC_ETH_MII_RXD0_ETH_RMII_RXD0>,
794 <STM32F429_PC5_FUNC_ETH_MII_RXD1_ETH_RMII_RXD1>,
795 <STM32F429_PH6_FUNC_ETH_MII_RXD2>,
796 <STM32F429_PH7_FUNC_ETH_MII_RXD3>;
797 slew-rate = <2>;
798 };
799 };
800
801 adc3_in8_pin: adc@200 {
802 pins {
803 pinmux = <STM32F429_PF10_FUNC_ANALOG>;
804 };
805 };
806
807 pwm1_pins: pwm@1 {
808 pins {
809 pinmux = <STM32F429_PA8_FUNC_TIM1_CH1>,
810 <STM32F429_PB13_FUNC_TIM1_CH1N>,
811 <STM32F429_PB12_FUNC_TIM1_BKIN>;
812 };
813 };
814
815 pwm3_pins: pwm@3 {
816 pins {
817 pinmux = <STM32F429_PB4_FUNC_TIM3_CH1>,
818 <STM32F429_PB5_FUNC_TIM3_CH2>;
819 };
820 };
821
822 i2c1_pins: i2c1@0 {
823 pins {
824 pinmux = <STM32F429_PB9_FUNC_I2C1_SDA>,
825 <STM32F429_PB6_FUNC_I2C1_SCL>;
826 bias-disable;
827 drive-open-drain;
828 slew-rate = <3>;
829 };
830 };
831
832 ltdc_pins: ltdc@0 {
833 pins {
834 pinmux = <STM32F429_PI12_FUNC_LCD_HSYNC>,
835 <STM32F429_PI13_FUNC_LCD_VSYNC>,
836 <STM32F429_PI14_FUNC_LCD_CLK>,
837 <STM32F429_PI15_FUNC_LCD_R0>,
838 <STM32F429_PJ0_FUNC_LCD_R1>,
839 <STM32F429_PJ1_FUNC_LCD_R2>,
840 <STM32F429_PJ2_FUNC_LCD_R3>,
841 <STM32F429_PJ3_FUNC_LCD_R4>,
842 <STM32F429_PJ4_FUNC_LCD_R5>,
843 <STM32F429_PJ5_FUNC_LCD_R6>,
844 <STM32F429_PJ6_FUNC_LCD_R7>,
845 <STM32F429_PJ7_FUNC_LCD_G0>,
846 <STM32F429_PJ8_FUNC_LCD_G1>,
847 <STM32F429_PJ9_FUNC_LCD_G2>,
848 <STM32F429_PJ10_FUNC_LCD_G3>,
849 <STM32F429_PJ11_FUNC_LCD_G4>,
850 <STM32F429_PJ12_FUNC_LCD_B0>,
851 <STM32F429_PJ13_FUNC_LCD_B1>,
852 <STM32F429_PJ14_FUNC_LCD_B2>,
853 <STM32F429_PJ15_FUNC_LCD_B3>,
854 <STM32F429_PK0_FUNC_LCD_G5>,
855 <STM32F429_PK1_FUNC_LCD_G6>,
856 <STM32F429_PK2_FUNC_LCD_G7>,
857 <STM32F429_PK3_FUNC_LCD_B4>,
858 <STM32F429_PK4_FUNC_LCD_B5>,
859 <STM32F429_PK5_FUNC_LCD_B6>,
860 <STM32F429_PK6_FUNC_LCD_B7>,
861 <STM32F429_PK7_FUNC_LCD_DE>;
862 slew-rate = <2>;
863 };
864 };
865
866 dcmi_pins: dcmi@0 {
867 pins {
868 pinmux = <STM32F429_PA4_FUNC_DCMI_HSYNC>,
869 <STM32F429_PB7_FUNC_DCMI_VSYNC>,
870 <STM32F429_PA6_FUNC_DCMI_PIXCLK>,
871 <STM32F429_PC6_FUNC_DCMI_D0>,
872 <STM32F429_PC7_FUNC_DCMI_D1>,
873 <STM32F429_PC8_FUNC_DCMI_D2>,
874 <STM32F429_PC9_FUNC_DCMI_D3>,
875 <STM32F429_PC11_FUNC_DCMI_D4>,
876 <STM32F429_PD3_FUNC_DCMI_D5>,
877 <STM32F429_PB8_FUNC_DCMI_D6>,
878 <STM32F429_PE6_FUNC_DCMI_D7>,
879 <STM32F429_PC10_FUNC_DCMI_D8>,
880 <STM32F429_PC12_FUNC_DCMI_D9>,
881 <STM32F429_PD6_FUNC_DCMI_D10>,
882 <STM32F429_PD2_FUNC_DCMI_D11>;
883 bias-disable;
884 drive-push-pull;
885 slew-rate = <3>;
886 };
887 };
888 };
889
890 crc: crc@40023000 { 593 crc: crc@40023000 {
891 compatible = "st,stm32f4-crc"; 594 compatible = "st,stm32f4-crc";
892 reg = <0x40023000 0x400>; 595 reg = <0x40023000 0x400>;
diff --git a/arch/arm/boot/dts/stm32f469-disco.dts b/arch/arm/boot/dts/stm32f469-disco.dts
index 6ae1f037f3f0..c18acbe4cf4e 100644
--- a/arch/arm/boot/dts/stm32f469-disco.dts
+++ b/arch/arm/boot/dts/stm32f469-disco.dts
@@ -47,6 +47,7 @@
47 47
48/dts-v1/; 48/dts-v1/;
49#include "stm32f429.dtsi" 49#include "stm32f429.dtsi"
50#include "stm32f469-pinctrl.dtsi"
50 51
51/ { 52/ {
52 model = "STMicroelectronics STM32F469i-DISCO board"; 53 model = "STMicroelectronics STM32F469i-DISCO board";
diff --git a/arch/arm/boot/dts/stm32f469-pinctrl.dtsi b/arch/arm/boot/dts/stm32f469-pinctrl.dtsi
new file mode 100644
index 000000000000..fff542662eea
--- /dev/null
+++ b/arch/arm/boot/dts/stm32f469-pinctrl.dtsi
@@ -0,0 +1,96 @@
1/*
2 * Copyright 2017 - Alexandre Torgue <alexandre.torgue@st.com>
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
13 *
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * Or, alternatively,
20 *
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
28 * conditions:
29 *
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
32 *
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
41 */
42
43#include "stm32f4-pinctrl.dtsi"
44
45/ {
46 soc {
47 pinctrl: pin-controller {
48 compatible = "st,stm32f469-pinctrl";
49
50 gpioa: gpio@40020000 {
51 gpio-ranges = <&pinctrl 0 0 16>;
52 };
53
54 gpiob: gpio@40020400 {
55 gpio-ranges = <&pinctrl 0 16 16>;
56 };
57
58 gpioc: gpio@40020800 {
59 gpio-ranges = <&pinctrl 0 32 16>;
60 };
61
62 gpiod: gpio@40020c00 {
63 gpio-ranges = <&pinctrl 0 48 16>;
64 };
65
66 gpioe: gpio@40021000 {
67 gpio-ranges = <&pinctrl 0 64 16>;
68 };
69
70 gpiof: gpio@40021400 {
71 gpio-ranges = <&pinctrl 0 80 16>;
72 };
73
74 gpiog: gpio@40021800 {
75 gpio-ranges = <&pinctrl 0 96 16>;
76 };
77
78 gpioh: gpio@40021c00 {
79 gpio-ranges = <&pinctrl 0 112 16>;
80 };
81
82 gpioi: gpio@40022000 {
83 gpio-ranges = <&pinctrl 0 128 16>;
84 };
85
86 gpioj: gpio@40022400 {
87 gpio-ranges = <&pinctrl 0 144 6>,
88 <&pinctrl 12 156 4>;
89 };
90
91 gpiok: gpio@40022800 {
92 gpio-ranges = <&pinctrl 3 163 5>;
93 };
94 };
95 };
96};
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-28 19:46:35 -0400