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authorThomas Gleixner <tglx@linutronix.de>2017-09-13 17:29:46 -0400
committerThomas Gleixner <tglx@linutronix.de>2017-09-25 14:52:00 -0400
commit2a85386a73fa57b114ba66421b57d3850dbcef9f (patch)
tree106fb7ffaf3bb1d795727c2bf214d82025be3870
parentba224feac8bb367edd62da33552353d4bdc3fe3a (diff)
x86/apic/msi: Force reactivation of interrupts at startup time
MSI(X) interrupts need a valid vector configuration early at allocation time, i.e. before the PCI core enables MSI(X). With managed interrupts and the new global reservation scheme, the early configuration will not assign a real device vector, but a special shutdown vector. When the irq is started up, then the interrupt must be reconfigured. Tell the MSI irqdomain core about it. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Tested-by: Juergen Gross <jgross@suse.com> Tested-by: Yu Chen <yu.c.chen@intel.com> Acked-by: Juergen Gross <jgross@suse.com> Cc: Boris Ostrovsky <boris.ostrovsky@oracle.com> Cc: Tony Luck <tony.luck@intel.com> Cc: Marc Zyngier <marc.zyngier@arm.com> Cc: Alok Kataria <akataria@vmware.com> Cc: Joerg Roedel <joro@8bytes.org> Cc: "Rafael J. Wysocki" <rjw@rjwysocki.net> Cc: Steven Rostedt <rostedt@goodmis.org> Cc: Christoph Hellwig <hch@lst.de> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Borislav Petkov <bp@alien8.de> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Rui Zhang <rui.zhang@intel.com> Cc: "K. Y. Srinivasan" <kys@microsoft.com> Cc: Arjan van de Ven <arjan@linux.intel.com> Cc: Dan Williams <dan.j.williams@intel.com> Cc: Len Brown <lenb@kernel.org> Link: https://lkml.kernel.org/r/20170913213155.774066582@linutronix.de
-rw-r--r--arch/x86/kernel/apic/msi.c5
1 files changed, 3 insertions, 2 deletions
diff --git a/arch/x86/kernel/apic/msi.c b/arch/x86/kernel/apic/msi.c
index 9b18be764422..5b6dd1a85ec4 100644
--- a/arch/x86/kernel/apic/msi.c
+++ b/arch/x86/kernel/apic/msi.c
@@ -129,7 +129,7 @@ static struct msi_domain_ops pci_msi_domain_ops = {
129 129
130static struct msi_domain_info pci_msi_domain_info = { 130static struct msi_domain_info pci_msi_domain_info = {
131 .flags = MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS | 131 .flags = MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
132 MSI_FLAG_PCI_MSIX, 132 MSI_FLAG_PCI_MSIX | MSI_FLAG_MUST_REACTIVATE,
133 .ops = &pci_msi_domain_ops, 133 .ops = &pci_msi_domain_ops,
134 .chip = &pci_msi_controller, 134 .chip = &pci_msi_controller,
135 .handler = handle_edge_irq, 135 .handler = handle_edge_irq,
@@ -167,7 +167,8 @@ static struct irq_chip pci_msi_ir_controller = {
167 167
168static struct msi_domain_info pci_msi_ir_domain_info = { 168static struct msi_domain_info pci_msi_ir_domain_info = {
169 .flags = MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS | 169 .flags = MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
170 MSI_FLAG_MULTI_PCI_MSI | MSI_FLAG_PCI_MSIX, 170 MSI_FLAG_MULTI_PCI_MSI | MSI_FLAG_PCI_MSIX |
171 MSI_FLAG_MUST_REACTIVATE,
171 .ops = &pci_msi_domain_ops, 172 .ops = &pci_msi_domain_ops,
172 .chip = &pci_msi_ir_controller, 173 .chip = &pci_msi_ir_controller,
173 .handler = handle_edge_irq, 174 .handler = handle_edge_irq,