diff options
author | Mikko Perttunen <mperttunen@nvidia.com> | 2017-09-28 08:50:42 -0400 |
---|---|---|
committer | Thierry Reding <treding@nvidia.com> | 2017-10-20 08:19:52 -0400 |
commit | 2a79c034b579beb90b34c6942ff7d54ece5d3ea0 (patch) | |
tree | 83be3261c435d2f27eefd2ff94771552012e2590 | |
parent | eb2ee1a28db17155bcee4630e36ea1759b7e10dc (diff) |
gpu: host1x: Disassemble more instructions
The disassembler for debug dumps was missing some newer host1x opcodes.
Add disassembly support for these.
Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Reviewed-by: Dmitry Osipenko <digetx@gmail.com>
Tested-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
-rw-r--r-- | drivers/gpu/host1x/hw/debug_hw.c | 59 | ||||
-rw-r--r-- | drivers/gpu/host1x/hw/debug_hw_1x01.c | 2 | ||||
-rw-r--r-- | drivers/gpu/host1x/hw/debug_hw_1x06.c | 3 |
3 files changed, 58 insertions, 6 deletions
diff --git a/drivers/gpu/host1x/hw/debug_hw.c b/drivers/gpu/host1x/hw/debug_hw.c index 1e67667e308c..989476801f9d 100644 --- a/drivers/gpu/host1x/hw/debug_hw.c +++ b/drivers/gpu/host1x/hw/debug_hw.c | |||
@@ -30,6 +30,13 @@ enum { | |||
30 | HOST1X_OPCODE_IMM = 0x04, | 30 | HOST1X_OPCODE_IMM = 0x04, |
31 | HOST1X_OPCODE_RESTART = 0x05, | 31 | HOST1X_OPCODE_RESTART = 0x05, |
32 | HOST1X_OPCODE_GATHER = 0x06, | 32 | HOST1X_OPCODE_GATHER = 0x06, |
33 | HOST1X_OPCODE_SETSTRMID = 0x07, | ||
34 | HOST1X_OPCODE_SETAPPID = 0x08, | ||
35 | HOST1X_OPCODE_SETPYLD = 0x09, | ||
36 | HOST1X_OPCODE_INCR_W = 0x0a, | ||
37 | HOST1X_OPCODE_NONINCR_W = 0x0b, | ||
38 | HOST1X_OPCODE_GATHER_W = 0x0c, | ||
39 | HOST1X_OPCODE_RESTART_W = 0x0d, | ||
33 | HOST1X_OPCODE_EXTEND = 0x0e, | 40 | HOST1X_OPCODE_EXTEND = 0x0e, |
34 | }; | 41 | }; |
35 | 42 | ||
@@ -38,11 +45,16 @@ enum { | |||
38 | HOST1X_OPCODE_EXTEND_RELEASE_MLOCK = 0x01, | 45 | HOST1X_OPCODE_EXTEND_RELEASE_MLOCK = 0x01, |
39 | }; | 46 | }; |
40 | 47 | ||
41 | static unsigned int show_channel_command(struct output *o, u32 val) | 48 | #define INVALID_PAYLOAD 0xffffffff |
49 | |||
50 | static unsigned int show_channel_command(struct output *o, u32 val, | ||
51 | u32 *payload) | ||
42 | { | 52 | { |
43 | unsigned int mask, subop, num; | 53 | unsigned int mask, subop, num, opcode; |
54 | |||
55 | opcode = val >> 28; | ||
44 | 56 | ||
45 | switch (val >> 28) { | 57 | switch (opcode) { |
46 | case HOST1X_OPCODE_SETCLASS: | 58 | case HOST1X_OPCODE_SETCLASS: |
47 | mask = val & 0x3f; | 59 | mask = val & 0x3f; |
48 | if (mask) { | 60 | if (mask) { |
@@ -97,6 +109,44 @@ static unsigned int show_channel_command(struct output *o, u32 val) | |||
97 | val >> 14 & 0x1, val & 0x3fff); | 109 | val >> 14 & 0x1, val & 0x3fff); |
98 | return 1; | 110 | return 1; |
99 | 111 | ||
112 | #if HOST1X_HW >= 6 | ||
113 | case HOST1X_OPCODE_SETSTRMID: | ||
114 | host1x_debug_cont(o, "SETSTRMID(offset=%06x)\n", | ||
115 | val & 0x3fffff); | ||
116 | return 0; | ||
117 | |||
118 | case HOST1X_OPCODE_SETAPPID: | ||
119 | host1x_debug_cont(o, "SETAPPID(appid=%02x)\n", val & 0xff); | ||
120 | return 0; | ||
121 | |||
122 | case HOST1X_OPCODE_SETPYLD: | ||
123 | *payload = val & 0xffff; | ||
124 | host1x_debug_cont(o, "SETPYLD(data=%04x)\n", *payload); | ||
125 | return 0; | ||
126 | |||
127 | case HOST1X_OPCODE_INCR_W: | ||
128 | case HOST1X_OPCODE_NONINCR_W: | ||
129 | host1x_debug_cont(o, "%s(offset=%06x, ", | ||
130 | opcode == HOST1X_OPCODE_INCR_W ? | ||
131 | "INCR_W" : "NONINCR_W", | ||
132 | val & 0x3fffff); | ||
133 | if (*payload == 0) { | ||
134 | host1x_debug_cont(o, "[])\n"); | ||
135 | return 0; | ||
136 | } else if (*payload == INVALID_PAYLOAD) { | ||
137 | host1x_debug_cont(o, "unknown)\n"); | ||
138 | return 0; | ||
139 | } else { | ||
140 | host1x_debug_cont(o, "["); | ||
141 | return *payload; | ||
142 | } | ||
143 | |||
144 | case HOST1X_OPCODE_GATHER_W: | ||
145 | host1x_debug_cont(o, "GATHER_W(count=%04x, addr=[", | ||
146 | val & 0x3fff); | ||
147 | return 2; | ||
148 | #endif | ||
149 | |||
100 | case HOST1X_OPCODE_EXTEND: | 150 | case HOST1X_OPCODE_EXTEND: |
101 | subop = val >> 24 & 0xf; | 151 | subop = val >> 24 & 0xf; |
102 | if (subop == HOST1X_OPCODE_EXTEND_ACQUIRE_MLOCK) | 152 | if (subop == HOST1X_OPCODE_EXTEND_ACQUIRE_MLOCK) |
@@ -122,6 +172,7 @@ static void show_gather(struct output *o, phys_addr_t phys_addr, | |||
122 | /* Map dmaget cursor to corresponding mem handle */ | 172 | /* Map dmaget cursor to corresponding mem handle */ |
123 | u32 offset = phys_addr - pin_addr; | 173 | u32 offset = phys_addr - pin_addr; |
124 | unsigned int data_count = 0, i; | 174 | unsigned int data_count = 0, i; |
175 | u32 payload = INVALID_PAYLOAD; | ||
125 | 176 | ||
126 | /* | 177 | /* |
127 | * Sometimes we're given different hardware address to the same | 178 | * Sometimes we're given different hardware address to the same |
@@ -139,7 +190,7 @@ static void show_gather(struct output *o, phys_addr_t phys_addr, | |||
139 | 190 | ||
140 | if (!data_count) { | 191 | if (!data_count) { |
141 | host1x_debug_output(o, "%08x: %08x: ", addr, val); | 192 | host1x_debug_output(o, "%08x: %08x: ", addr, val); |
142 | data_count = show_channel_command(o, val); | 193 | data_count = show_channel_command(o, val, &payload); |
143 | } else { | 194 | } else { |
144 | host1x_debug_cont(o, "%08x%s", val, | 195 | host1x_debug_cont(o, "%08x%s", val, |
145 | data_count > 1 ? ", " : "])\n"); | 196 | data_count > 1 ? ", " : "])\n"); |
diff --git a/drivers/gpu/host1x/hw/debug_hw_1x01.c b/drivers/gpu/host1x/hw/debug_hw_1x01.c index 09e1aa7bb5dd..8790d5fd5f20 100644 --- a/drivers/gpu/host1x/hw/debug_hw_1x01.c +++ b/drivers/gpu/host1x/hw/debug_hw_1x01.c | |||
@@ -112,7 +112,7 @@ static void host1x_debug_show_channel_fifo(struct host1x *host, | |||
112 | 112 | ||
113 | if (!data_count) { | 113 | if (!data_count) { |
114 | host1x_debug_output(o, "%08x: ", val); | 114 | host1x_debug_output(o, "%08x: ", val); |
115 | data_count = show_channel_command(o, val); | 115 | data_count = show_channel_command(o, val, NULL); |
116 | } else { | 116 | } else { |
117 | host1x_debug_cont(o, "%08x%s", val, | 117 | host1x_debug_cont(o, "%08x%s", val, |
118 | data_count > 1 ? ", " : "])\n"); | 118 | data_count > 1 ? ", " : "])\n"); |
diff --git a/drivers/gpu/host1x/hw/debug_hw_1x06.c b/drivers/gpu/host1x/hw/debug_hw_1x06.c index bd89da5dc64c..b503c740c022 100644 --- a/drivers/gpu/host1x/hw/debug_hw_1x06.c +++ b/drivers/gpu/host1x/hw/debug_hw_1x06.c | |||
@@ -63,6 +63,7 @@ static void host1x_debug_show_channel_fifo(struct host1x *host, | |||
63 | struct output *o) | 63 | struct output *o) |
64 | { | 64 | { |
65 | u32 val, rd_ptr, wr_ptr, start, end; | 65 | u32 val, rd_ptr, wr_ptr, start, end; |
66 | u32 payload = INVALID_PAYLOAD; | ||
66 | unsigned int data_count = 0; | 67 | unsigned int data_count = 0; |
67 | 68 | ||
68 | host1x_debug_output(o, "%u: fifo:\n", ch->id); | 69 | host1x_debug_output(o, "%u: fifo:\n", ch->id); |
@@ -107,7 +108,7 @@ static void host1x_debug_show_channel_fifo(struct host1x *host, | |||
107 | if (!data_count) { | 108 | if (!data_count) { |
108 | host1x_debug_output(o, "%03x 0x%08x: ", | 109 | host1x_debug_output(o, "%03x 0x%08x: ", |
109 | rd_ptr - start, val); | 110 | rd_ptr - start, val); |
110 | data_count = show_channel_command(o, val); | 111 | data_count = show_channel_command(o, val, &payload); |
111 | } else { | 112 | } else { |
112 | host1x_debug_cont(o, "%08x%s", val, | 113 | host1x_debug_cont(o, "%08x%s", val, |
113 | data_count > 1 ? ", " : "])\n"); | 114 | data_count > 1 ? ", " : "])\n"); |