diff options
author | Tadeusz Struk <tadeusz.struk@intel.com> | 2015-12-23 10:36:28 -0500 |
---|---|---|
committer | Herbert Xu <herbert@gondor.apana.org.au> | 2015-12-25 08:41:09 -0500 |
commit | 2a5de720dcecbc7ba998bc1ae8f7b9cd7cb81654 (patch) | |
tree | 9f58841998614ccafd3f4d6009251da11dce1a7f | |
parent | 1fa844e2ff914370a1c7f14bb854f220bfe87c73 (diff) |
crypto: qat - fix SKU definiftion for c3xxx dev
c3xxx doesn't have the esram BAR and only has 6 ue.
Signed-off-by: Tadeusz Struk <tadeusz.struk@intel.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
-rw-r--r-- | drivers/crypto/qat/qat_c3xxx/adf_c3xxx_hw_data.c | 22 | ||||
-rw-r--r-- | drivers/crypto/qat/qat_c3xxx/adf_c3xxx_hw_data.h | 5 |
2 files changed, 8 insertions, 19 deletions
diff --git a/drivers/crypto/qat/qat_c3xxx/adf_c3xxx_hw_data.c b/drivers/crypto/qat/qat_c3xxx/adf_c3xxx_hw_data.c index bda8f9f789b9..c5bd5a9abc4d 100644 --- a/drivers/crypto/qat/qat_c3xxx/adf_c3xxx_hw_data.c +++ b/drivers/crypto/qat/qat_c3xxx/adf_c3xxx_hw_data.c | |||
@@ -50,14 +50,9 @@ | |||
50 | #include "adf_c3xxx_hw_data.h" | 50 | #include "adf_c3xxx_hw_data.h" |
51 | 51 | ||
52 | /* Worker thread to service arbiter mappings based on dev SKUs */ | 52 | /* Worker thread to service arbiter mappings based on dev SKUs */ |
53 | static const u32 thrd_to_arb_map_8_me_sku[] = { | 53 | static const u32 thrd_to_arb_map_6_me_sku[] = { |
54 | 0x10000888, 0x11000888, 0x10000888, 0x11000888, 0x10000888, | 54 | 0x12222AAA, 0x11222AAA, 0x12222AAA, |
55 | 0x11000888, 0x10000888, 0x11000888, 0, 0 | 55 | 0x11222AAA, 0x12222AAA, 0x11222AAA |
56 | }; | ||
57 | |||
58 | static const u32 thrd_to_arb_map_10_me_sku[] = { | ||
59 | 0x12222AAA, 0x11222AAA, 0x12222AAA, 0x11222AAA, 0x12222AAA, | ||
60 | 0x11222AAA, 0x12222AAA, 0x11222AAA, 0x12222AAA, 0x11222AAA | ||
61 | }; | 56 | }; |
62 | 57 | ||
63 | static struct adf_hw_device_class c3xxx_class = { | 58 | static struct adf_hw_device_class c3xxx_class = { |
@@ -117,16 +112,14 @@ static u32 get_etr_bar_id(struct adf_hw_device_data *self) | |||
117 | 112 | ||
118 | static u32 get_sram_bar_id(struct adf_hw_device_data *self) | 113 | static u32 get_sram_bar_id(struct adf_hw_device_data *self) |
119 | { | 114 | { |
120 | return ADF_C3XXX_SRAM_BAR; | 115 | return 0; |
121 | } | 116 | } |
122 | 117 | ||
123 | static enum dev_sku_info get_sku(struct adf_hw_device_data *self) | 118 | static enum dev_sku_info get_sku(struct adf_hw_device_data *self) |
124 | { | 119 | { |
125 | int aes = get_num_aes(self); | 120 | int aes = get_num_aes(self); |
126 | 121 | ||
127 | if (aes == 8) | 122 | if (aes == 6) |
128 | return DEV_SKU_2; | ||
129 | else if (aes == 10) | ||
130 | return DEV_SKU_4; | 123 | return DEV_SKU_4; |
131 | 124 | ||
132 | return DEV_SKU_UNKNOWN; | 125 | return DEV_SKU_UNKNOWN; |
@@ -136,11 +129,8 @@ static void adf_get_arbiter_mapping(struct adf_accel_dev *accel_dev, | |||
136 | u32 const **arb_map_config) | 129 | u32 const **arb_map_config) |
137 | { | 130 | { |
138 | switch (accel_dev->accel_pci_dev.sku) { | 131 | switch (accel_dev->accel_pci_dev.sku) { |
139 | case DEV_SKU_2: | ||
140 | *arb_map_config = thrd_to_arb_map_8_me_sku; | ||
141 | break; | ||
142 | case DEV_SKU_4: | 132 | case DEV_SKU_4: |
143 | *arb_map_config = thrd_to_arb_map_10_me_sku; | 133 | *arb_map_config = thrd_to_arb_map_6_me_sku; |
144 | break; | 134 | break; |
145 | default: | 135 | default: |
146 | dev_err(&GET_DEV(accel_dev), | 136 | dev_err(&GET_DEV(accel_dev), |
diff --git a/drivers/crypto/qat/qat_c3xxx/adf_c3xxx_hw_data.h b/drivers/crypto/qat/qat_c3xxx/adf_c3xxx_hw_data.h index f2fa23458c8c..2f2681d3458a 100644 --- a/drivers/crypto/qat/qat_c3xxx/adf_c3xxx_hw_data.h +++ b/drivers/crypto/qat/qat_c3xxx/adf_c3xxx_hw_data.h | |||
@@ -48,9 +48,8 @@ | |||
48 | #define ADF_C3XXX_HW_DATA_H_ | 48 | #define ADF_C3XXX_HW_DATA_H_ |
49 | 49 | ||
50 | /* PCIe configuration space */ | 50 | /* PCIe configuration space */ |
51 | #define ADF_C3XXX_SRAM_BAR 0 | 51 | #define ADF_C3XXX_PMISC_BAR 0 |
52 | #define ADF_C3XXX_PMISC_BAR 1 | 52 | #define ADF_C3XXX_ETR_BAR 1 |
53 | #define ADF_C3XXX_ETR_BAR 2 | ||
54 | #define ADF_C3XXX_RX_RINGS_OFFSET 8 | 53 | #define ADF_C3XXX_RX_RINGS_OFFSET 8 |
55 | #define ADF_C3XXX_TX_RINGS_MASK 0xFF | 54 | #define ADF_C3XXX_TX_RINGS_MASK 0xFF |
56 | #define ADF_C3XXX_MAX_ACCELERATORS 3 | 55 | #define ADF_C3XXX_MAX_ACCELERATORS 3 |