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authorMasahiro Yamada <yamada.masahiro@socionext.com>2017-10-04 22:30:57 -0400
committerPhilipp Zabel <p.zabel@pengutronix.de>2017-10-05 04:24:14 -0400
commit2a158f888853cb11140532be79883c8faf31c83d (patch)
tree9b208c46bc17cfd9836a0cf453b95a89d8e3c448
parent7f4fbf79f4d4c00466e1b4158b17c5a095c83f2c (diff)
reset: uniphier: add PXs3 reset data
Add basic reset data for Socionext's new SoC PXs3. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
-rw-r--r--Documentation/devicetree/bindings/reset/uniphier-reset.txt3
-rw-r--r--drivers/reset/reset-uniphier.c26
2 files changed, 29 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/reset/uniphier-reset.txt b/Documentation/devicetree/bindings/reset/uniphier-reset.txt
index 68a6f487c409..93efed629900 100644
--- a/Documentation/devicetree/bindings/reset/uniphier-reset.txt
+++ b/Documentation/devicetree/bindings/reset/uniphier-reset.txt
@@ -13,6 +13,7 @@ Required properties:
13 "socionext,uniphier-pxs2-reset" - for PXs2/LD6b SoC 13 "socionext,uniphier-pxs2-reset" - for PXs2/LD6b SoC
14 "socionext,uniphier-ld11-reset" - for LD11 SoC 14 "socionext,uniphier-ld11-reset" - for LD11 SoC
15 "socionext,uniphier-ld20-reset" - for LD20 SoC 15 "socionext,uniphier-ld20-reset" - for LD20 SoC
16 "socionext,uniphier-pxs3-reset" - for PXs3 SoC
16- #reset-cells: should be 1. 17- #reset-cells: should be 1.
17 18
18Example: 19Example:
@@ -44,6 +45,7 @@ Required properties:
44 "socionext,uniphier-ld11-mio-reset" - for LD11 SoC (MIO) 45 "socionext,uniphier-ld11-mio-reset" - for LD11 SoC (MIO)
45 "socionext,uniphier-ld11-sd-reset" - for LD11 SoC (SD) 46 "socionext,uniphier-ld11-sd-reset" - for LD11 SoC (SD)
46 "socionext,uniphier-ld20-sd-reset" - for LD20 SoC 47 "socionext,uniphier-ld20-sd-reset" - for LD20 SoC
48 "socionext,uniphier-pxs3-sd-reset" - for PXs3 SoC
47- #reset-cells: should be 1. 49- #reset-cells: should be 1.
48 50
49Example: 51Example:
@@ -74,6 +76,7 @@ Required properties:
74 "socionext,uniphier-pxs2-peri-reset" - for PXs2/LD6b SoC 76 "socionext,uniphier-pxs2-peri-reset" - for PXs2/LD6b SoC
75 "socionext,uniphier-ld11-peri-reset" - for LD11 SoC 77 "socionext,uniphier-ld11-peri-reset" - for LD11 SoC
76 "socionext,uniphier-ld20-peri-reset" - for LD20 SoC 78 "socionext,uniphier-ld20-peri-reset" - for LD20 SoC
79 "socionext,uniphier-pxs3-peri-reset" - for PXs3 SoC
77- #reset-cells: should be 1. 80- #reset-cells: should be 1.
78 81
79Example: 82Example:
diff --git a/drivers/reset/reset-uniphier.c b/drivers/reset/reset-uniphier.c
index 6e40f7db4243..e8bb023ff15e 100644
--- a/drivers/reset/reset-uniphier.c
+++ b/drivers/reset/reset-uniphier.c
@@ -118,6 +118,20 @@ static const struct uniphier_reset_data uniphier_ld20_sys_reset_data[] = {
118 UNIPHIER_RESET_END, 118 UNIPHIER_RESET_END,
119}; 119};
120 120
121static const struct uniphier_reset_data uniphier_pxs3_sys_reset_data[] = {
122 UNIPHIER_RESETX(2, 0x200c, 0), /* NAND */
123 UNIPHIER_RESETX(4, 0x200c, 2), /* eMMC */
124 UNIPHIER_RESETX(8, 0x200c, 12), /* STDMAC */
125 UNIPHIER_RESETX(12, 0x200c, 4), /* USB30 link (GIO0) */
126 UNIPHIER_RESETX(13, 0x200c, 5), /* USB31 link (GIO1) */
127 UNIPHIER_RESETX(16, 0x200c, 16), /* USB30-PHY0 */
128 UNIPHIER_RESETX(17, 0x200c, 18), /* USB30-PHY1 */
129 UNIPHIER_RESETX(18, 0x200c, 20), /* USB30-PHY2 */
130 UNIPHIER_RESETX(20, 0x200c, 17), /* USB31-PHY0 */
131 UNIPHIER_RESETX(21, 0x200c, 19), /* USB31-PHY1 */
132 UNIPHIER_RESET_END,
133};
134
121/* Media I/O reset data */ 135/* Media I/O reset data */
122#define UNIPHIER_MIO_RESET_SD(id, ch) \ 136#define UNIPHIER_MIO_RESET_SD(id, ch) \
123 UNIPHIER_RESETX((id), 0x110 + 0x200 * (ch), 0) 137 UNIPHIER_RESETX((id), 0x110 + 0x200 * (ch), 0)
@@ -363,6 +377,10 @@ static const struct of_device_id uniphier_reset_match[] = {
363 .compatible = "socionext,uniphier-ld20-reset", 377 .compatible = "socionext,uniphier-ld20-reset",
364 .data = uniphier_ld20_sys_reset_data, 378 .data = uniphier_ld20_sys_reset_data,
365 }, 379 },
380 {
381 .compatible = "socionext,uniphier-pxs3-reset",
382 .data = uniphier_pxs3_sys_reset_data,
383 },
366 /* Media I/O reset, SD reset */ 384 /* Media I/O reset, SD reset */
367 { 385 {
368 .compatible = "socionext,uniphier-ld4-mio-reset", 386 .compatible = "socionext,uniphier-ld4-mio-reset",
@@ -396,6 +414,10 @@ static const struct of_device_id uniphier_reset_match[] = {
396 .compatible = "socionext,uniphier-ld20-sd-reset", 414 .compatible = "socionext,uniphier-ld20-sd-reset",
397 .data = uniphier_pro5_sd_reset_data, 415 .data = uniphier_pro5_sd_reset_data,
398 }, 416 },
417 {
418 .compatible = "socionext,uniphier-pxs3-sd-reset",
419 .data = uniphier_pro5_sd_reset_data,
420 },
399 /* Peripheral reset */ 421 /* Peripheral reset */
400 { 422 {
401 .compatible = "socionext,uniphier-ld4-peri-reset", 423 .compatible = "socionext,uniphier-ld4-peri-reset",
@@ -425,6 +447,10 @@ static const struct of_device_id uniphier_reset_match[] = {
425 .compatible = "socionext,uniphier-ld20-peri-reset", 447 .compatible = "socionext,uniphier-ld20-peri-reset",
426 .data = uniphier_pro4_peri_reset_data, 448 .data = uniphier_pro4_peri_reset_data,
427 }, 449 },
450 {
451 .compatible = "socionext,uniphier-pxs3-peri-reset",
452 .data = uniphier_pro4_peri_reset_data,
453 },
428 /* Analog signal amplifiers reset */ 454 /* Analog signal amplifiers reset */
429 { 455 {
430 .compatible = "socionext,uniphier-ld11-adamv-reset", 456 .compatible = "socionext,uniphier-ld11-adamv-reset",