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authorMasahiro Yamada <yamada.masahiro@socionext.com>2017-11-07 03:14:12 -0500
committerLee Jones <lee.jones@linaro.org>2018-01-08 06:03:34 -0500
commit299fad6b9b6e4b50929861c701af64a36cde0f31 (patch)
tree6cbd35d6bf510a1b64e5c4d15bf025945581c997
parentd501ff903bdd735b215bded10958d8f794ca0339 (diff)
mfd: tmio: Move register macros to tmio_core.c
These registers are only used in drivers/mfd/tmio_core.c Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Lee Jones <lee.jones@linaro.org>
-rw-r--r--drivers/mfd/tmio_core.c20
-rw-r--r--include/linux/mfd/tmio.h20
2 files changed, 20 insertions, 20 deletions
diff --git a/drivers/mfd/tmio_core.c b/drivers/mfd/tmio_core.c
index 83af78c1b0eb..ebf54cc28f7a 100644
--- a/drivers/mfd/tmio_core.c
+++ b/drivers/mfd/tmio_core.c
@@ -9,6 +9,26 @@
9#include <linux/export.h> 9#include <linux/export.h>
10#include <linux/mfd/tmio.h> 10#include <linux/mfd/tmio.h>
11 11
12#define CNF_CMD 0x04
13#define CNF_CTL_BASE 0x10
14#define CNF_INT_PIN 0x3d
15#define CNF_STOP_CLK_CTL 0x40
16#define CNF_GCLK_CTL 0x41
17#define CNF_SD_CLK_MODE 0x42
18#define CNF_PIN_STATUS 0x44
19#define CNF_PWR_CTL_1 0x48
20#define CNF_PWR_CTL_2 0x49
21#define CNF_PWR_CTL_3 0x4a
22#define CNF_CARD_DETECT_MODE 0x4c
23#define CNF_SD_SLOT 0x50
24#define CNF_EXT_GCLK_CTL_1 0xf0
25#define CNF_EXT_GCLK_CTL_2 0xf1
26#define CNF_EXT_GCLK_CTL_3 0xf9
27#define CNF_SD_LED_EN_1 0xfa
28#define CNF_SD_LED_EN_2 0xfe
29
30#define SDCREN 0x2 /* Enable access to MMC CTL regs. (flag in COMMAND_REG)*/
31
12int tmio_core_mmc_enable(void __iomem *cnf, int shift, unsigned long base) 32int tmio_core_mmc_enable(void __iomem *cnf, int shift, unsigned long base)
13{ 33{
14 /* Enable the MMC/SD Control registers */ 34 /* Enable the MMC/SD Control registers */
diff --git a/include/linux/mfd/tmio.h b/include/linux/mfd/tmio.h
index e1cfe9194129..396a103c8bc6 100644
--- a/include/linux/mfd/tmio.h
+++ b/include/linux/mfd/tmio.h
@@ -25,26 +25,6 @@
25 writew((val) >> 16, (addr) + 2); \ 25 writew((val) >> 16, (addr) + 2); \
26 } while (0) 26 } while (0)
27 27
28#define CNF_CMD 0x04
29#define CNF_CTL_BASE 0x10
30#define CNF_INT_PIN 0x3d
31#define CNF_STOP_CLK_CTL 0x40
32#define CNF_GCLK_CTL 0x41
33#define CNF_SD_CLK_MODE 0x42
34#define CNF_PIN_STATUS 0x44
35#define CNF_PWR_CTL_1 0x48
36#define CNF_PWR_CTL_2 0x49
37#define CNF_PWR_CTL_3 0x4a
38#define CNF_CARD_DETECT_MODE 0x4c
39#define CNF_SD_SLOT 0x50
40#define CNF_EXT_GCLK_CTL_1 0xf0
41#define CNF_EXT_GCLK_CTL_2 0xf1
42#define CNF_EXT_GCLK_CTL_3 0xf9
43#define CNF_SD_LED_EN_1 0xfa
44#define CNF_SD_LED_EN_2 0xfe
45
46#define SDCREN 0x2 /* Enable access to MMC CTL regs. (flag in COMMAND_REG)*/
47
48#define sd_config_write8(base, shift, reg, val) \ 28#define sd_config_write8(base, shift, reg, val) \
49 tmio_iowrite8((val), (base) + ((reg) << (shift))) 29 tmio_iowrite8((val), (base) + ((reg) << (shift)))
50#define sd_config_write16(base, shift, reg, val) \ 30#define sd_config_write16(base, shift, reg, val) \