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authorLinus Torvalds <torvalds@linux-foundation.org>2015-02-21 15:41:50 -0500
committerLinus Torvalds <torvalds@linux-foundation.org>2015-02-21 15:41:50 -0500
commit295324556c427d60b41668ab81a43f604533f456 (patch)
treea9a9acc5f790ba7093ee61a295bba7ac1f54a298
parent18a8d49973667aa016e68826eeb374788b7c63b0 (diff)
parent0d8fb59924cf20e7bef2c41f8d4e87127f573546 (diff)
Merge branch 'i2c/for-3.20' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux
Pull i2c updates from Wolfram Sang: "Summary: - legacy PM code removed from the core, there were no users anymore (thanks to Lars-Peter Clausen) - new driver for Broadcom iProc - bigger driver updates for designware, rk3x, cadence, ocores - a bunch of smaller updates and bugfixes" * 'i2c/for-3.20' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux: (31 commits) i2c: ocores: rework clk code to handle NULL cookie i2c: designware-baytrail: another fixup for proper Kconfig dependencies i2c: fix reference to functionality constants definition i2c: iproc: Add Broadcom iProc I2C Driver i2c: designware-pci: update Intel copyright line i2c: ocores: add common clock support i2c: hix5hd2: add COMPILE_TEST i2c: clarify comments about the dev_released completion i2c: ocores: fix clock-frequency binding usage i2c: tegra: Maintain CPU endianness i2c: designware-baytrail: use proper Kconfig dependencies i2c: designware: Do not calculate SCL timing parameters needlessly i2c: do not try to load modules for of-registered devices i2c: designware: Add Intel Baytrail PMIC I2C bus support i2c: designware: Add i2c bus locking support of: i2c: Add i2c-mux-idle-disconnect DT property to PCA954x mux driver i2c: designware: use {readl|writel}_relaxed instead of readl/writel i2c: designware-pci: no need to provide clk_khz i2c: designware-pci: remove Moorestown support i2c: imx: whitespace and checkpatch cleanup ...
Diffstat
-rw-r--r--Documentation/devicetree/bindings/i2c/brcm,iproc-i2c.txt37
-rw-r--r--Documentation/devicetree/bindings/i2c/i2c-mux-pca954x.txt3
-rw-r--r--Documentation/devicetree/bindings/i2c/i2c-ocores.txt42
-rw-r--r--Documentation/devicetree/bindings/i2c/i2c-rk3x.txt14
-rw-r--r--Documentation/devicetree/bindings/i2c/trivial-devices.txt5
-rw-r--r--Documentation/i2c/functionality2
-rw-r--r--drivers/i2c/busses/Kconfig22
-rw-r--r--drivers/i2c/busses/Makefile2
-rw-r--r--drivers/i2c/busses/i2c-bcm-iproc.c461
-rw-r--r--drivers/i2c/busses/i2c-cadence.c189
-rw-r--r--drivers/i2c/busses/i2c-designware-baytrail.c160
-rw-r--r--drivers/i2c/busses/i2c-designware-core.c83
-rw-r--r--drivers/i2c/busses/i2c-designware-core.h12
-rw-r--r--drivers/i2c/busses/i2c-designware-pcidrv.c41
-rw-r--r--drivers/i2c/busses/i2c-designware-platdrv.c20
-rw-r--r--drivers/i2c/busses/i2c-imx.c33
-rw-r--r--drivers/i2c/busses/i2c-ocores.c91
-rw-r--r--drivers/i2c/busses/i2c-pmcmsp.c7
-rw-r--r--drivers/i2c/busses/i2c-rk3x.c99
-rw-r--r--drivers/i2c/busses/i2c-tegra.c2
-rw-r--r--drivers/i2c/i2c-core.c162
-rw-r--r--drivers/i2c/muxes/i2c-mux-pca954x.c11
-rw-r--r--include/linux/i2c.h4
23 files changed, 1139 insertions, 363 deletions
diff --git a/Documentation/devicetree/bindings/i2c/brcm,iproc-i2c.txt b/Documentation/devicetree/bindings/i2c/brcm,iproc-i2c.txt
new file mode 100644
index 000000000000..81f982ccca31
--- /dev/null
+++ b/Documentation/devicetree/bindings/i2c/brcm,iproc-i2c.txt
@@ -0,0 +1,37 @@
1Broadcom iProc I2C controller
2
3Required properties:
4
5- compatible:
6 Must be "brcm,iproc-i2c"
7
8- reg:
9 Define the base and range of the I/O address space that contain the iProc
10 I2C controller registers
11
12- interrupts:
13 Should contain the I2C interrupt
14
15- clock-frequency:
16 This is the I2C bus clock. Need to be either 100000 or 400000
17
18- #address-cells:
19 Always 1 (for I2C addresses)
20
21- #size-cells:
22 Always 0
23
24Example:
25 i2c0: i2c@18008000 {
26 compatible = "brcm,iproc-i2c";
27 reg = <0x18008000 0x100>;
28 #address-cells = <1>;
29 #size-cells = <0>;
30 interrupts = <GIC_SPI 85 IRQ_TYPE_NONE>;
31 clock-frequency = <100000>;
32
33 codec: wm8750@1a {
34 compatible = "wlf,wm8750";
35 reg = <0x1a>;
36 };
37 };
diff --git a/Documentation/devicetree/bindings/i2c/i2c-mux-pca954x.txt b/Documentation/devicetree/bindings/i2c/i2c-mux-pca954x.txt
index 34a3fb6f8488..cf53d5fba20a 100644
--- a/Documentation/devicetree/bindings/i2c/i2c-mux-pca954x.txt
+++ b/Documentation/devicetree/bindings/i2c/i2c-mux-pca954x.txt
@@ -16,6 +16,9 @@ Required Properties:
16Optional Properties: 16Optional Properties:
17 17
18 - reset-gpios: Reference to the GPIO connected to the reset input. 18 - reset-gpios: Reference to the GPIO connected to the reset input.
19 - i2c-mux-idle-disconnect: Boolean; if defined, forces mux to disconnect all
20 children in idle state. This is necessary for example, if there are several
21 multiplexers on the bus and the devices behind them use same I2C addresses.
19 22
20 23
21Example: 24Example:
diff --git a/Documentation/devicetree/bindings/i2c/i2c-ocores.txt b/Documentation/devicetree/bindings/i2c/i2c-ocores.txt
index 1637c298a1b3..17bef9a34e50 100644
--- a/Documentation/devicetree/bindings/i2c/i2c-ocores.txt
+++ b/Documentation/devicetree/bindings/i2c/i2c-ocores.txt
@@ -4,24 +4,60 @@ Required properties:
4- compatible : "opencores,i2c-ocores" or "aeroflexgaisler,i2cmst" 4- compatible : "opencores,i2c-ocores" or "aeroflexgaisler,i2cmst"
5- reg : bus address start and address range size of device 5- reg : bus address start and address range size of device
6- interrupts : interrupt number 6- interrupts : interrupt number
7- clock-frequency : frequency of bus clock in Hz 7- clocks : handle to the controller clock; see the note below.
8 Mutually exclusive with opencores,ip-clock-frequency
9- opencores,ip-clock-frequency: frequency of the controller clock in Hz;
10 see the note below. Mutually exclusive with clocks
8- #address-cells : should be <1> 11- #address-cells : should be <1>
9- #size-cells : should be <0> 12- #size-cells : should be <0>
10 13
11Optional properties: 14Optional properties:
15- clock-frequency : frequency of bus clock in Hz; see the note below.
16 Defaults to 100 KHz when the property is not specified
12- reg-shift : device register offsets are shifted by this value 17- reg-shift : device register offsets are shifted by this value
13- reg-io-width : io register width in bytes (1, 2 or 4) 18- reg-io-width : io register width in bytes (1, 2 or 4)
14- regstep : deprecated, use reg-shift above 19- regstep : deprecated, use reg-shift above
15 20
16Example: 21Note
22clock-frequency property is meant to control the bus frequency for i2c bus
23drivers, but it was incorrectly used to specify i2c controller input clock
24frequency. So the following rules are set to fix this situation:
25- if clock-frequency is present and neither opencores,ip-clock-frequency nor
26 clocks are, then clock-frequency specifies i2c controller clock frequency.
27 This is to keep backwards compatibility with setups using old DTB. i2c bus
28 frequency is fixed at 100 KHz.
29- if clocks is present it specifies i2c controller clock. clock-frequency
30 property specifies i2c bus frequency.
31- if opencores,ip-clock-frequency is present it specifies i2c controller
32 clock frequency. clock-frequency property specifies i2c bus frequency.
17 33
34Examples:
35
36 i2c0: ocores@a0000000 {
37 #address-cells = <1>;
38 #size-cells = <0>;
39 compatible = "opencores,i2c-ocores";
40 reg = <0xa0000000 0x8>;
41 interrupts = <10>;
42 opencores,ip-clock-frequency = <20000000>;
43
44 reg-shift = <0>; /* 8 bit registers */
45 reg-io-width = <1>; /* 8 bit read/write */
46
47 dummy@60 {
48 compatible = "dummy";
49 reg = <0x60>;
50 };
51 };
52or
18 i2c0: ocores@a0000000 { 53 i2c0: ocores@a0000000 {
19 #address-cells = <1>; 54 #address-cells = <1>;
20 #size-cells = <0>; 55 #size-cells = <0>;
21 compatible = "opencores,i2c-ocores"; 56 compatible = "opencores,i2c-ocores";
22 reg = <0xa0000000 0x8>; 57 reg = <0xa0000000 0x8>;
23 interrupts = <10>; 58 interrupts = <10>;
24 clock-frequency = <20000000>; 59 clocks = <&osc>;
60 clock-frequency = <400000>; /* i2c bus frequency 400 KHz */
25 61
26 reg-shift = <0>; /* 8 bit registers */ 62 reg-shift = <0>; /* 8 bit registers */
27 reg-io-width = <1>; /* 8 bit read/write */ 63 reg-io-width = <1>; /* 8 bit read/write */
diff --git a/Documentation/devicetree/bindings/i2c/i2c-rk3x.txt b/Documentation/devicetree/bindings/i2c/i2c-rk3x.txt
index dde6c22ce91a..f0d71bc52e64 100644
--- a/Documentation/devicetree/bindings/i2c/i2c-rk3x.txt
+++ b/Documentation/devicetree/bindings/i2c/i2c-rk3x.txt
@@ -21,6 +21,17 @@ Required on RK3066, RK3188 :
21Optional properties : 21Optional properties :
22 22
23 - clock-frequency : SCL frequency to use (in Hz). If omitted, 100kHz is used. 23 - clock-frequency : SCL frequency to use (in Hz). If omitted, 100kHz is used.
24 - i2c-scl-rising-time-ns : Number of nanoseconds the SCL signal takes to rise
25 (t(r) in I2C specification). If not specified this is assumed to be
26 the maximum the specification allows(1000 ns for Standard-mode,
27 300 ns for Fast-mode) which might cause slightly slower communication.
28 - i2c-scl-falling-time-ns : Number of nanoseconds the SCL signal takes to fall
29 (t(f) in the I2C specification). If not specified this is assumed to
30 be the maximum the specification allows (300 ns) which might cause
31 slightly slower communication.
32 - i2c-sda-falling-time-ns : Number of nanoseconds the SDA signal takes to fall
33 (t(f) in the I2C specification). If not specified we'll use the SCL
34 value since they are the same in nearly all cases.
24 35
25Example: 36Example:
26 37
@@ -39,4 +50,7 @@ i2c0: i2c@2002d000 {
39 50
40 clock-names = "i2c"; 51 clock-names = "i2c";
41 clocks = <&cru PCLK_I2C0>; 52 clocks = <&cru PCLK_I2C0>;
53
54 i2c-scl-rising-time-ns = <800>;
55 i2c-scl-falling-time-ns = <100>;
42}; 56};
diff --git a/Documentation/devicetree/bindings/i2c/trivial-devices.txt b/Documentation/devicetree/bindings/i2c/trivial-devices.txt
index 4dcd88d5f7ca..aaa8325004d2 100644
--- a/Documentation/devicetree/bindings/i2c/trivial-devices.txt
+++ b/Documentation/devicetree/bindings/i2c/trivial-devices.txt
@@ -61,9 +61,8 @@ fsl,sgtl5000 SGTL5000: Ultra Low-Power Audio Codec
61gmt,g751 G751: Digital Temperature Sensor and Thermal Watchdog with Two-Wire Interface 61gmt,g751 G751: Digital Temperature Sensor and Thermal Watchdog with Two-Wire Interface
62infineon,slb9635tt Infineon SLB9635 (Soft-) I2C TPM (old protocol, max 100khz) 62infineon,slb9635tt Infineon SLB9635 (Soft-) I2C TPM (old protocol, max 100khz)
63infineon,slb9645tt Infineon SLB9645 I2C TPM (new protocol, max 400khz) 63infineon,slb9645tt Infineon SLB9645 I2C TPM (new protocol, max 400khz)
64isl,isl12057 Intersil ISL12057 I2C RTC Chip 64isil,isl12057 Intersil ISL12057 I2C RTC Chip
65isil,isl29028 (deprecated, use isl) 65isil,isl29028 Intersil ISL29028 Ambient Light and Proximity Sensor
66isl,isl29028 Intersil ISL29028 Ambient Light and Proximity Sensor
67maxim,ds1050 5 Bit Programmable, Pulse-Width Modulator 66maxim,ds1050 5 Bit Programmable, Pulse-Width Modulator
68maxim,max1237 Low-Power, 4-/12-Channel, 2-Wire Serial, 12-Bit ADCs 67maxim,max1237 Low-Power, 4-/12-Channel, 2-Wire Serial, 12-Bit ADCs
69maxim,max6625 9-Bit/12-Bit Temperature Sensors with I²C-Compatible Serial Interface 68maxim,max6625 9-Bit/12-Bit Temperature Sensors with I²C-Compatible Serial Interface
diff --git a/Documentation/i2c/functionality b/Documentation/i2c/functionality
index 4556a3eb87c4..4aae8ed15873 100644
--- a/Documentation/i2c/functionality
+++ b/Documentation/i2c/functionality
@@ -12,7 +12,7 @@ FUNCTIONALITY CONSTANTS
12----------------------- 12-----------------------
13 13
14For the most up-to-date list of functionality constants, please check 14For the most up-to-date list of functionality constants, please check
15<linux/i2c.h>! 15<uapi/linux/i2c.h>!
16 16
17 I2C_FUNC_I2C Plain i2c-level commands (Pure SMBus 17 I2C_FUNC_I2C Plain i2c-level commands (Pure SMBus
18 adapters typically can not do these) 18 adapters typically can not do these)
diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
index ab838d9e28b6..22da9c2ffa22 100644
--- a/drivers/i2c/busses/Kconfig
+++ b/drivers/i2c/busses/Kconfig
@@ -79,7 +79,7 @@ config I2C_AMD8111
79 79
80config I2C_HIX5HD2 80config I2C_HIX5HD2
81 tristate "Hix5hd2 high-speed I2C driver" 81 tristate "Hix5hd2 high-speed I2C driver"
82 depends on ARCH_HIX5HD2 82 depends on ARCH_HIX5HD2 || COMPILE_TEST
83 help 83 help
84 Say Y here to include support for high-speed I2C controller in the 84 Say Y here to include support for high-speed I2C controller in the
85 Hisilicon based hix5hd2 SoCs. 85 Hisilicon based hix5hd2 SoCs.
@@ -372,6 +372,16 @@ config I2C_BCM2835
372 This support is also available as a module. If so, the module 372 This support is also available as a module. If so, the module
373 will be called i2c-bcm2835. 373 will be called i2c-bcm2835.
374 374
375config I2C_BCM_IPROC
376 tristate "Broadcom iProc I2C controller"
377 depends on ARCH_BCM_IPROC || COMPILE_TEST
378 default ARCH_BCM_IPROC
379 help
380 If you say yes to this option, support will be included for the
381 Broadcom iProc I2C controller.
382
383 If you don't know what to do here, say N.
384
375config I2C_BCM_KONA 385config I2C_BCM_KONA
376 tristate "BCM Kona I2C adapter" 386 tristate "BCM Kona I2C adapter"
377 depends on ARCH_BCM_MOBILE 387 depends on ARCH_BCM_MOBILE
@@ -465,6 +475,16 @@ config I2C_DESIGNWARE_PCI
465 This driver can also be built as a module. If so, the module 475 This driver can also be built as a module. If so, the module
466 will be called i2c-designware-pci. 476 will be called i2c-designware-pci.
467 477
478config I2C_DESIGNWARE_BAYTRAIL
479 bool "Intel Baytrail I2C semaphore support"
480 depends on I2C_DESIGNWARE_PLATFORM && IOSF_MBI=y && ACPI
481 help
482 This driver enables managed host access to the PMIC I2C bus on select
483 Intel BayTrail platforms using the X-Powers AXP288 PMIC. It allows
484 the host to request uninterrupted access to the PMIC's I2C bus from
485 the platform firmware controlling it. You should say Y if running on
486 a BayTrail system using the AXP288.
487
468config I2C_EFM32 488config I2C_EFM32
469 tristate "EFM32 I2C controller" 489 tristate "EFM32 I2C controller"
470 depends on ARCH_EFM32 || COMPILE_TEST 490 depends on ARCH_EFM32 || COMPILE_TEST
diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile
index 56388f658d2f..3638feb6677e 100644
--- a/drivers/i2c/busses/Makefile
+++ b/drivers/i2c/busses/Makefile
@@ -33,6 +33,7 @@ obj-$(CONFIG_I2C_AT91) += i2c-at91.o
33obj-$(CONFIG_I2C_AU1550) += i2c-au1550.o 33obj-$(CONFIG_I2C_AU1550) += i2c-au1550.o
34obj-$(CONFIG_I2C_AXXIA) += i2c-axxia.o 34obj-$(CONFIG_I2C_AXXIA) += i2c-axxia.o
35obj-$(CONFIG_I2C_BCM2835) += i2c-bcm2835.o 35obj-$(CONFIG_I2C_BCM2835) += i2c-bcm2835.o
36obj-$(CONFIG_I2C_BCM_IPROC) += i2c-bcm-iproc.o
36obj-$(CONFIG_I2C_BLACKFIN_TWI) += i2c-bfin-twi.o 37obj-$(CONFIG_I2C_BLACKFIN_TWI) += i2c-bfin-twi.o
37obj-$(CONFIG_I2C_CADENCE) += i2c-cadence.o 38obj-$(CONFIG_I2C_CADENCE) += i2c-cadence.o
38obj-$(CONFIG_I2C_CBUS_GPIO) += i2c-cbus-gpio.o 39obj-$(CONFIG_I2C_CBUS_GPIO) += i2c-cbus-gpio.o
@@ -41,6 +42,7 @@ obj-$(CONFIG_I2C_DAVINCI) += i2c-davinci.o
41obj-$(CONFIG_I2C_DESIGNWARE_CORE) += i2c-designware-core.o 42obj-$(CONFIG_I2C_DESIGNWARE_CORE) += i2c-designware-core.o
42obj-$(CONFIG_I2C_DESIGNWARE_PLATFORM) += i2c-designware-platform.o 43obj-$(CONFIG_I2C_DESIGNWARE_PLATFORM) += i2c-designware-platform.o
43i2c-designware-platform-objs := i2c-designware-platdrv.o 44i2c-designware-platform-objs := i2c-designware-platdrv.o
45i2c-designware-platform-$(CONFIG_I2C_DESIGNWARE_BAYTRAIL) += i2c-designware-baytrail.o
44obj-$(CONFIG_I2C_DESIGNWARE_PCI) += i2c-designware-pci.o 46obj-$(CONFIG_I2C_DESIGNWARE_PCI) += i2c-designware-pci.o
45i2c-designware-pci-objs := i2c-designware-pcidrv.o 47i2c-designware-pci-objs := i2c-designware-pcidrv.o
46obj-$(CONFIG_I2C_EFM32) += i2c-efm32.o 48obj-$(CONFIG_I2C_EFM32) += i2c-efm32.o
diff --git a/drivers/i2c/busses/i2c-bcm-iproc.c b/drivers/i2c/busses/i2c-bcm-iproc.c
new file mode 100644
index 000000000000..d3c89157b337
--- /dev/null
+++ b/drivers/i2c/busses/i2c-bcm-iproc.c
@@ -0,0 +1,461 @@
1/*
2 * Copyright (C) 2014 Broadcom Corporation
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License as
6 * published by the Free Software Foundation version 2.
7 *
8 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
9 * kind, whether express or implied; without even the implied warranty
10 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#include <linux/delay.h>
15#include <linux/i2c.h>
16#include <linux/interrupt.h>
17#include <linux/io.h>
18#include <linux/kernel.h>
19#include <linux/module.h>
20#include <linux/platform_device.h>
21#include <linux/slab.h>
22
23#define CFG_OFFSET 0x00
24#define CFG_RESET_SHIFT 31
25#define CFG_EN_SHIFT 30
26#define CFG_M_RETRY_CNT_SHIFT 16
27#define CFG_M_RETRY_CNT_MASK 0x0f
28
29#define TIM_CFG_OFFSET 0x04
30#define TIM_CFG_MODE_400_SHIFT 31
31
32#define M_FIFO_CTRL_OFFSET 0x0c
33#define M_FIFO_RX_FLUSH_SHIFT 31
34#define M_FIFO_TX_FLUSH_SHIFT 30
35#define M_FIFO_RX_CNT_SHIFT 16
36#define M_FIFO_RX_CNT_MASK 0x7f
37#define M_FIFO_RX_THLD_SHIFT 8
38#define M_FIFO_RX_THLD_MASK 0x3f
39
40#define M_CMD_OFFSET 0x30
41#define M_CMD_START_BUSY_SHIFT 31
42#define M_CMD_STATUS_SHIFT 25
43#define M_CMD_STATUS_MASK 0x07
44#define M_CMD_STATUS_SUCCESS 0x0
45#define M_CMD_STATUS_LOST_ARB 0x1
46#define M_CMD_STATUS_NACK_ADDR 0x2
47#define M_CMD_STATUS_NACK_DATA 0x3
48#define M_CMD_STATUS_TIMEOUT 0x4
49#define M_CMD_PROTOCOL_SHIFT 9
50#define M_CMD_PROTOCOL_MASK 0xf
51#define M_CMD_PROTOCOL_BLK_WR 0x7
52#define M_CMD_PROTOCOL_BLK_RD 0x8
53#define M_CMD_PEC_SHIFT 8
54#define M_CMD_RD_CNT_SHIFT 0
55#define M_CMD_RD_CNT_MASK 0xff
56
57#define IE_OFFSET 0x38
58#define IE_M_RX_FIFO_FULL_SHIFT 31
59#define IE_M_RX_THLD_SHIFT 30
60#define IE_M_START_BUSY_SHIFT 28
61
62#define IS_OFFSET 0x3c
63#define IS_M_RX_FIFO_FULL_SHIFT 31
64#define IS_M_RX_THLD_SHIFT 30
65#define IS_M_START_BUSY_SHIFT 28
66
67#define M_TX_OFFSET 0x40
68#define M_TX_WR_STATUS_SHIFT 31
69#define M_TX_DATA_SHIFT 0
70#define M_TX_DATA_MASK 0xff
71
72#define M_RX_OFFSET 0x44
73#define M_RX_STATUS_SHIFT 30
74#define M_RX_STATUS_MASK 0x03
75#define M_RX_PEC_ERR_SHIFT 29
76#define M_RX_DATA_SHIFT 0
77#define M_RX_DATA_MASK 0xff
78
79#define I2C_TIMEOUT_MESC 100
80#define M_TX_RX_FIFO_SIZE 64
81
82enum bus_speed_index {
83 I2C_SPD_100K = 0,
84 I2C_SPD_400K,
85};
86
87struct bcm_iproc_i2c_dev {
88 struct device *device;
89 int irq;
90
91 void __iomem *base;
92
93 struct i2c_adapter adapter;
94
95 struct completion done;
96 int xfer_is_done;
97};
98
99/*
100 * Can be expanded in the future if more interrupt status bits are utilized
101 */
102#define ISR_MASK (1 << IS_M_START_BUSY_SHIFT)
103
104static irqreturn_t bcm_iproc_i2c_isr(int irq, void *data)
105{
106 struct bcm_iproc_i2c_dev *iproc_i2c = data;
107 u32 status = readl(iproc_i2c->base + IS_OFFSET);
108
109 status &= ISR_MASK;
110
111 if (!status)
112 return IRQ_NONE;
113
114 writel(status, iproc_i2c->base + IS_OFFSET);
115 iproc_i2c->xfer_is_done = 1;
116 complete_all(&iproc_i2c->done);
117
118 return IRQ_HANDLED;
119}
120
121static int bcm_iproc_i2c_check_status(struct bcm_iproc_i2c_dev *iproc_i2c,
122 struct i2c_msg *msg)
123{
124 u32 val;
125
126 val = readl(iproc_i2c->base + M_CMD_OFFSET);
127 val = (val >> M_CMD_STATUS_SHIFT) & M_CMD_STATUS_MASK;
128
129 switch (val) {
130 case M_CMD_STATUS_SUCCESS:
131 return 0;
132
133 case M_CMD_STATUS_LOST_ARB:
134 dev_dbg(iproc_i2c->device, "lost bus arbitration\n");
135 return -EAGAIN;
136
137 case M_CMD_STATUS_NACK_ADDR:
138 dev_dbg(iproc_i2c->device, "NAK addr:0x%02x\n", msg->addr);
139 return -ENXIO;
140
141 case M_CMD_STATUS_NACK_DATA:
142 dev_dbg(iproc_i2c->device, "NAK data\n");
143 return -ENXIO;
144
145 case M_CMD_STATUS_TIMEOUT:
146 dev_dbg(iproc_i2c->device, "bus timeout\n");
147 return -ETIMEDOUT;
148
149 default:
150 dev_dbg(iproc_i2c->device, "unknown error code=%d\n", val);
151 return -EIO;
152 }
153}
154
155static int bcm_iproc_i2c_xfer_single_msg(struct bcm_iproc_i2c_dev *iproc_i2c,
156 struct i2c_msg *msg)
157{
158 int ret, i;
159 u8 addr;
160 u32 val;
161 unsigned long time_left = msecs_to_jiffies(I2C_TIMEOUT_MESC);
162
163 /* need to reserve one byte in the FIFO for the slave address */
164 if (msg->len > M_TX_RX_FIFO_SIZE - 1) {
165 dev_err(iproc_i2c->device,
166 "only support data length up to %u bytes\n",
167 M_TX_RX_FIFO_SIZE - 1);
168 return -EOPNOTSUPP;
169 }
170
171 /* check if bus is busy */
172 if (!!(readl(iproc_i2c->base + M_CMD_OFFSET) &
173 BIT(M_CMD_START_BUSY_SHIFT))) {
174 dev_warn(iproc_i2c->device, "bus is busy\n");
175 return -EBUSY;
176 }
177
178 /* format and load slave address into the TX FIFO */
179 addr = msg->addr << 1 | (msg->flags & I2C_M_RD ? 1 : 0);
180 writel(addr, iproc_i2c->base + M_TX_OFFSET);
181
182 /* for a write transaction, load data into the TX FIFO */
183 if (!(msg->flags & I2C_M_RD)) {
184 for (i = 0; i < msg->len; i++) {
185 val = msg->buf[i];
186
187 /* mark the last byte */
188 if (i == msg->len - 1)
189 val |= 1 << M_TX_WR_STATUS_SHIFT;
190
191 writel(val, iproc_i2c->base + M_TX_OFFSET);
192 }
193 }
194
195 /* mark as incomplete before starting the transaction */
196 reinit_completion(&iproc_i2c->done);
197 iproc_i2c->xfer_is_done = 0;
198
199 /*
200 * Enable the "start busy" interrupt, which will be triggered after the
201 * transaction is done, i.e., the internal start_busy bit, transitions
202 * from 1 to 0.
203 */
204 writel(1 << IE_M_START_BUSY_SHIFT, iproc_i2c->base + IE_OFFSET);
205
206 /*
207 * Now we can activate the transfer. For a read operation, specify the
208 * number of bytes to read
209 */
210 val = 1 << M_CMD_START_BUSY_SHIFT;
211 if (msg->flags & I2C_M_RD) {
212 val |= (M_CMD_PROTOCOL_BLK_RD << M_CMD_PROTOCOL_SHIFT) |
213 (msg->len << M_CMD_RD_CNT_SHIFT);
214 } else {
215 val |= (M_CMD_PROTOCOL_BLK_WR << M_CMD_PROTOCOL_SHIFT);
216 }
217 writel(val, iproc_i2c->base + M_CMD_OFFSET);
218
219 time_left = wait_for_completion_timeout(&iproc_i2c->done, time_left);
220
221 /* disable all interrupts */
222 writel(0, iproc_i2c->base + IE_OFFSET);
223 /* read it back to flush the write */
224 readl(iproc_i2c->base + IE_OFFSET);
225
226 /* make sure the interrupt handler isn't running */
227 synchronize_irq(iproc_i2c->irq);
228
229 if (!time_left && !iproc_i2c->xfer_is_done) {
230 dev_err(iproc_i2c->device, "transaction timed out\n");
231
232 /* flush FIFOs */
233 val = (1 << M_FIFO_RX_FLUSH_SHIFT) |
234 (1 << M_FIFO_TX_FLUSH_SHIFT);
235 writel(val, iproc_i2c->base + M_FIFO_CTRL_OFFSET);
236 return -ETIMEDOUT;
237 }
238
239 ret = bcm_iproc_i2c_check_status(iproc_i2c, msg);
240 if (ret) {
241 /* flush both TX/RX FIFOs */
242 val = (1 << M_FIFO_RX_FLUSH_SHIFT) |
243 (1 << M_FIFO_TX_FLUSH_SHIFT);
244 writel(val, iproc_i2c->base + M_FIFO_CTRL_OFFSET);
245 return ret;
246 }
247
248 /*
249 * For a read operation, we now need to load the data from FIFO
250 * into the memory buffer
251 */
252 if (msg->flags & I2C_M_RD) {
253 for (i = 0; i < msg->len; i++) {
254 msg->buf[i] = (readl(iproc_i2c->base + M_RX_OFFSET) >>
255 M_RX_DATA_SHIFT) & M_RX_DATA_MASK;
256 }
257 }
258
259 return 0;
260}
261
262static int bcm_iproc_i2c_xfer(struct i2c_adapter *adapter,
263 struct i2c_msg msgs[], int num)
264{
265 struct bcm_iproc_i2c_dev *iproc_i2c = i2c_get_adapdata(adapter);
266 int ret, i;
267
268 /* go through all messages */
269 for (i = 0; i < num; i++) {
270 ret = bcm_iproc_i2c_xfer_single_msg(iproc_i2c, &msgs[i]);
271 if (ret) {
272 dev_dbg(iproc_i2c->device, "xfer failed\n");
273 return ret;
274 }
275 }
276
277 return num;
278}
279
280static uint32_t bcm_iproc_i2c_functionality(struct i2c_adapter *adap)
281{
282 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
283}
284
285static const struct i2c_algorithm bcm_iproc_algo = {
286 .master_xfer = bcm_iproc_i2c_xfer,
287 .functionality = bcm_iproc_i2c_functionality,
288};
289
290static int bcm_iproc_i2c_cfg_speed(struct bcm_iproc_i2c_dev *iproc_i2c)
291{
292 unsigned int bus_speed;
293 u32 val;
294 int ret = of_property_read_u32(iproc_i2c->device->of_node,
295 "clock-frequency", &bus_speed);
296 if (ret < 0) {
297 dev_info(iproc_i2c->device,
298 "unable to interpret clock-frequency DT property\n");
299 bus_speed = 100000;
300 }
301
302 if (bus_speed < 100000) {
303 dev_err(iproc_i2c->device, "%d Hz bus speed not supported\n",
304 bus_speed);
305 dev_err(iproc_i2c->device,
306 "valid speeds are 100khz and 400khz\n");
307 return -EINVAL;
308 } else if (bus_speed < 400000) {
309 bus_speed = 100000;
310 } else {
311 bus_speed = 400000;
312 }
313
314 val = readl(iproc_i2c->base + TIM_CFG_OFFSET);
315 val &= ~(1 << TIM_CFG_MODE_400_SHIFT);
316 val |= (bus_speed == 400000) << TIM_CFG_MODE_400_SHIFT;
317 writel(val, iproc_i2c->base + TIM_CFG_OFFSET);
318
319 dev_info(iproc_i2c->device, "bus set to %u Hz\n", bus_speed);
320
321 return 0;
322}
323
324static int bcm_iproc_i2c_init(struct bcm_iproc_i2c_dev *iproc_i2c)
325{
326 u32 val;
327
328 /* put controller in reset */
329 val = readl(iproc_i2c->base + CFG_OFFSET);
330 val |= 1 << CFG_RESET_SHIFT;
331 val &= ~(1 << CFG_EN_SHIFT);
332 writel(val, iproc_i2c->base + CFG_OFFSET);
333
334 /* wait 100 usec per spec */
335 udelay(100);
336
337 /* bring controller out of reset */
338 val &= ~(1 << CFG_RESET_SHIFT);
339 writel(val, iproc_i2c->base + CFG_OFFSET);
340
341 /* flush TX/RX FIFOs and set RX FIFO threshold to zero */
342 val = (1 << M_FIFO_RX_FLUSH_SHIFT) | (1 << M_FIFO_TX_FLUSH_SHIFT);
343 writel(val, iproc_i2c->base + M_FIFO_CTRL_OFFSET);
344
345 /* disable all interrupts */
346 writel(0, iproc_i2c->base + IE_OFFSET);
347
348 /* clear all pending interrupts */
349 writel(0xffffffff, iproc_i2c->base + IS_OFFSET);
350
351 return 0;
352}
353
354static void bcm_iproc_i2c_enable_disable(struct bcm_iproc_i2c_dev *iproc_i2c,
355 bool enable)
356{
357 u32 val;
358
359 val = readl(iproc_i2c->base + CFG_OFFSET);
360 if (enable)
361 val |= BIT(CFG_EN_SHIFT);
362 else
363 val &= ~BIT(CFG_EN_SHIFT);
364 writel(val, iproc_i2c->base + CFG_OFFSET);
365}
366
367static int bcm_iproc_i2c_probe(struct platform_device *pdev)
368{
369 int irq, ret = 0;
370 struct bcm_iproc_i2c_dev *iproc_i2c;
371 struct i2c_adapter *adap;
372 struct resource *res;
373
374 iproc_i2c = devm_kzalloc(&pdev->dev, sizeof(*iproc_i2c),
375 GFP_KERNEL);
376 if (!iproc_i2c)
377 return -ENOMEM;
378
379 platform_set_drvdata(pdev, iproc_i2c);
380 iproc_i2c->device = &pdev->dev;
381 init_completion(&iproc_i2c->done);
382
383 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
384 iproc_i2c->base = devm_ioremap_resource(iproc_i2c->device, res);
385 if (IS_ERR(iproc_i2c->base))
386 return PTR_ERR(iproc_i2c->base);
387
388 ret = bcm_iproc_i2c_init(iproc_i2c);
389 if (ret)
390 return ret;
391
392 ret = bcm_iproc_i2c_cfg_speed(iproc_i2c);
393 if (ret)
394 return ret;
395
396 irq = platform_get_irq(pdev, 0);
397 if (irq <= 0) {
398 dev_err(iproc_i2c->device, "no irq resource\n");
399 return irq;
400 }
401 iproc_i2c->irq = irq;
402
403 ret = devm_request_irq(iproc_i2c->device, irq, bcm_iproc_i2c_isr, 0,
404 pdev->name, iproc_i2c);
405 if (ret < 0) {
406 dev_err(iproc_i2c->device, "unable to request irq %i\n", irq);
407 return ret;
408 }
409
410 bcm_iproc_i2c_enable_disable(iproc_i2c, true);
411
412 adap = &iproc_i2c->adapter;
413 i2c_set_adapdata(adap, iproc_i2c);
414 strlcpy(adap->name, "Broadcom iProc I2C adapter", sizeof(adap->name));
415 adap->algo = &bcm_iproc_algo;
416 adap->dev.parent = &pdev->dev;
417 adap->dev.of_node = pdev->dev.of_node;
418
419 ret = i2c_add_adapter(adap);
420 if (ret) {
421 dev_err(iproc_i2c->device, "failed to add adapter\n");
422 return ret;
423 }
424
425 return 0;
426}
427
428static int bcm_iproc_i2c_remove(struct platform_device *pdev)
429{
430 struct bcm_iproc_i2c_dev *iproc_i2c = platform_get_drvdata(pdev);
431
432 /* make sure there's no pending interrupt when we remove the adapter */
433 writel(0, iproc_i2c->base + IE_OFFSET);
434 readl(iproc_i2c->base + IE_OFFSET);
435 synchronize_irq(iproc_i2c->irq);
436
437 i2c_del_adapter(&iproc_i2c->adapter);
438 bcm_iproc_i2c_enable_disable(iproc_i2c, false);
439
440 return 0;
441}
442
443static const struct of_device_id bcm_iproc_i2c_of_match[] = {
444 { .compatible = "brcm,iproc-i2c" },
445 { /* sentinel */ }
446};
447MODULE_DEVICE_TABLE(of, bcm_iproc_i2c_of_match);
448
449static struct platform_driver bcm_iproc_i2c_driver = {
450 .driver = {
451 .name = "bcm-iproc-i2c",
452 .of_match_table = bcm_iproc_i2c_of_match,
453 },
454 .probe = bcm_iproc_i2c_probe,
455 .remove = bcm_iproc_i2c_remove,
456};
457module_platform_driver(bcm_iproc_i2c_driver);
458
459MODULE_AUTHOR("Ray Jui <rjui@broadcom.com>");
460MODULE_DESCRIPTION("Broadcom iProc I2C Driver");
461MODULE_LICENSE("GPL v2");
diff --git a/drivers/i2c/busses/i2c-cadence.c b/drivers/i2c/busses/i2c-cadence.c
index 626f74ecd4be..7d7a14cdadfb 100644
--- a/drivers/i2c/busses/i2c-cadence.c
+++ b/drivers/i2c/busses/i2c-cadence.c
@@ -128,6 +128,7 @@
128 * @suspended: Flag holding the device's PM status 128 * @suspended: Flag holding the device's PM status
129 * @send_count: Number of bytes still expected to send 129 * @send_count: Number of bytes still expected to send
130 * @recv_count: Number of bytes still expected to receive 130 * @recv_count: Number of bytes still expected to receive
131 * @curr_recv_count: Number of bytes to be received in current transfer
131 * @irq: IRQ number 132 * @irq: IRQ number
132 * @input_clk: Input clock to I2C controller 133 * @input_clk: Input clock to I2C controller
133 * @i2c_clk: Maximum I2C clock speed 134 * @i2c_clk: Maximum I2C clock speed
@@ -146,6 +147,7 @@ struct cdns_i2c {
146 u8 suspended; 147 u8 suspended;
147 unsigned int send_count; 148 unsigned int send_count;
148 unsigned int recv_count; 149 unsigned int recv_count;
150 unsigned int curr_recv_count;
149 int irq; 151 int irq;
150 unsigned long input_clk; 152 unsigned long input_clk;
151 unsigned int i2c_clk; 153 unsigned int i2c_clk;
@@ -182,14 +184,15 @@ static void cdns_i2c_clear_bus_hold(struct cdns_i2c *id)
182 */ 184 */
183static irqreturn_t cdns_i2c_isr(int irq, void *ptr) 185static irqreturn_t cdns_i2c_isr(int irq, void *ptr)
184{ 186{
185 unsigned int isr_status, avail_bytes; 187 unsigned int isr_status, avail_bytes, updatetx;
186 unsigned int bytes_to_recv, bytes_to_send; 188 unsigned int bytes_to_send;
187 struct cdns_i2c *id = ptr; 189 struct cdns_i2c *id = ptr;
188 /* Signal completion only after everything is updated */ 190 /* Signal completion only after everything is updated */
189 int done_flag = 0; 191 int done_flag = 0;
190 irqreturn_t status = IRQ_NONE; 192 irqreturn_t status = IRQ_NONE;
191 193
192 isr_status = cdns_i2c_readreg(CDNS_I2C_ISR_OFFSET); 194 isr_status = cdns_i2c_readreg(CDNS_I2C_ISR_OFFSET);
195 cdns_i2c_writereg(isr_status, CDNS_I2C_ISR_OFFSET);
193 196
194 /* Handling nack and arbitration lost interrupt */ 197 /* Handling nack and arbitration lost interrupt */
195 if (isr_status & (CDNS_I2C_IXR_NACK | CDNS_I2C_IXR_ARB_LOST)) { 198 if (isr_status & (CDNS_I2C_IXR_NACK | CDNS_I2C_IXR_ARB_LOST)) {
@@ -197,89 +200,112 @@ static irqreturn_t cdns_i2c_isr(int irq, void *ptr)
197 status = IRQ_HANDLED; 200 status = IRQ_HANDLED;
198 } 201 }
199 202
200 /* Handling Data interrupt */ 203 /*
201 if ((isr_status & CDNS_I2C_IXR_DATA) && 204 * Check if transfer size register needs to be updated again for a
202 (id->recv_count >= CDNS_I2C_DATA_INTR_DEPTH)) { 205 * large data receive operation.
203 /* Always read data interrupt threshold bytes */ 206 */
204 bytes_to_recv = CDNS_I2C_DATA_INTR_DEPTH; 207 updatetx = 0;
205 id->recv_count -= CDNS_I2C_DATA_INTR_DEPTH; 208 if (id->recv_count > id->curr_recv_count)
206 avail_bytes = cdns_i2c_readreg(CDNS_I2C_XFER_SIZE_OFFSET); 209 updatetx = 1;
207 210
208 /* 211 /* When receiving, handle data interrupt and completion interrupt */
209 * if the tranfer size register value is zero, then 212 if (id->p_recv_buf &&
210 * check for the remaining bytes and update the 213 ((isr_status & CDNS_I2C_IXR_COMP) ||
211 * transfer size register. 214 (isr_status & CDNS_I2C_IXR_DATA))) {
212 */ 215 /* Read data if receive data valid is set */
213 if (!avail_bytes) { 216 while (cdns_i2c_readreg(CDNS_I2C_SR_OFFSET) &
214 if (id->recv_count > CDNS_I2C_TRANSFER_SIZE) 217 CDNS_I2C_SR_RXDV) {
215 cdns_i2c_writereg(CDNS_I2C_TRANSFER_SIZE, 218 /*
216 CDNS_I2C_XFER_SIZE_OFFSET); 219 * Clear hold bit that was set for FIFO control if
217 else 220 * RX data left is less than FIFO depth, unless
218 cdns_i2c_writereg(id->recv_count, 221 * repeated start is selected.
219 CDNS_I2C_XFER_SIZE_OFFSET); 222 */
220 } 223 if ((id->recv_count < CDNS_I2C_FIFO_DEPTH) &&
224 !id->bus_hold_flag)
225 cdns_i2c_clear_bus_hold(id);
221 226
222 /* Process the data received */
223 while (bytes_to_recv--)
224 *(id->p_recv_buf)++ = 227 *(id->p_recv_buf)++ =
225 cdns_i2c_readreg(CDNS_I2C_DATA_OFFSET); 228 cdns_i2c_readreg(CDNS_I2C_DATA_OFFSET);
229 id->recv_count--;
230 id->curr_recv_count--;
226 231
227 if (!id->bus_hold_flag && 232 if (updatetx &&
228 (id->recv_count <= CDNS_I2C_FIFO_DEPTH)) 233 (id->curr_recv_count == CDNS_I2C_FIFO_DEPTH + 1))
229 cdns_i2c_clear_bus_hold(id); 234 break;
235 }
230 236
231 status = IRQ_HANDLED; 237 /*
232 } 238 * The controller sends NACK to the slave when transfer size
239 * register reaches zero without considering the HOLD bit.
240 * This workaround is implemented for large data transfers to
241 * maintain transfer size non-zero while performing a large
242 * receive operation.
243 */
244 if (updatetx &&
245 (id->curr_recv_count == CDNS_I2C_FIFO_DEPTH + 1)) {
246 /* wait while fifo is full */
247 while (cdns_i2c_readreg(CDNS_I2C_XFER_SIZE_OFFSET) !=
248 (id->curr_recv_count - CDNS_I2C_FIFO_DEPTH))
249 ;
233 250
234 /* Handling Transfer Complete interrupt */
235 if (isr_status & CDNS_I2C_IXR_COMP) {
236 if (!id->p_recv_buf) {
237 /* 251 /*
238 * If the device is sending data If there is further 252 * Check number of bytes to be received against maximum
239 * data to be sent. Calculate the available space 253 * transfer size and update register accordingly.
240 * in FIFO and fill the FIFO with that many bytes.
241 */ 254 */
242 if (id->send_count) { 255 if (((int)(id->recv_count) - CDNS_I2C_FIFO_DEPTH) >
243 avail_bytes = CDNS_I2C_FIFO_DEPTH - 256 CDNS_I2C_TRANSFER_SIZE) {
244 cdns_i2c_readreg(CDNS_I2C_XFER_SIZE_OFFSET); 257 cdns_i2c_writereg(CDNS_I2C_TRANSFER_SIZE,
245 if (id->send_count > avail_bytes) 258 CDNS_I2C_XFER_SIZE_OFFSET);
246 bytes_to_send = avail_bytes; 259 id->curr_recv_count = CDNS_I2C_TRANSFER_SIZE +
247 else 260 CDNS_I2C_FIFO_DEPTH;
248 bytes_to_send = id->send_count;
249
250 while (bytes_to_send--) {
251 cdns_i2c_writereg(
252 (*(id->p_send_buf)++),
253 CDNS_I2C_DATA_OFFSET);
254 id->send_count--;
255 }
256 } else { 261 } else {
257 /* 262 cdns_i2c_writereg(id->recv_count -
258 * Signal the completion of transaction and 263 CDNS_I2C_FIFO_DEPTH,
259 * clear the hold bus bit if there are no 264 CDNS_I2C_XFER_SIZE_OFFSET);
260 * further messages to be processed. 265 id->curr_recv_count = id->recv_count;
261 */
262 done_flag = 1;
263 } 266 }
264 if (!id->send_count && !id->bus_hold_flag) 267 }
265 cdns_i2c_clear_bus_hold(id); 268
266 } else { 269 /* Clear hold (if not repeated start) and signal completion */
270 if ((isr_status & CDNS_I2C_IXR_COMP) && !id->recv_count) {
267 if (!id->bus_hold_flag) 271 if (!id->bus_hold_flag)
268 cdns_i2c_clear_bus_hold(id); 272 cdns_i2c_clear_bus_hold(id);
273 done_flag = 1;
274 }
275
276 status = IRQ_HANDLED;
277 }
278
279 /* When sending, handle transfer complete interrupt */
280 if ((isr_status & CDNS_I2C_IXR_COMP) && !id->p_recv_buf) {
281 /*
282 * If there is more data to be sent, calculate the
283 * space available in FIFO and fill with that many bytes.
284 */
285 if (id->send_count) {
286 avail_bytes = CDNS_I2C_FIFO_DEPTH -
287 cdns_i2c_readreg(CDNS_I2C_XFER_SIZE_OFFSET);
288 if (id->send_count > avail_bytes)
289 bytes_to_send = avail_bytes;
290 else
291 bytes_to_send = id->send_count;
292
293 while (bytes_to_send--) {
294 cdns_i2c_writereg(
295 (*(id->p_send_buf)++),
296 CDNS_I2C_DATA_OFFSET);
297 id->send_count--;
298 }
299 } else {
269 /* 300 /*
270 * If the device is receiving data, then signal 301 * Signal the completion of transaction and
271 * the completion of transaction and read the data 302 * clear the hold bus bit if there are no
272 * present in the FIFO. Signal the completion of 303 * further messages to be processed.
273 * transaction.
274 */ 304 */
275 while (cdns_i2c_readreg(CDNS_I2C_SR_OFFSET) &
276 CDNS_I2C_SR_RXDV) {
277 *(id->p_recv_buf)++ =
278 cdns_i2c_readreg(CDNS_I2C_DATA_OFFSET);
279 id->recv_count--;
280 }
281 done_flag = 1; 305 done_flag = 1;
282 } 306 }
307 if (!id->send_count && !id->bus_hold_flag)
308 cdns_i2c_clear_bus_hold(id);
283 309
284 status = IRQ_HANDLED; 310 status = IRQ_HANDLED;
285 } 311 }
@@ -289,8 +315,6 @@ static irqreturn_t cdns_i2c_isr(int irq, void *ptr)
289 if (id->err_status) 315 if (id->err_status)
290 status = IRQ_HANDLED; 316 status = IRQ_HANDLED;
291 317
292 cdns_i2c_writereg(isr_status, CDNS_I2C_ISR_OFFSET);
293
294 if (done_flag) 318 if (done_flag)
295 complete(&id->xfer_done); 319 complete(&id->xfer_done);
296 320
@@ -316,6 +340,8 @@ static void cdns_i2c_mrecv(struct cdns_i2c *id)
316 if (id->p_msg->flags & I2C_M_RECV_LEN) 340 if (id->p_msg->flags & I2C_M_RECV_LEN)
317 id->recv_count = I2C_SMBUS_BLOCK_MAX + 1; 341 id->recv_count = I2C_SMBUS_BLOCK_MAX + 1;
318 342
343 id->curr_recv_count = id->recv_count;
344
319 /* 345 /*
320 * Check for the message size against FIFO depth and set the 346 * Check for the message size against FIFO depth and set the
321 * 'hold bus' bit if it is greater than FIFO depth. 347 * 'hold bus' bit if it is greater than FIFO depth.
@@ -335,11 +361,14 @@ static void cdns_i2c_mrecv(struct cdns_i2c *id)
335 * receive if it is less than transfer size and transfer size if 361 * receive if it is less than transfer size and transfer size if
336 * it is more. Enable the interrupts. 362 * it is more. Enable the interrupts.
337 */ 363 */
338 if (id->recv_count > CDNS_I2C_TRANSFER_SIZE) 364 if (id->recv_count > CDNS_I2C_TRANSFER_SIZE) {
339 cdns_i2c_writereg(CDNS_I2C_TRANSFER_SIZE, 365 cdns_i2c_writereg(CDNS_I2C_TRANSFER_SIZE,
340 CDNS_I2C_XFER_SIZE_OFFSET); 366 CDNS_I2C_XFER_SIZE_OFFSET);
341 else 367 id->curr_recv_count = CDNS_I2C_TRANSFER_SIZE;
368 } else {
342 cdns_i2c_writereg(id->recv_count, CDNS_I2C_XFER_SIZE_OFFSET); 369 cdns_i2c_writereg(id->recv_count, CDNS_I2C_XFER_SIZE_OFFSET);
370 }
371
343 /* Clear the bus hold flag if bytes to receive is less than FIFO size */ 372 /* Clear the bus hold flag if bytes to receive is less than FIFO size */
344 if (!id->bus_hold_flag && 373 if (!id->bus_hold_flag &&
345 ((id->p_msg->flags & I2C_M_RECV_LEN) != I2C_M_RECV_LEN) && 374 ((id->p_msg->flags & I2C_M_RECV_LEN) != I2C_M_RECV_LEN) &&
@@ -516,6 +545,20 @@ static int cdns_i2c_master_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs,
516 * processed with a repeated start. 545 * processed with a repeated start.
517 */ 546 */
518 if (num > 1) { 547 if (num > 1) {
548 /*
549 * This controller does not give completion interrupt after a
550 * master receive message if HOLD bit is set (repeated start),
551 * resulting in SW timeout. Hence, if a receive message is
552 * followed by any other message, an error is returned
553 * indicating that this sequence is not supported.
554 */
555 for (count = 0; count < num - 1; count++) {
556 if (msgs[count].flags & I2C_M_RD) {
557 dev_warn(adap->dev.parent,
558 "Can't do repeated start after a receive message\n");
559 return -EOPNOTSUPP;
560 }
561 }
519 id->bus_hold_flag = 1; 562 id->bus_hold_flag = 1;
520 reg = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET); 563 reg = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET);
521 reg |= CDNS_I2C_CR_HOLD; 564 reg |= CDNS_I2C_CR_HOLD;
diff --git a/drivers/i2c/busses/i2c-designware-baytrail.c b/drivers/i2c/busses/i2c-designware-baytrail.c
new file mode 100644
index 000000000000..5f1ff4cc5c34
--- /dev/null
+++ b/drivers/i2c/busses/i2c-designware-baytrail.c
@@ -0,0 +1,160 @@
1/*
2 * Intel BayTrail PMIC I2C bus semaphore implementaion
3 * Copyright (c) 2014, Intel Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 */
14#include <linux/module.h>
15#include <linux/delay.h>
16#include <linux/device.h>
17#include <linux/acpi.h>
18#include <linux/i2c.h>
19#include <linux/interrupt.h>
20#include <asm/iosf_mbi.h>
21#include "i2c-designware-core.h"
22
23#define SEMAPHORE_TIMEOUT 100
24#define PUNIT_SEMAPHORE 0x7
25
26static unsigned long acquired;
27
28static int get_sem(struct device *dev, u32 *sem)
29{
30 u32 reg_val;
31 int ret;
32
33 ret = iosf_mbi_read(BT_MBI_UNIT_PMC, BT_MBI_BUNIT_READ, PUNIT_SEMAPHORE,
34 &reg_val);
35 if (ret) {
36 dev_err(dev, "iosf failed to read punit semaphore\n");
37 return ret;
38 }
39
40 *sem = reg_val & 0x1;
41
42 return 0;
43}
44
45static void reset_semaphore(struct device *dev)
46{
47 u32 data;
48
49 if (iosf_mbi_read(BT_MBI_UNIT_PMC, BT_MBI_BUNIT_READ,
50 PUNIT_SEMAPHORE, &data)) {
51 dev_err(dev, "iosf failed to reset punit semaphore during read\n");
52 return;
53 }
54
55 data = data & 0xfffffffe;
56 if (iosf_mbi_write(BT_MBI_UNIT_PMC, BT_MBI_BUNIT_WRITE,
57 PUNIT_SEMAPHORE, data))
58 dev_err(dev, "iosf failed to reset punit semaphore during write\n");
59}
60
61int baytrail_i2c_acquire(struct dw_i2c_dev *dev)
62{
63 u32 sem = 0;
64 int ret;
65 unsigned long start, end;
66
67 if (!dev || !dev->dev)
68 return -ENODEV;
69
70 if (!dev->acquire_lock)
71 return 0;
72
73 /* host driver writes 0x2 to side band semaphore register */
74 ret = iosf_mbi_write(BT_MBI_UNIT_PMC, BT_MBI_BUNIT_WRITE,
75 PUNIT_SEMAPHORE, 0x2);
76 if (ret) {
77 dev_err(dev->dev, "iosf punit semaphore request failed\n");
78 return ret;
79 }
80
81 /* host driver waits for bit 0 to be set in semaphore register */
82 start = jiffies;
83 end = start + msecs_to_jiffies(SEMAPHORE_TIMEOUT);
84 while (!time_after(jiffies, end)) {
85 ret = get_sem(dev->dev, &sem);
86 if (!ret && sem) {
87 acquired = jiffies;
88 dev_dbg(dev->dev, "punit semaphore acquired after %ums\n",
89 jiffies_to_msecs(jiffies - start));
90 return 0;
91 }
92
93 usleep_range(1000, 2000);
94 }
95
96 dev_err(dev->dev, "punit semaphore timed out, resetting\n");
97 reset_semaphore(dev->dev);
98
99 ret = iosf_mbi_read(BT_MBI_UNIT_PMC, BT_MBI_BUNIT_READ,
100 PUNIT_SEMAPHORE, &sem);
101 if (!ret)
102 dev_err(dev->dev, "iosf failed to read punit semaphore\n");
103 else
104 dev_err(dev->dev, "PUNIT SEM: %d\n", sem);
105
106 WARN_ON(1);
107
108 return -ETIMEDOUT;
109}
110EXPORT_SYMBOL(baytrail_i2c_acquire);
111
112void baytrail_i2c_release(struct dw_i2c_dev *dev)
113{
114 if (!dev || !dev->dev)
115 return;
116
117 if (!dev->acquire_lock)
118 return;
119
120 reset_semaphore(dev->dev);
121 dev_dbg(dev->dev, "punit semaphore held for %ums\n",
122 jiffies_to_msecs(jiffies - acquired));
123}
124EXPORT_SYMBOL(baytrail_i2c_release);
125
126int i2c_dw_eval_lock_support(struct dw_i2c_dev *dev)
127{
128 acpi_status status;
129 unsigned long long shared_host = 0;
130 acpi_handle handle;
131
132 if (!dev || !dev->dev)
133 return 0;
134
135 handle = ACPI_HANDLE(dev->dev);
136 if (!handle)
137 return 0;
138
139 status = acpi_evaluate_integer(handle, "_SEM", NULL, &shared_host);
140
141 if (ACPI_FAILURE(status))
142 return 0;
143
144 if (shared_host) {
145 dev_info(dev->dev, "I2C bus managed by PUNIT\n");
146 dev->acquire_lock = baytrail_i2c_acquire;
147 dev->release_lock = baytrail_i2c_release;
148 dev->pm_runtime_disabled = true;
149 }
150
151 if (!iosf_mbi_available())
152 return -EPROBE_DEFER;
153
154 return 0;
155}
156EXPORT_SYMBOL(i2c_dw_eval_lock_support);
157
158MODULE_AUTHOR("David E. Box <david.e.box@linux.intel.com>");
159MODULE_DESCRIPTION("Baytrail I2C Semaphore driver");
160MODULE_LICENSE("GPL v2");
diff --git a/drivers/i2c/busses/i2c-designware-core.c b/drivers/i2c/busses/i2c-designware-core.c
index 23628b7bfb8d..6e25c010e690 100644
--- a/drivers/i2c/busses/i2c-designware-core.c
+++ b/drivers/i2c/busses/i2c-designware-core.c
@@ -170,10 +170,10 @@ u32 dw_readl(struct dw_i2c_dev *dev, int offset)
170 u32 value; 170 u32 value;
171 171
172 if (dev->accessor_flags & ACCESS_16BIT) 172 if (dev->accessor_flags & ACCESS_16BIT)
173 value = readw(dev->base + offset) | 173 value = readw_relaxed(dev->base + offset) |
174 (readw(dev->base + offset + 2) << 16); 174 (readw_relaxed(dev->base + offset + 2) << 16);
175 else 175 else
176 value = readl(dev->base + offset); 176 value = readl_relaxed(dev->base + offset);
177 177
178 if (dev->accessor_flags & ACCESS_SWAP) 178 if (dev->accessor_flags & ACCESS_SWAP)
179 return swab32(value); 179 return swab32(value);
@@ -187,10 +187,10 @@ void dw_writel(struct dw_i2c_dev *dev, u32 b, int offset)
187 b = swab32(b); 187 b = swab32(b);
188 188
189 if (dev->accessor_flags & ACCESS_16BIT) { 189 if (dev->accessor_flags & ACCESS_16BIT) {
190 writew((u16)b, dev->base + offset); 190 writew_relaxed((u16)b, dev->base + offset);
191 writew((u16)(b >> 16), dev->base + offset + 2); 191 writew_relaxed((u16)(b >> 16), dev->base + offset + 2);
192 } else { 192 } else {
193 writel(b, dev->base + offset); 193 writel_relaxed(b, dev->base + offset);
194 } 194 }
195} 195}
196 196
@@ -285,6 +285,15 @@ int i2c_dw_init(struct dw_i2c_dev *dev)
285 u32 hcnt, lcnt; 285 u32 hcnt, lcnt;
286 u32 reg; 286 u32 reg;
287 u32 sda_falling_time, scl_falling_time; 287 u32 sda_falling_time, scl_falling_time;
288 int ret;
289
290 if (dev->acquire_lock) {
291 ret = dev->acquire_lock(dev);
292 if (ret) {
293 dev_err(dev->dev, "couldn't acquire bus ownership\n");
294 return ret;
295 }
296 }
288 297
289 input_clock_khz = dev->get_clk_rate_khz(dev); 298 input_clock_khz = dev->get_clk_rate_khz(dev);
290 299
@@ -298,6 +307,8 @@ int i2c_dw_init(struct dw_i2c_dev *dev)
298 } else if (reg != DW_IC_COMP_TYPE_VALUE) { 307 } else if (reg != DW_IC_COMP_TYPE_VALUE) {
299 dev_err(dev->dev, "Unknown Synopsys component type: " 308 dev_err(dev->dev, "Unknown Synopsys component type: "
300 "0x%08x\n", reg); 309 "0x%08x\n", reg);
310 if (dev->release_lock)
311 dev->release_lock(dev);
301 return -ENODEV; 312 return -ENODEV;
302 } 313 }
303 314
@@ -309,40 +320,39 @@ int i2c_dw_init(struct dw_i2c_dev *dev)
309 sda_falling_time = dev->sda_falling_time ?: 300; /* ns */ 320 sda_falling_time = dev->sda_falling_time ?: 300; /* ns */
310 scl_falling_time = dev->scl_falling_time ?: 300; /* ns */ 321 scl_falling_time = dev->scl_falling_time ?: 300; /* ns */
311 322
312 /* Standard-mode */ 323 /* Set SCL timing parameters for standard-mode */
313 hcnt = i2c_dw_scl_hcnt(input_clock_khz,
314 4000, /* tHD;STA = tHIGH = 4.0 us */
315 sda_falling_time,
316 0, /* 0: DW default, 1: Ideal */
317 0); /* No offset */
318 lcnt = i2c_dw_scl_lcnt(input_clock_khz,
319 4700, /* tLOW = 4.7 us */
320 scl_falling_time,
321 0); /* No offset */
322
323 /* Allow platforms to specify the ideal HCNT and LCNT values */
324 if (dev->ss_hcnt && dev->ss_lcnt) { 324 if (dev->ss_hcnt && dev->ss_lcnt) {
325 hcnt = dev->ss_hcnt; 325 hcnt = dev->ss_hcnt;
326 lcnt = dev->ss_lcnt; 326 lcnt = dev->ss_lcnt;
327 } else {
328 hcnt = i2c_dw_scl_hcnt(input_clock_khz,
329 4000, /* tHD;STA = tHIGH = 4.0 us */
330 sda_falling_time,
331 0, /* 0: DW default, 1: Ideal */
332 0); /* No offset */
333 lcnt = i2c_dw_scl_lcnt(input_clock_khz,
334 4700, /* tLOW = 4.7 us */
335 scl_falling_time,
336 0); /* No offset */
327 } 337 }
328 dw_writel(dev, hcnt, DW_IC_SS_SCL_HCNT); 338 dw_writel(dev, hcnt, DW_IC_SS_SCL_HCNT);
329 dw_writel(dev, lcnt, DW_IC_SS_SCL_LCNT); 339 dw_writel(dev, lcnt, DW_IC_SS_SCL_LCNT);
330 dev_dbg(dev->dev, "Standard-mode HCNT:LCNT = %d:%d\n", hcnt, lcnt); 340 dev_dbg(dev->dev, "Standard-mode HCNT:LCNT = %d:%d\n", hcnt, lcnt);
331 341
332 /* Fast-mode */ 342 /* Set SCL timing parameters for fast-mode */
333 hcnt = i2c_dw_scl_hcnt(input_clock_khz,
334 600, /* tHD;STA = tHIGH = 0.6 us */
335 sda_falling_time,
336 0, /* 0: DW default, 1: Ideal */
337 0); /* No offset */
338 lcnt = i2c_dw_scl_lcnt(input_clock_khz,
339 1300, /* tLOW = 1.3 us */
340 scl_falling_time,
341 0); /* No offset */
342
343 if (dev->fs_hcnt && dev->fs_lcnt) { 343 if (dev->fs_hcnt && dev->fs_lcnt) {
344 hcnt = dev->fs_hcnt; 344 hcnt = dev->fs_hcnt;
345 lcnt = dev->fs_lcnt; 345 lcnt = dev->fs_lcnt;
346 } else {
347 hcnt = i2c_dw_scl_hcnt(input_clock_khz,
348 600, /* tHD;STA = tHIGH = 0.6 us */
349 sda_falling_time,
350 0, /* 0: DW default, 1: Ideal */
351 0); /* No offset */
352 lcnt = i2c_dw_scl_lcnt(input_clock_khz,
353 1300, /* tLOW = 1.3 us */
354 scl_falling_time,
355 0); /* No offset */
346 } 356 }
347 dw_writel(dev, hcnt, DW_IC_FS_SCL_HCNT); 357 dw_writel(dev, hcnt, DW_IC_FS_SCL_HCNT);
348 dw_writel(dev, lcnt, DW_IC_FS_SCL_LCNT); 358 dw_writel(dev, lcnt, DW_IC_FS_SCL_LCNT);
@@ -364,6 +374,9 @@ int i2c_dw_init(struct dw_i2c_dev *dev)
364 374
365 /* configure the i2c master */ 375 /* configure the i2c master */
366 dw_writel(dev, dev->master_cfg , DW_IC_CON); 376 dw_writel(dev, dev->master_cfg , DW_IC_CON);
377
378 if (dev->release_lock)
379 dev->release_lock(dev);
367 return 0; 380 return 0;
368} 381}
369EXPORT_SYMBOL_GPL(i2c_dw_init); 382EXPORT_SYMBOL_GPL(i2c_dw_init);
@@ -627,6 +640,14 @@ i2c_dw_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
627 dev->abort_source = 0; 640 dev->abort_source = 0;
628 dev->rx_outstanding = 0; 641 dev->rx_outstanding = 0;
629 642
643 if (dev->acquire_lock) {
644 ret = dev->acquire_lock(dev);
645 if (ret) {
646 dev_err(dev->dev, "couldn't acquire bus ownership\n");
647 goto done_nolock;
648 }
649 }
650
630 ret = i2c_dw_wait_bus_not_busy(dev); 651 ret = i2c_dw_wait_bus_not_busy(dev);
631 if (ret < 0) 652 if (ret < 0)
632 goto done; 653 goto done;
@@ -672,6 +693,10 @@ i2c_dw_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
672 ret = -EIO; 693 ret = -EIO;
673 694
674done: 695done:
696 if (dev->release_lock)
697 dev->release_lock(dev);
698
699done_nolock:
675 pm_runtime_mark_last_busy(dev->dev); 700 pm_runtime_mark_last_busy(dev->dev);
676 pm_runtime_put_autosuspend(dev->dev); 701 pm_runtime_put_autosuspend(dev->dev);
677 mutex_unlock(&dev->lock); 702 mutex_unlock(&dev->lock);
diff --git a/drivers/i2c/busses/i2c-designware-core.h b/drivers/i2c/busses/i2c-designware-core.h
index 5a410ef17abd..9630222abf32 100644
--- a/drivers/i2c/busses/i2c-designware-core.h
+++ b/drivers/i2c/busses/i2c-designware-core.h
@@ -61,6 +61,9 @@
61 * @ss_lcnt: standard speed LCNT value 61 * @ss_lcnt: standard speed LCNT value
62 * @fs_hcnt: fast speed HCNT value 62 * @fs_hcnt: fast speed HCNT value
63 * @fs_lcnt: fast speed LCNT value 63 * @fs_lcnt: fast speed LCNT value
64 * @acquire_lock: function to acquire a hardware lock on the bus
65 * @release_lock: function to release a hardware lock on the bus
66 * @pm_runtime_disabled: true if pm runtime is disabled
64 * 67 *
65 * HCNT and LCNT parameters can be used if the platform knows more accurate 68 * HCNT and LCNT parameters can be used if the platform knows more accurate
66 * values than the one computed based only on the input clock frequency. 69 * values than the one computed based only on the input clock frequency.
@@ -101,6 +104,9 @@ struct dw_i2c_dev {
101 u16 ss_lcnt; 104 u16 ss_lcnt;
102 u16 fs_hcnt; 105 u16 fs_hcnt;
103 u16 fs_lcnt; 106 u16 fs_lcnt;
107 int (*acquire_lock)(struct dw_i2c_dev *dev);
108 void (*release_lock)(struct dw_i2c_dev *dev);
109 bool pm_runtime_disabled;
104}; 110};
105 111
106#define ACCESS_SWAP 0x00000001 112#define ACCESS_SWAP 0x00000001
@@ -119,3 +125,9 @@ extern void i2c_dw_disable(struct dw_i2c_dev *dev);
119extern void i2c_dw_clear_int(struct dw_i2c_dev *dev); 125extern void i2c_dw_clear_int(struct dw_i2c_dev *dev);
120extern void i2c_dw_disable_int(struct dw_i2c_dev *dev); 126extern void i2c_dw_disable_int(struct dw_i2c_dev *dev);
121extern u32 i2c_dw_read_comp_param(struct dw_i2c_dev *dev); 127extern u32 i2c_dw_read_comp_param(struct dw_i2c_dev *dev);
128
129#if IS_ENABLED(CONFIG_I2C_DESIGNWARE_BAYTRAIL)
130extern int i2c_dw_eval_lock_support(struct dw_i2c_dev *dev);
131#else
132static inline int i2c_dw_eval_lock_support(struct dw_i2c_dev *dev) { return 0; }
133#endif
diff --git a/drivers/i2c/busses/i2c-designware-pcidrv.c b/drivers/i2c/busses/i2c-designware-pcidrv.c
index acb40f95db78..6643d2dc0b25 100644
--- a/drivers/i2c/busses/i2c-designware-pcidrv.c
+++ b/drivers/i2c/busses/i2c-designware-pcidrv.c
@@ -6,7 +6,7 @@
6 * Copyright (C) 2006 Texas Instruments. 6 * Copyright (C) 2006 Texas Instruments.
7 * Copyright (C) 2007 MontaVista Software Inc. 7 * Copyright (C) 2007 MontaVista Software Inc.
8 * Copyright (C) 2009 Provigent Ltd. 8 * Copyright (C) 2009 Provigent Ltd.
9 * Copyright (C) 2011 Intel corporation. 9 * Copyright (C) 2011, 2015 Intel Corporation.
10 * 10 *
11 * ---------------------------------------------------------------------------- 11 * ----------------------------------------------------------------------------
12 * 12 *
@@ -40,10 +40,6 @@
40#define DRIVER_NAME "i2c-designware-pci" 40#define DRIVER_NAME "i2c-designware-pci"
41 41
42enum dw_pci_ctl_id_t { 42enum dw_pci_ctl_id_t {
43 moorestown_0,
44 moorestown_1,
45 moorestown_2,
46
47 medfield_0, 43 medfield_0,
48 medfield_1, 44 medfield_1,
49 medfield_2, 45 medfield_2,
@@ -101,28 +97,7 @@ static struct dw_scl_sda_cfg hsw_config = {
101 .sda_hold = 0x9, 97 .sda_hold = 0x9,
102}; 98};
103 99
104static struct dw_pci_controller dw_pci_controllers[] = { 100static struct dw_pci_controller dw_pci_controllers[] = {
105 [moorestown_0] = {
106 .bus_num = 0,
107 .bus_cfg = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST,
108 .tx_fifo_depth = 32,
109 .rx_fifo_depth = 32,
110 .clk_khz = 25000,
111 },
112 [moorestown_1] = {
113 .bus_num = 1,
114 .bus_cfg = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST,
115 .tx_fifo_depth = 32,
116 .rx_fifo_depth = 32,
117 .clk_khz = 25000,
118 },
119 [moorestown_2] = {
120 .bus_num = 2,
121 .bus_cfg = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST,
122 .tx_fifo_depth = 32,
123 .rx_fifo_depth = 32,
124 .clk_khz = 25000,
125 },
126 [medfield_0] = { 101 [medfield_0] = {
127 .bus_num = 0, 102 .bus_num = 0,
128 .bus_cfg = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST, 103 .bus_cfg = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST,
@@ -170,7 +145,6 @@ static struct dw_pci_controller dw_pci_controllers[] = {
170 .bus_cfg = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST, 145 .bus_cfg = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST,
171 .tx_fifo_depth = 32, 146 .tx_fifo_depth = 32,
172 .rx_fifo_depth = 32, 147 .rx_fifo_depth = 32,
173 .clk_khz = 100000,
174 .functionality = I2C_FUNC_10BIT_ADDR, 148 .functionality = I2C_FUNC_10BIT_ADDR,
175 .scl_sda_cfg = &byt_config, 149 .scl_sda_cfg = &byt_config,
176 }, 150 },
@@ -179,7 +153,6 @@ static struct dw_pci_controller dw_pci_controllers[] = {
179 .bus_cfg = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST, 153 .bus_cfg = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST,
180 .tx_fifo_depth = 32, 154 .tx_fifo_depth = 32,
181 .rx_fifo_depth = 32, 155 .rx_fifo_depth = 32,
182 .clk_khz = 100000,
183 .functionality = I2C_FUNC_10BIT_ADDR, 156 .functionality = I2C_FUNC_10BIT_ADDR,
184 .scl_sda_cfg = &hsw_config, 157 .scl_sda_cfg = &hsw_config,
185 }, 158 },
@@ -259,7 +232,7 @@ static int i2c_dw_pci_probe(struct pci_dev *pdev,
259 dev->functionality = controller->functionality | 232 dev->functionality = controller->functionality |
260 DW_DEFAULT_FUNCTIONALITY; 233 DW_DEFAULT_FUNCTIONALITY;
261 234
262 dev->master_cfg = controller->bus_cfg; 235 dev->master_cfg = controller->bus_cfg;
263 if (controller->scl_sda_cfg) { 236 if (controller->scl_sda_cfg) {
264 cfg = controller->scl_sda_cfg; 237 cfg = controller->scl_sda_cfg;
265 dev->ss_hcnt = cfg->ss_hcnt; 238 dev->ss_hcnt = cfg->ss_hcnt;
@@ -325,12 +298,8 @@ static void i2c_dw_pci_remove(struct pci_dev *pdev)
325MODULE_ALIAS("i2c_designware-pci"); 298MODULE_ALIAS("i2c_designware-pci");
326 299
327static const struct pci_device_id i2_designware_pci_ids[] = { 300static const struct pci_device_id i2_designware_pci_ids[] = {
328 /* Moorestown */
329 { PCI_VDEVICE(INTEL, 0x0802), moorestown_0 },
330 { PCI_VDEVICE(INTEL, 0x0803), moorestown_1 },
331 { PCI_VDEVICE(INTEL, 0x0804), moorestown_2 },
332 /* Medfield */ 301 /* Medfield */
333 { PCI_VDEVICE(INTEL, 0x0817), medfield_3,}, 302 { PCI_VDEVICE(INTEL, 0x0817), medfield_3 },
334 { PCI_VDEVICE(INTEL, 0x0818), medfield_4 }, 303 { PCI_VDEVICE(INTEL, 0x0818), medfield_4 },
335 { PCI_VDEVICE(INTEL, 0x0819), medfield_5 }, 304 { PCI_VDEVICE(INTEL, 0x0819), medfield_5 },
336 { PCI_VDEVICE(INTEL, 0x082C), medfield_0 }, 305 { PCI_VDEVICE(INTEL, 0x082C), medfield_0 },
@@ -348,7 +317,7 @@ static const struct pci_device_id i2_designware_pci_ids[] = {
348 { PCI_VDEVICE(INTEL, 0x9c61), haswell }, 317 { PCI_VDEVICE(INTEL, 0x9c61), haswell },
349 { PCI_VDEVICE(INTEL, 0x9c62), haswell }, 318 { PCI_VDEVICE(INTEL, 0x9c62), haswell },
350 /* Braswell / Cherrytrail */ 319 /* Braswell / Cherrytrail */
351 { PCI_VDEVICE(INTEL, 0x22C1), baytrail,}, 320 { PCI_VDEVICE(INTEL, 0x22C1), baytrail },
352 { PCI_VDEVICE(INTEL, 0x22C2), baytrail }, 321 { PCI_VDEVICE(INTEL, 0x22C2), baytrail },
353 { PCI_VDEVICE(INTEL, 0x22C3), baytrail }, 322 { PCI_VDEVICE(INTEL, 0x22C3), baytrail },
354 { PCI_VDEVICE(INTEL, 0x22C4), baytrail }, 323 { PCI_VDEVICE(INTEL, 0x22C4), baytrail },
diff --git a/drivers/i2c/busses/i2c-designware-platdrv.c b/drivers/i2c/busses/i2c-designware-platdrv.c
index 2b463c313e4e..c270f5f9a8f9 100644
--- a/drivers/i2c/busses/i2c-designware-platdrv.c
+++ b/drivers/i2c/busses/i2c-designware-platdrv.c
@@ -195,6 +195,10 @@ static int dw_i2c_probe(struct platform_device *pdev)
195 clk_freq = pdata->i2c_scl_freq; 195 clk_freq = pdata->i2c_scl_freq;
196 } 196 }
197 197
198 r = i2c_dw_eval_lock_support(dev);
199 if (r)
200 return r;
201
198 dev->functionality = 202 dev->functionality =
199 I2C_FUNC_I2C | 203 I2C_FUNC_I2C |
200 I2C_FUNC_10BIT_ADDR | 204 I2C_FUNC_10BIT_ADDR |
@@ -257,10 +261,14 @@ static int dw_i2c_probe(struct platform_device *pdev)
257 return r; 261 return r;
258 } 262 }
259 263
260 pm_runtime_set_autosuspend_delay(&pdev->dev, 1000); 264 if (dev->pm_runtime_disabled) {
261 pm_runtime_use_autosuspend(&pdev->dev); 265 pm_runtime_forbid(&pdev->dev);
262 pm_runtime_set_active(&pdev->dev); 266 } else {
263 pm_runtime_enable(&pdev->dev); 267 pm_runtime_set_autosuspend_delay(&pdev->dev, 1000);
268 pm_runtime_use_autosuspend(&pdev->dev);
269 pm_runtime_set_active(&pdev->dev);
270 pm_runtime_enable(&pdev->dev);
271 }
264 272
265 return 0; 273 return 0;
266} 274}
@@ -310,7 +318,9 @@ static int dw_i2c_resume(struct device *dev)
310 struct dw_i2c_dev *i_dev = platform_get_drvdata(pdev); 318 struct dw_i2c_dev *i_dev = platform_get_drvdata(pdev);
311 319
312 clk_prepare_enable(i_dev->clk); 320 clk_prepare_enable(i_dev->clk);
313 i2c_dw_init(i_dev); 321
322 if (!i_dev->pm_runtime_disabled)
323 i2c_dw_init(i_dev);
314 324
315 return 0; 325 return 0;
316} 326}
diff --git a/drivers/i2c/busses/i2c-imx.c b/drivers/i2c/busses/i2c-imx.c
index 7f3a9fe9bf4e..d7b26fc6f432 100644
--- a/drivers/i2c/busses/i2c-imx.c
+++ b/drivers/i2c/busses/i2c-imx.c
@@ -201,7 +201,7 @@ struct imx_i2c_struct {
201 void __iomem *base; 201 void __iomem *base;
202 wait_queue_head_t queue; 202 wait_queue_head_t queue;
203 unsigned long i2csr; 203 unsigned long i2csr;
204 unsigned int disable_delay; 204 unsigned int disable_delay;
205 int stopped; 205 int stopped;
206 unsigned int ifdr; /* IMX_I2C_IFDR */ 206 unsigned int ifdr; /* IMX_I2C_IFDR */
207 unsigned int cur_clk; 207 unsigned int cur_clk;
@@ -295,7 +295,6 @@ static void i2c_imx_dma_request(struct imx_i2c_struct *i2c_imx,
295 dma->chan_tx = dma_request_slave_channel(dev, "tx"); 295 dma->chan_tx = dma_request_slave_channel(dev, "tx");
296 if (!dma->chan_tx) { 296 if (!dma->chan_tx) {
297 dev_dbg(dev, "can't request DMA tx channel\n"); 297 dev_dbg(dev, "can't request DMA tx channel\n");
298 ret = -ENODEV;
299 goto fail_al; 298 goto fail_al;
300 } 299 }
301 300
@@ -313,7 +312,6 @@ static void i2c_imx_dma_request(struct imx_i2c_struct *i2c_imx,
313 dma->chan_rx = dma_request_slave_channel(dev, "rx"); 312 dma->chan_rx = dma_request_slave_channel(dev, "rx");
314 if (!dma->chan_rx) { 313 if (!dma->chan_rx) {
315 dev_dbg(dev, "can't request DMA rx channel\n"); 314 dev_dbg(dev, "can't request DMA rx channel\n");
316 ret = -ENODEV;
317 goto fail_tx; 315 goto fail_tx;
318 } 316 }
319 317
@@ -481,8 +479,8 @@ static void i2c_imx_set_clk(struct imx_i2c_struct *i2c_imx)
481 i2c_clk_rate = clk_get_rate(i2c_imx->clk); 479 i2c_clk_rate = clk_get_rate(i2c_imx->clk);
482 if (i2c_imx->cur_clk == i2c_clk_rate) 480 if (i2c_imx->cur_clk == i2c_clk_rate)
483 return; 481 return;
484 else 482
485 i2c_imx->cur_clk = i2c_clk_rate; 483 i2c_imx->cur_clk = i2c_clk_rate;
486 484
487 div = (i2c_clk_rate + i2c_imx->bitrate - 1) / i2c_imx->bitrate; 485 div = (i2c_clk_rate + i2c_imx->bitrate - 1) / i2c_imx->bitrate;
488 if (div < i2c_clk_div[0].div) 486 if (div < i2c_clk_div[0].div)
@@ -490,7 +488,8 @@ static void i2c_imx_set_clk(struct imx_i2c_struct *i2c_imx)
490 else if (div > i2c_clk_div[i2c_imx->hwdata->ndivs - 1].div) 488 else if (div > i2c_clk_div[i2c_imx->hwdata->ndivs - 1].div)
491 i = i2c_imx->hwdata->ndivs - 1; 489 i = i2c_imx->hwdata->ndivs - 1;
492 else 490 else
493 for (i = 0; i2c_clk_div[i].div < div; i++); 491 for (i = 0; i2c_clk_div[i].div < div; i++)
492 ;
494 493
495 /* Store divider value */ 494 /* Store divider value */
496 i2c_imx->ifdr = i2c_clk_div[i].val; 495 i2c_imx->ifdr = i2c_clk_div[i].val;
@@ -628,9 +627,9 @@ static int i2c_imx_dma_write(struct imx_i2c_struct *i2c_imx,
628 result = wait_for_completion_timeout( 627 result = wait_for_completion_timeout(
629 &i2c_imx->dma->cmd_complete, 628 &i2c_imx->dma->cmd_complete,
630 msecs_to_jiffies(DMA_TIMEOUT)); 629 msecs_to_jiffies(DMA_TIMEOUT));
631 if (result <= 0) { 630 if (result == 0) {
632 dmaengine_terminate_all(dma->chan_using); 631 dmaengine_terminate_all(dma->chan_using);
633 return result ?: -ETIMEDOUT; 632 return -ETIMEDOUT;
634 } 633 }
635 634
636 /* Waiting for transfer complete. */ 635 /* Waiting for transfer complete. */
@@ -686,9 +685,9 @@ static int i2c_imx_dma_read(struct imx_i2c_struct *i2c_imx,
686 result = wait_for_completion_timeout( 685 result = wait_for_completion_timeout(
687 &i2c_imx->dma->cmd_complete, 686 &i2c_imx->dma->cmd_complete,
688 msecs_to_jiffies(DMA_TIMEOUT)); 687 msecs_to_jiffies(DMA_TIMEOUT));
689 if (result <= 0) { 688 if (result == 0) {
690 dmaengine_terminate_all(dma->chan_using); 689 dmaengine_terminate_all(dma->chan_using);
691 return result ?: -ETIMEDOUT; 690 return -ETIMEDOUT;
692 } 691 }
693 692
694 /* waiting for transfer complete. */ 693 /* waiting for transfer complete. */
@@ -822,6 +821,7 @@ static int i2c_imx_read(struct imx_i2c_struct *i2c_imx, struct i2c_msg *msgs, bo
822 /* read data */ 821 /* read data */
823 for (i = 0; i < msgs->len; i++) { 822 for (i = 0; i < msgs->len; i++) {
824 u8 len = 0; 823 u8 len = 0;
824
825 result = i2c_imx_trx_complete(i2c_imx); 825 result = i2c_imx_trx_complete(i2c_imx);
826 if (result) 826 if (result)
827 return result; 827 return result;
@@ -917,15 +917,16 @@ static int i2c_imx_xfer(struct i2c_adapter *adapter,
917 /* write/read data */ 917 /* write/read data */
918#ifdef CONFIG_I2C_DEBUG_BUS 918#ifdef CONFIG_I2C_DEBUG_BUS
919 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 919 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
920 dev_dbg(&i2c_imx->adapter.dev, "<%s> CONTROL: IEN=%d, IIEN=%d, " 920 dev_dbg(&i2c_imx->adapter.dev,
921 "MSTA=%d, MTX=%d, TXAK=%d, RSTA=%d\n", __func__, 921 "<%s> CONTROL: IEN=%d, IIEN=%d, MSTA=%d, MTX=%d, TXAK=%d, RSTA=%d\n",
922 __func__,
922 (temp & I2CR_IEN ? 1 : 0), (temp & I2CR_IIEN ? 1 : 0), 923 (temp & I2CR_IEN ? 1 : 0), (temp & I2CR_IIEN ? 1 : 0),
923 (temp & I2CR_MSTA ? 1 : 0), (temp & I2CR_MTX ? 1 : 0), 924 (temp & I2CR_MSTA ? 1 : 0), (temp & I2CR_MTX ? 1 : 0),
924 (temp & I2CR_TXAK ? 1 : 0), (temp & I2CR_RSTA ? 1 : 0)); 925 (temp & I2CR_TXAK ? 1 : 0), (temp & I2CR_RSTA ? 1 : 0));
925 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR); 926 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
926 dev_dbg(&i2c_imx->adapter.dev, 927 dev_dbg(&i2c_imx->adapter.dev,
927 "<%s> STATUS: ICF=%d, IAAS=%d, IBB=%d, " 928 "<%s> STATUS: ICF=%d, IAAS=%d, IBB=%d, IAL=%d, SRW=%d, IIF=%d, RXAK=%d\n",
928 "IAL=%d, SRW=%d, IIF=%d, RXAK=%d\n", __func__, 929 __func__,
929 (temp & I2SR_ICF ? 1 : 0), (temp & I2SR_IAAS ? 1 : 0), 930 (temp & I2SR_ICF ? 1 : 0), (temp & I2SR_IAAS ? 1 : 0),
930 (temp & I2SR_IBB ? 1 : 0), (temp & I2SR_IAL ? 1 : 0), 931 (temp & I2SR_IBB ? 1 : 0), (temp & I2SR_IAL ? 1 : 0),
931 (temp & I2SR_SRW ? 1 : 0), (temp & I2SR_IIF ? 1 : 0), 932 (temp & I2SR_SRW ? 1 : 0), (temp & I2SR_IIF ? 1 : 0),
@@ -1004,7 +1005,7 @@ static int i2c_imx_probe(struct platform_device *pdev)
1004 i2c_imx->adapter.owner = THIS_MODULE; 1005 i2c_imx->adapter.owner = THIS_MODULE;
1005 i2c_imx->adapter.algo = &i2c_imx_algo; 1006 i2c_imx->adapter.algo = &i2c_imx_algo;
1006 i2c_imx->adapter.dev.parent = &pdev->dev; 1007 i2c_imx->adapter.dev.parent = &pdev->dev;
1007 i2c_imx->adapter.nr = pdev->id; 1008 i2c_imx->adapter.nr = pdev->id;
1008 i2c_imx->adapter.dev.of_node = pdev->dev.of_node; 1009 i2c_imx->adapter.dev.of_node = pdev->dev.of_node;
1009 i2c_imx->base = base; 1010 i2c_imx->base = base;
1010 1011
@@ -1063,7 +1064,7 @@ static int i2c_imx_probe(struct platform_device *pdev)
1063 i2c_imx->adapter.name); 1064 i2c_imx->adapter.name);
1064 dev_info(&i2c_imx->adapter.dev, "IMX I2C adapter registered\n"); 1065 dev_info(&i2c_imx->adapter.dev, "IMX I2C adapter registered\n");
1065 1066
1066 /* Init DMA config if support*/ 1067 /* Init DMA config if supported */
1067 i2c_imx_dma_request(i2c_imx, phy_addr); 1068 i2c_imx_dma_request(i2c_imx, phy_addr);
1068 1069
1069 return 0; /* Return OK */ 1070 return 0; /* Return OK */
diff --git a/drivers/i2c/busses/i2c-ocores.c b/drivers/i2c/busses/i2c-ocores.c
index 7249b5b1e5d0..abf5db7e441e 100644
--- a/drivers/i2c/busses/i2c-ocores.c
+++ b/drivers/i2c/busses/i2c-ocores.c
@@ -12,6 +12,7 @@
12 * kind, whether express or implied. 12 * kind, whether express or implied.
13 */ 13 */
14 14
15#include <linux/clk.h>
15#include <linux/err.h> 16#include <linux/err.h>
16#include <linux/kernel.h> 17#include <linux/kernel.h>
17#include <linux/module.h> 18#include <linux/module.h>
@@ -35,7 +36,9 @@ struct ocores_i2c {
35 int pos; 36 int pos;
36 int nmsgs; 37 int nmsgs;
37 int state; /* see STATE_ */ 38 int state; /* see STATE_ */
38 int clock_khz; 39 struct clk *clk;
40 int ip_clock_khz;
41 int bus_clock_khz;
39 void (*setreg)(struct ocores_i2c *i2c, int reg, u8 value); 42 void (*setreg)(struct ocores_i2c *i2c, int reg, u8 value);
40 u8 (*getreg)(struct ocores_i2c *i2c, int reg); 43 u8 (*getreg)(struct ocores_i2c *i2c, int reg);
41}; 44};
@@ -215,21 +218,34 @@ static int ocores_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
215 return -ETIMEDOUT; 218 return -ETIMEDOUT;
216} 219}
217 220
218static void ocores_init(struct ocores_i2c *i2c) 221static int ocores_init(struct device *dev, struct ocores_i2c *i2c)
219{ 222{
220 int prescale; 223 int prescale;
224 int diff;
221 u8 ctrl = oc_getreg(i2c, OCI2C_CONTROL); 225 u8 ctrl = oc_getreg(i2c, OCI2C_CONTROL);
222 226
223 /* make sure the device is disabled */ 227 /* make sure the device is disabled */
224 oc_setreg(i2c, OCI2C_CONTROL, ctrl & ~(OCI2C_CTRL_EN|OCI2C_CTRL_IEN)); 228 oc_setreg(i2c, OCI2C_CONTROL, ctrl & ~(OCI2C_CTRL_EN|OCI2C_CTRL_IEN));
225 229
226 prescale = (i2c->clock_khz / (5*100)) - 1; 230 prescale = (i2c->ip_clock_khz / (5 * i2c->bus_clock_khz)) - 1;
231 prescale = clamp(prescale, 0, 0xffff);
232
233 diff = i2c->ip_clock_khz / (5 * (prescale + 1)) - i2c->bus_clock_khz;
234 if (abs(diff) > i2c->bus_clock_khz / 10) {
235 dev_err(dev,
236 "Unsupported clock settings: core: %d KHz, bus: %d KHz\n",
237 i2c->ip_clock_khz, i2c->bus_clock_khz);
238 return -EINVAL;
239 }
240
227 oc_setreg(i2c, OCI2C_PRELOW, prescale & 0xff); 241 oc_setreg(i2c, OCI2C_PRELOW, prescale & 0xff);
228 oc_setreg(i2c, OCI2C_PREHIGH, prescale >> 8); 242 oc_setreg(i2c, OCI2C_PREHIGH, prescale >> 8);
229 243
230 /* Init the device */ 244 /* Init the device */
231 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_IACK); 245 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_IACK);
232 oc_setreg(i2c, OCI2C_CONTROL, ctrl | OCI2C_CTRL_IEN | OCI2C_CTRL_EN); 246 oc_setreg(i2c, OCI2C_CONTROL, ctrl | OCI2C_CTRL_IEN | OCI2C_CTRL_EN);
247
248 return 0;
233} 249}
234 250
235 251
@@ -304,6 +320,8 @@ static int ocores_i2c_of_probe(struct platform_device *pdev,
304 struct device_node *np = pdev->dev.of_node; 320 struct device_node *np = pdev->dev.of_node;
305 const struct of_device_id *match; 321 const struct of_device_id *match;
306 u32 val; 322 u32 val;
323 u32 clock_frequency;
324 bool clock_frequency_present;
307 325
308 if (of_property_read_u32(np, "reg-shift", &i2c->reg_shift)) { 326 if (of_property_read_u32(np, "reg-shift", &i2c->reg_shift)) {
309 /* no 'reg-shift', check for deprecated 'regstep' */ 327 /* no 'reg-shift', check for deprecated 'regstep' */
@@ -319,12 +337,42 @@ static int ocores_i2c_of_probe(struct platform_device *pdev,
319 } 337 }
320 } 338 }
321 339
322 if (of_property_read_u32(np, "clock-frequency", &val)) { 340 clock_frequency_present = !of_property_read_u32(np, "clock-frequency",
323 dev_err(&pdev->dev, 341 &clock_frequency);
324 "Missing required parameter 'clock-frequency'\n"); 342 i2c->bus_clock_khz = 100;
325 return -ENODEV; 343
344 i2c->clk = devm_clk_get(&pdev->dev, NULL);
345
346 if (!IS_ERR(i2c->clk)) {
347 int ret = clk_prepare_enable(i2c->clk);
348
349 if (ret) {
350 dev_err(&pdev->dev,
351 "clk_prepare_enable failed: %d\n", ret);
352 return ret;
353 }
354 i2c->ip_clock_khz = clk_get_rate(i2c->clk) / 1000;
355 if (clock_frequency_present)
356 i2c->bus_clock_khz = clock_frequency / 1000;
357 }
358
359 if (i2c->ip_clock_khz == 0) {
360 if (of_property_read_u32(np, "opencores,ip-clock-frequency",
361 &val)) {
362 if (!clock_frequency_present) {
363 dev_err(&pdev->dev,
364 "Missing required parameter 'opencores,ip-clock-frequency'\n");
365 return -ENODEV;
366 }
367 i2c->ip_clock_khz = clock_frequency / 1000;
368 dev_warn(&pdev->dev,
369 "Deprecated usage of the 'clock-frequency' property, please update to 'opencores,ip-clock-frequency'\n");
370 } else {
371 i2c->ip_clock_khz = val / 1000;
372 if (clock_frequency_present)
373 i2c->bus_clock_khz = clock_frequency / 1000;
374 }
326 } 375 }
327 i2c->clock_khz = val / 1000;
328 376
329 of_property_read_u32(pdev->dev.of_node, "reg-io-width", 377 of_property_read_u32(pdev->dev.of_node, "reg-io-width",
330 &i2c->reg_io_width); 378 &i2c->reg_io_width);
@@ -368,7 +416,8 @@ static int ocores_i2c_probe(struct platform_device *pdev)
368 if (pdata) { 416 if (pdata) {
369 i2c->reg_shift = pdata->reg_shift; 417 i2c->reg_shift = pdata->reg_shift;
370 i2c->reg_io_width = pdata->reg_io_width; 418 i2c->reg_io_width = pdata->reg_io_width;
371 i2c->clock_khz = pdata->clock_khz; 419 i2c->ip_clock_khz = pdata->clock_khz;
420 i2c->bus_clock_khz = 100;
372 } else { 421 } else {
373 ret = ocores_i2c_of_probe(pdev, i2c); 422 ret = ocores_i2c_of_probe(pdev, i2c);
374 if (ret) 423 if (ret)
@@ -402,7 +451,9 @@ static int ocores_i2c_probe(struct platform_device *pdev)
402 } 451 }
403 } 452 }
404 453
405 ocores_init(i2c); 454 ret = ocores_init(&pdev->dev, i2c);
455 if (ret)
456 return ret;
406 457
407 init_waitqueue_head(&i2c->wait); 458 init_waitqueue_head(&i2c->wait);
408 ret = devm_request_irq(&pdev->dev, irq, ocores_isr, 0, 459 ret = devm_request_irq(&pdev->dev, irq, ocores_isr, 0,
@@ -446,6 +497,9 @@ static int ocores_i2c_remove(struct platform_device *pdev)
446 /* remove adapter & data */ 497 /* remove adapter & data */
447 i2c_del_adapter(&i2c->adap); 498 i2c_del_adapter(&i2c->adap);
448 499
500 if (!IS_ERR(i2c->clk))
501 clk_disable_unprepare(i2c->clk);
502
449 return 0; 503 return 0;
450} 504}
451 505
@@ -458,6 +512,8 @@ static int ocores_i2c_suspend(struct device *dev)
458 /* make sure the device is disabled */ 512 /* make sure the device is disabled */
459 oc_setreg(i2c, OCI2C_CONTROL, ctrl & ~(OCI2C_CTRL_EN|OCI2C_CTRL_IEN)); 513 oc_setreg(i2c, OCI2C_CONTROL, ctrl & ~(OCI2C_CTRL_EN|OCI2C_CTRL_IEN));
460 514
515 if (!IS_ERR(i2c->clk))
516 clk_disable_unprepare(i2c->clk);
461 return 0; 517 return 0;
462} 518}
463 519
@@ -465,9 +521,20 @@ static int ocores_i2c_resume(struct device *dev)
465{ 521{
466 struct ocores_i2c *i2c = dev_get_drvdata(dev); 522 struct ocores_i2c *i2c = dev_get_drvdata(dev);
467 523
468 ocores_init(i2c); 524 if (!IS_ERR(i2c->clk)) {
525 unsigned long rate;
526 int ret = clk_prepare_enable(i2c->clk);
469 527
470 return 0; 528 if (ret) {
529 dev_err(dev,
530 "clk_prepare_enable failed: %d\n", ret);
531 return ret;
532 }
533 rate = clk_get_rate(i2c->clk) / 1000;
534 if (rate)
535 i2c->ip_clock_khz = rate;
536 }
537 return ocores_init(dev, i2c);
471} 538}
472 539
473static SIMPLE_DEV_PM_OPS(ocores_i2c_pm, ocores_i2c_suspend, ocores_i2c_resume); 540static SIMPLE_DEV_PM_OPS(ocores_i2c_pm, ocores_i2c_suspend, ocores_i2c_resume);
diff --git a/drivers/i2c/busses/i2c-pmcmsp.c b/drivers/i2c/busses/i2c-pmcmsp.c
index 44f03eed00dd..d37d9db6681e 100644
--- a/drivers/i2c/busses/i2c-pmcmsp.c
+++ b/drivers/i2c/busses/i2c-pmcmsp.c
@@ -148,13 +148,6 @@ static inline u32 pmcmsptwi_clock_to_reg(
148 return ((clock->filter & 0xf) << 12) | (clock->clock & 0x03ff); 148 return ((clock->filter & 0xf) << 12) | (clock->clock & 0x03ff);
149} 149}
150 150
151static inline void pmcmsptwi_reg_to_clock(
152 u32 reg, struct pmcmsptwi_clock *clock)
153{
154 clock->filter = (reg >> 12) & 0xf;
155 clock->clock = reg & 0x03ff;
156}
157
158static inline u32 pmcmsptwi_cfg_to_reg(const struct pmcmsptwi_cfg *cfg) 151static inline u32 pmcmsptwi_cfg_to_reg(const struct pmcmsptwi_cfg *cfg)
159{ 152{
160 return ((cfg->arbf & 0xf) << 12) | 153 return ((cfg->arbf & 0xf) << 12) |
diff --git a/drivers/i2c/busses/i2c-rk3x.c b/drivers/i2c/busses/i2c-rk3x.c
index 92462843db66..5f96b1b3e3a5 100644
--- a/drivers/i2c/busses/i2c-rk3x.c
+++ b/drivers/i2c/busses/i2c-rk3x.c
@@ -102,6 +102,9 @@ struct rk3x_i2c {
102 102
103 /* Settings */ 103 /* Settings */
104 unsigned int scl_frequency; 104 unsigned int scl_frequency;
105 unsigned int scl_rise_ns;
106 unsigned int scl_fall_ns;
107 unsigned int sda_fall_ns;
105 108
106 /* Synchronization & notification */ 109 /* Synchronization & notification */
107 spinlock_t lock; 110 spinlock_t lock;
@@ -435,6 +438,9 @@ out:
435 * 438 *
436 * @clk_rate: I2C input clock rate 439 * @clk_rate: I2C input clock rate
437 * @scl_rate: Desired SCL rate 440 * @scl_rate: Desired SCL rate
441 * @scl_rise_ns: How many ns it takes for SCL to rise.
442 * @scl_fall_ns: How many ns it takes for SCL to fall.
443 * @sda_fall_ns: How many ns it takes for SDA to fall.
438 * @div_low: Divider output for low 444 * @div_low: Divider output for low
439 * @div_high: Divider output for high 445 * @div_high: Divider output for high
440 * 446 *
@@ -443,11 +449,16 @@ out:
443 * too high, we silently use the highest possible rate. 449 * too high, we silently use the highest possible rate.
444 */ 450 */
445static int rk3x_i2c_calc_divs(unsigned long clk_rate, unsigned long scl_rate, 451static int rk3x_i2c_calc_divs(unsigned long clk_rate, unsigned long scl_rate,
452 unsigned long scl_rise_ns,
453 unsigned long scl_fall_ns,
454 unsigned long sda_fall_ns,
446 unsigned long *div_low, unsigned long *div_high) 455 unsigned long *div_low, unsigned long *div_high)
447{ 456{
448 unsigned long min_low_ns, min_high_ns; 457 unsigned long spec_min_low_ns, spec_min_high_ns;
449 unsigned long max_data_hold_ns; 458 unsigned long spec_setup_start, spec_max_data_hold_ns;
450 unsigned long data_hold_buffer_ns; 459 unsigned long data_hold_buffer_ns;
460
461 unsigned long min_low_ns, min_high_ns;
451 unsigned long max_low_ns, min_total_ns; 462 unsigned long max_low_ns, min_total_ns;
452 463
453 unsigned long clk_rate_khz, scl_rate_khz; 464 unsigned long clk_rate_khz, scl_rate_khz;
@@ -469,29 +480,50 @@ static int rk3x_i2c_calc_divs(unsigned long clk_rate, unsigned long scl_rate,
469 scl_rate = 1000; 480 scl_rate = 1000;
470 481
471 /* 482 /*
472 * min_low_ns: The minimum number of ns we need to hold low 483 * min_low_ns: The minimum number of ns we need to hold low to
473 * to meet i2c spec 484 * meet I2C specification, should include fall time.
474 * min_high_ns: The minimum number of ns we need to hold high 485 * min_high_ns: The minimum number of ns we need to hold high to
475 * to meet i2c spec 486 * meet I2C specification, should include rise time.
476 * max_low_ns: The maximum number of ns we can hold low 487 * max_low_ns: The maximum number of ns we can hold low to meet
477 * to meet i2c spec 488 * I2C specification.
478 * 489 *
479 * Note: max_low_ns should be (max data hold time * 2 - buffer) 490 * Note: max_low_ns should be (maximum data hold time * 2 - buffer)
480 * This is because the i2c host on Rockchip holds the data line 491 * This is because the i2c host on Rockchip holds the data line
481 * for half the low time. 492 * for half the low time.
482 */ 493 */
483 if (scl_rate <= 100000) { 494 if (scl_rate <= 100000) {
484 min_low_ns = 4700; 495 /* Standard-mode */
485 min_high_ns = 4000; 496 spec_min_low_ns = 4700;
486 max_data_hold_ns = 3450; 497 spec_setup_start = 4700;
498 spec_min_high_ns = 4000;
499 spec_max_data_hold_ns = 3450;
487 data_hold_buffer_ns = 50; 500 data_hold_buffer_ns = 50;
488 } else { 501 } else {
489 min_low_ns = 1300; 502 /* Fast-mode */
490 min_high_ns = 600; 503 spec_min_low_ns = 1300;
491 max_data_hold_ns = 900; 504 spec_setup_start = 600;
505 spec_min_high_ns = 600;
506 spec_max_data_hold_ns = 900;
492 data_hold_buffer_ns = 50; 507 data_hold_buffer_ns = 50;
493 } 508 }
494 max_low_ns = max_data_hold_ns * 2 - data_hold_buffer_ns; 509 min_high_ns = scl_rise_ns + spec_min_high_ns;
510
511 /*
512 * Timings for repeated start:
513 * - controller appears to drop SDA at .875x (7/8) programmed clk high.
514 * - controller appears to keep SCL high for 2x programmed clk high.
515 *
516 * We need to account for those rules in picking our "high" time so
517 * we meet tSU;STA and tHD;STA times.
518 */
519 min_high_ns = max(min_high_ns,
520 DIV_ROUND_UP((scl_rise_ns + spec_setup_start) * 1000, 875));
521 min_high_ns = max(min_high_ns,
522 DIV_ROUND_UP((scl_rise_ns + spec_setup_start +
523 sda_fall_ns + spec_min_high_ns), 2));
524
525 min_low_ns = scl_fall_ns + spec_min_low_ns;
526 max_low_ns = spec_max_data_hold_ns * 2 - data_hold_buffer_ns;
495 min_total_ns = min_low_ns + min_high_ns; 527 min_total_ns = min_low_ns + min_high_ns;
496 528
497 /* Adjust to avoid overflow */ 529 /* Adjust to avoid overflow */
@@ -510,8 +542,8 @@ static int rk3x_i2c_calc_divs(unsigned long clk_rate, unsigned long scl_rate,
510 min_div_for_hold = (min_low_div + min_high_div); 542 min_div_for_hold = (min_low_div + min_high_div);
511 543
512 /* 544 /*
513 * This is the maximum divider so we don't go over the max. 545 * This is the maximum divider so we don't go over the maximum.
514 * We don't round up here (we round down) since this is a max. 546 * We don't round up here (we round down) since this is a maximum.
515 */ 547 */
516 max_low_div = clk_rate_khz * max_low_ns / (8 * 1000000); 548 max_low_div = clk_rate_khz * max_low_ns / (8 * 1000000);
517 549
@@ -544,7 +576,7 @@ static int rk3x_i2c_calc_divs(unsigned long clk_rate, unsigned long scl_rate,
544 ideal_low_div = DIV_ROUND_UP(clk_rate_khz * min_low_ns, 576 ideal_low_div = DIV_ROUND_UP(clk_rate_khz * min_low_ns,
545 scl_rate_khz * 8 * min_total_ns); 577 scl_rate_khz * 8 * min_total_ns);
546 578
547 /* Don't allow it to go over the max */ 579 /* Don't allow it to go over the maximum */
548 if (ideal_low_div > max_low_div) 580 if (ideal_low_div > max_low_div)
549 ideal_low_div = max_low_div; 581 ideal_low_div = max_low_div;
550 582
@@ -588,9 +620,9 @@ static void rk3x_i2c_adapt_div(struct rk3x_i2c *i2c, unsigned long clk_rate)
588 u64 t_low_ns, t_high_ns; 620 u64 t_low_ns, t_high_ns;
589 int ret; 621 int ret;
590 622
591 ret = rk3x_i2c_calc_divs(clk_rate, i2c->scl_frequency, &div_low, 623 ret = rk3x_i2c_calc_divs(clk_rate, i2c->scl_frequency, i2c->scl_rise_ns,
592 &div_high); 624 i2c->scl_fall_ns, i2c->sda_fall_ns,
593 625 &div_low, &div_high);
594 WARN_ONCE(ret != 0, "Could not reach SCL freq %u", i2c->scl_frequency); 626 WARN_ONCE(ret != 0, "Could not reach SCL freq %u", i2c->scl_frequency);
595 627
596 clk_enable(i2c->clk); 628 clk_enable(i2c->clk);
@@ -633,9 +665,10 @@ static int rk3x_i2c_clk_notifier_cb(struct notifier_block *nb, unsigned long
633 switch (event) { 665 switch (event) {
634 case PRE_RATE_CHANGE: 666 case PRE_RATE_CHANGE:
635 if (rk3x_i2c_calc_divs(ndata->new_rate, i2c->scl_frequency, 667 if (rk3x_i2c_calc_divs(ndata->new_rate, i2c->scl_frequency,
636 &div_low, &div_high) != 0) { 668 i2c->scl_rise_ns, i2c->scl_fall_ns,
669 i2c->sda_fall_ns,
670 &div_low, &div_high) != 0)
637 return NOTIFY_STOP; 671 return NOTIFY_STOP;
638 }
639 672
640 /* scale up */ 673 /* scale up */
641 if (ndata->new_rate > ndata->old_rate) 674 if (ndata->new_rate > ndata->old_rate)
@@ -859,6 +892,24 @@ static int rk3x_i2c_probe(struct platform_device *pdev)
859 i2c->scl_frequency = DEFAULT_SCL_RATE; 892 i2c->scl_frequency = DEFAULT_SCL_RATE;
860 } 893 }
861 894
895 /*
896 * Read rise and fall time from device tree. If not available use
897 * the default maximum timing from the specification.
898 */
899 if (of_property_read_u32(pdev->dev.of_node, "i2c-scl-rising-time-ns",
900 &i2c->scl_rise_ns)) {
901 if (i2c->scl_frequency <= 100000)
902 i2c->scl_rise_ns = 1000;
903 else
904 i2c->scl_rise_ns = 300;
905 }
906 if (of_property_read_u32(pdev->dev.of_node, "i2c-scl-falling-time-ns",
907 &i2c->scl_fall_ns))
908 i2c->scl_fall_ns = 300;
909 if (of_property_read_u32(pdev->dev.of_node, "i2c-sda-falling-time-ns",
910 &i2c->scl_fall_ns))
911 i2c->sda_fall_ns = i2c->scl_fall_ns;
912
862 strlcpy(i2c->adap.name, "rk3x-i2c", sizeof(i2c->adap.name)); 913 strlcpy(i2c->adap.name, "rk3x-i2c", sizeof(i2c->adap.name));
863 i2c->adap.owner = THIS_MODULE; 914 i2c->adap.owner = THIS_MODULE;
864 i2c->adap.algo = &rk3x_i2c_algorithm; 915 i2c->adap.algo = &rk3x_i2c_algorithm;
diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/i2c-tegra.c
index 28b87e683503..29f14331dd9d 100644
--- a/drivers/i2c/busses/i2c-tegra.c
+++ b/drivers/i2c/busses/i2c-tegra.c
@@ -286,6 +286,7 @@ static int tegra_i2c_empty_rx_fifo(struct tegra_i2c_dev *i2c_dev)
286 if (rx_fifo_avail > 0 && buf_remaining > 0) { 286 if (rx_fifo_avail > 0 && buf_remaining > 0) {
287 BUG_ON(buf_remaining > 3); 287 BUG_ON(buf_remaining > 3);
288 val = i2c_readl(i2c_dev, I2C_RX_FIFO); 288 val = i2c_readl(i2c_dev, I2C_RX_FIFO);
289 val = cpu_to_le32(val);
289 memcpy(buf, &val, buf_remaining); 290 memcpy(buf, &val, buf_remaining);
290 buf_remaining = 0; 291 buf_remaining = 0;
291 rx_fifo_avail--; 292 rx_fifo_avail--;
@@ -344,6 +345,7 @@ static int tegra_i2c_fill_tx_fifo(struct tegra_i2c_dev *i2c_dev)
344 if (tx_fifo_avail > 0 && buf_remaining > 0) { 345 if (tx_fifo_avail > 0 && buf_remaining > 0) {
345 BUG_ON(buf_remaining > 3); 346 BUG_ON(buf_remaining > 3);
346 memcpy(&val, buf, buf_remaining); 347 memcpy(&val, buf, buf_remaining);
348 val = le32_to_cpu(val);
347 349
348 /* Again update before writing to FIFO to make sure isr sees. */ 350 /* Again update before writing to FIFO to make sure isr sees. */
349 i2c_dev->msg_buf_remaining = 0; 351 i2c_dev->msg_buf_remaining = 0;
diff --git a/drivers/i2c/i2c-core.c b/drivers/i2c/i2c-core.c
index e9eae57a2b50..210cf4874cb7 100644
--- a/drivers/i2c/i2c-core.c
+++ b/drivers/i2c/i2c-core.c
@@ -102,7 +102,7 @@ static int acpi_i2c_add_resource(struct acpi_resource *ares, void *data)
102 struct acpi_resource_i2c_serialbus *sb; 102 struct acpi_resource_i2c_serialbus *sb;
103 103
104 sb = &ares->data.i2c_serial_bus; 104 sb = &ares->data.i2c_serial_bus;
105 if (sb->type == ACPI_RESOURCE_SERIAL_TYPE_I2C) { 105 if (!info->addr && sb->type == ACPI_RESOURCE_SERIAL_TYPE_I2C) {
106 info->addr = sb->slave_address; 106 info->addr = sb->slave_address;
107 if (sb->access_mode == ACPI_I2C_10BIT_MODE) 107 if (sb->access_mode == ACPI_I2C_10BIT_MODE)
108 info->flags |= I2C_CLIENT_TEN; 108 info->flags |= I2C_CLIENT_TEN;
@@ -698,101 +698,6 @@ static void i2c_device_shutdown(struct device *dev)
698 driver->shutdown(client); 698 driver->shutdown(client);
699} 699}
700 700
701#ifdef CONFIG_PM_SLEEP
702static int i2c_legacy_suspend(struct device *dev, pm_message_t mesg)
703{
704 struct i2c_client *client = i2c_verify_client(dev);
705 struct i2c_driver *driver;
706
707 if (!client || !dev->driver)
708 return 0;
709 driver = to_i2c_driver(dev->driver);
710 if (!driver->suspend)
711 return 0;
712 return driver->suspend(client, mesg);
713}
714
715static int i2c_legacy_resume(struct device *dev)
716{
717 struct i2c_client *client = i2c_verify_client(dev);
718 struct i2c_driver *driver;
719
720 if (!client || !dev->driver)
721 return 0;
722 driver = to_i2c_driver(dev->driver);
723 if (!driver->resume)
724 return 0;
725 return driver->resume(client);
726}
727
728static int i2c_device_pm_suspend(struct device *dev)
729{
730 const struct dev_pm_ops *pm = dev->driver ? dev->driver->pm : NULL;
731
732 if (pm)
733 return pm_generic_suspend(dev);
734 else
735 return i2c_legacy_suspend(dev, PMSG_SUSPEND);
736}
737
738static int i2c_device_pm_resume(struct device *dev)
739{
740 const struct dev_pm_ops *pm = dev->driver ? dev->driver->pm : NULL;
741
742 if (pm)
743 return pm_generic_resume(dev);
744 else
745 return i2c_legacy_resume(dev);
746}
747
748static int i2c_device_pm_freeze(struct device *dev)
749{
750 const struct dev_pm_ops *pm = dev->driver ? dev->driver->pm : NULL;
751
752 if (pm)
753 return pm_generic_freeze(dev);
754 else
755 return i2c_legacy_suspend(dev, PMSG_FREEZE);
756}
757
758static int i2c_device_pm_thaw(struct device *dev)
759{
760 const struct dev_pm_ops *pm = dev->driver ? dev->driver->pm : NULL;
761
762 if (pm)
763 return pm_generic_thaw(dev);
764 else
765 return i2c_legacy_resume(dev);
766}
767
768static int i2c_device_pm_poweroff(struct device *dev)
769{
770 const struct dev_pm_ops *pm = dev->driver ? dev->driver->pm : NULL;
771
772 if (pm)
773 return pm_generic_poweroff(dev);
774 else
775 return i2c_legacy_suspend(dev, PMSG_HIBERNATE);
776}
777
778static int i2c_device_pm_restore(struct device *dev)
779{
780 const struct dev_pm_ops *pm = dev->driver ? dev->driver->pm : NULL;
781
782 if (pm)
783 return pm_generic_restore(dev);
784 else
785 return i2c_legacy_resume(dev);
786}
787#else /* !CONFIG_PM_SLEEP */
788#define i2c_device_pm_suspend NULL
789#define i2c_device_pm_resume NULL
790#define i2c_device_pm_freeze NULL
791#define i2c_device_pm_thaw NULL
792#define i2c_device_pm_poweroff NULL
793#define i2c_device_pm_restore NULL
794#endif /* !CONFIG_PM_SLEEP */
795
796static void i2c_client_dev_release(struct device *dev) 701static void i2c_client_dev_release(struct device *dev)
797{ 702{
798 kfree(to_i2c_client(dev)); 703 kfree(to_i2c_client(dev));
@@ -804,6 +709,7 @@ show_name(struct device *dev, struct device_attribute *attr, char *buf)
804 return sprintf(buf, "%s\n", dev->type == &i2c_client_type ? 709 return sprintf(buf, "%s\n", dev->type == &i2c_client_type ?
805 to_i2c_client(dev)->name : to_i2c_adapter(dev)->name); 710 to_i2c_client(dev)->name : to_i2c_adapter(dev)->name);
806} 711}
712static DEVICE_ATTR(name, S_IRUGO, show_name, NULL);
807 713
808static ssize_t 714static ssize_t
809show_modalias(struct device *dev, struct device_attribute *attr, char *buf) 715show_modalias(struct device *dev, struct device_attribute *attr, char *buf)
@@ -817,8 +723,6 @@ show_modalias(struct device *dev, struct device_attribute *attr, char *buf)
817 723
818 return sprintf(buf, "%s%s\n", I2C_MODULE_PREFIX, client->name); 724 return sprintf(buf, "%s%s\n", I2C_MODULE_PREFIX, client->name);
819} 725}
820
821static DEVICE_ATTR(name, S_IRUGO, show_name, NULL);
822static DEVICE_ATTR(modalias, S_IRUGO, show_modalias, NULL); 726static DEVICE_ATTR(modalias, S_IRUGO, show_modalias, NULL);
823 727
824static struct attribute *i2c_dev_attrs[] = { 728static struct attribute *i2c_dev_attrs[] = {
@@ -827,29 +731,7 @@ static struct attribute *i2c_dev_attrs[] = {
827 &dev_attr_modalias.attr, 731 &dev_attr_modalias.attr,
828 NULL 732 NULL
829}; 733};
830 734ATTRIBUTE_GROUPS(i2c_dev);
831static struct attribute_group i2c_dev_attr_group = {
832 .attrs = i2c_dev_attrs,
833};
834
835static const struct attribute_group *i2c_dev_attr_groups[] = {
836 &i2c_dev_attr_group,
837 NULL
838};
839
840static const struct dev_pm_ops i2c_device_pm_ops = {
841 .suspend = i2c_device_pm_suspend,
842 .resume = i2c_device_pm_resume,
843 .freeze = i2c_device_pm_freeze,
844 .thaw = i2c_device_pm_thaw,
845 .poweroff = i2c_device_pm_poweroff,
846 .restore = i2c_device_pm_restore,
847 SET_RUNTIME_PM_OPS(
848 pm_generic_runtime_suspend,
849 pm_generic_runtime_resume,
850 NULL
851 )
852};
853 735
854struct bus_type i2c_bus_type = { 736struct bus_type i2c_bus_type = {
855 .name = "i2c", 737 .name = "i2c",
@@ -857,12 +739,11 @@ struct bus_type i2c_bus_type = {
857 .probe = i2c_device_probe, 739 .probe = i2c_device_probe,
858 .remove = i2c_device_remove, 740 .remove = i2c_device_remove,
859 .shutdown = i2c_device_shutdown, 741 .shutdown = i2c_device_shutdown,
860 .pm = &i2c_device_pm_ops,
861}; 742};
862EXPORT_SYMBOL_GPL(i2c_bus_type); 743EXPORT_SYMBOL_GPL(i2c_bus_type);
863 744
864static struct device_type i2c_client_type = { 745static struct device_type i2c_client_type = {
865 .groups = i2c_dev_attr_groups, 746 .groups = i2c_dev_groups,
866 .uevent = i2c_device_uevent, 747 .uevent = i2c_device_uevent,
867 .release = i2c_client_dev_release, 748 .release = i2c_client_dev_release,
868}; 749};
@@ -1261,6 +1142,7 @@ i2c_sysfs_new_device(struct device *dev, struct device_attribute *attr,
1261 1142
1262 return count; 1143 return count;
1263} 1144}
1145static DEVICE_ATTR(new_device, S_IWUSR, NULL, i2c_sysfs_new_device);
1264 1146
1265/* 1147/*
1266 * And of course let the users delete the devices they instantiated, if 1148 * And of course let the users delete the devices they instantiated, if
@@ -1315,8 +1197,6 @@ i2c_sysfs_delete_device(struct device *dev, struct device_attribute *attr,
1315 "delete_device"); 1197 "delete_device");
1316 return res; 1198 return res;
1317} 1199}
1318
1319static DEVICE_ATTR(new_device, S_IWUSR, NULL, i2c_sysfs_new_device);
1320static DEVICE_ATTR_IGNORE_LOCKDEP(delete_device, S_IWUSR, NULL, 1200static DEVICE_ATTR_IGNORE_LOCKDEP(delete_device, S_IWUSR, NULL,
1321 i2c_sysfs_delete_device); 1201 i2c_sysfs_delete_device);
1322 1202
@@ -1326,18 +1206,10 @@ static struct attribute *i2c_adapter_attrs[] = {
1326 &dev_attr_delete_device.attr, 1206 &dev_attr_delete_device.attr,
1327 NULL 1207 NULL
1328}; 1208};
1329 1209ATTRIBUTE_GROUPS(i2c_adapter);
1330static struct attribute_group i2c_adapter_attr_group = {
1331 .attrs = i2c_adapter_attrs,
1332};
1333
1334static const struct attribute_group *i2c_adapter_attr_groups[] = {
1335 &i2c_adapter_attr_group,
1336 NULL
1337};
1338 1210
1339struct device_type i2c_adapter_type = { 1211struct device_type i2c_adapter_type = {
1340 .groups = i2c_adapter_attr_groups, 1212 .groups = i2c_adapter_groups,
1341 .release = i2c_adapter_dev_release, 1213 .release = i2c_adapter_dev_release,
1342}; 1214};
1343EXPORT_SYMBOL_GPL(i2c_adapter_type); 1215EXPORT_SYMBOL_GPL(i2c_adapter_type);
@@ -1419,8 +1291,6 @@ static struct i2c_client *of_i2c_register_device(struct i2c_adapter *adap,
1419 if (of_get_property(node, "wakeup-source", NULL)) 1291 if (of_get_property(node, "wakeup-source", NULL))
1420 info.flags |= I2C_CLIENT_WAKE; 1292 info.flags |= I2C_CLIENT_WAKE;
1421 1293
1422 request_module("%s%s", I2C_MODULE_PREFIX, info.type);
1423
1424 result = i2c_new_device(adap, &info); 1294 result = i2c_new_device(adap, &info);
1425 if (result == NULL) { 1295 if (result == NULL) {
1426 dev_err(&adap->dev, "of_i2c: Failure registering %s\n", 1296 dev_err(&adap->dev, "of_i2c: Failure registering %s\n",
@@ -1796,11 +1666,15 @@ void i2c_del_adapter(struct i2c_adapter *adap)
1796 /* device name is gone after device_unregister */ 1666 /* device name is gone after device_unregister */
1797 dev_dbg(&adap->dev, "adapter [%s] unregistered\n", adap->name); 1667 dev_dbg(&adap->dev, "adapter [%s] unregistered\n", adap->name);
1798 1668
1799 /* clean up the sysfs representation */ 1669 /* wait until all references to the device are gone
1670 *
1671 * FIXME: This is old code and should ideally be replaced by an
1672 * alternative which results in decoupling the lifetime of the struct
1673 * device from the i2c_adapter, like spi or netdev do. Any solution
1674 * should be throughly tested with DEBUG_KOBJECT_RELEASE enabled!
1675 */
1800 init_completion(&adap->dev_released); 1676 init_completion(&adap->dev_released);
1801 device_unregister(&adap->dev); 1677 device_unregister(&adap->dev);
1802
1803 /* wait for sysfs to drop all references */
1804 wait_for_completion(&adap->dev_released); 1678 wait_for_completion(&adap->dev_released);
1805 1679
1806 /* free bus id */ 1680 /* free bus id */
@@ -1859,14 +1733,6 @@ int i2c_register_driver(struct module *owner, struct i2c_driver *driver)
1859 if (res) 1733 if (res)
1860 return res; 1734 return res;
1861 1735
1862 /* Drivers should switch to dev_pm_ops instead. */
1863 if (driver->suspend)
1864 pr_warn("i2c-core: driver [%s] using legacy suspend method\n",
1865 driver->driver.name);
1866 if (driver->resume)
1867 pr_warn("i2c-core: driver [%s] using legacy resume method\n",
1868 driver->driver.name);
1869
1870 pr_debug("i2c-core: driver [%s] registered\n", driver->driver.name); 1736 pr_debug("i2c-core: driver [%s] registered\n", driver->driver.name);
1871 1737
1872 INIT_LIST_HEAD(&driver->clients); 1738 INIT_LIST_HEAD(&driver->clients);
diff --git a/drivers/i2c/muxes/i2c-mux-pca954x.c b/drivers/i2c/muxes/i2c-mux-pca954x.c
index ec11b404b433..3d8f4fe2e47e 100644
--- a/drivers/i2c/muxes/i2c-mux-pca954x.c
+++ b/drivers/i2c/muxes/i2c-mux-pca954x.c
@@ -41,6 +41,7 @@
41#include <linux/i2c-mux.h> 41#include <linux/i2c-mux.h>
42#include <linux/i2c/pca954x.h> 42#include <linux/i2c/pca954x.h>
43#include <linux/module.h> 43#include <linux/module.h>
44#include <linux/of.h>
44#include <linux/pm.h> 45#include <linux/pm.h>
45#include <linux/slab.h> 46#include <linux/slab.h>
46 47
@@ -186,6 +187,8 @@ static int pca954x_probe(struct i2c_client *client,
186{ 187{
187 struct i2c_adapter *adap = to_i2c_adapter(client->dev.parent); 188 struct i2c_adapter *adap = to_i2c_adapter(client->dev.parent);
188 struct pca954x_platform_data *pdata = dev_get_platdata(&client->dev); 189 struct pca954x_platform_data *pdata = dev_get_platdata(&client->dev);
190 struct device_node *of_node = client->dev.of_node;
191 bool idle_disconnect_dt;
189 struct gpio_desc *gpio; 192 struct gpio_desc *gpio;
190 int num, force, class; 193 int num, force, class;
191 struct pca954x *data; 194 struct pca954x *data;
@@ -217,8 +220,13 @@ static int pca954x_probe(struct i2c_client *client,
217 data->type = id->driver_data; 220 data->type = id->driver_data;
218 data->last_chan = 0; /* force the first selection */ 221 data->last_chan = 0; /* force the first selection */
219 222
223 idle_disconnect_dt = of_node &&
224 of_property_read_bool(of_node, "i2c-mux-idle-disconnect");
225
220 /* Now create an adapter for each channel */ 226 /* Now create an adapter for each channel */
221 for (num = 0; num < chips[data->type].nchans; num++) { 227 for (num = 0; num < chips[data->type].nchans; num++) {
228 bool idle_disconnect_pd = false;
229
222 force = 0; /* dynamic adap number */ 230 force = 0; /* dynamic adap number */
223 class = 0; /* no class by default */ 231 class = 0; /* no class by default */
224 if (pdata) { 232 if (pdata) {
@@ -229,12 +237,13 @@ static int pca954x_probe(struct i2c_client *client,
229 } else 237 } else
230 /* discard unconfigured channels */ 238 /* discard unconfigured channels */
231 break; 239 break;
240 idle_disconnect_pd = pdata->modes[num].deselect_on_exit;
232 } 241 }
233 242
234 data->virt_adaps[num] = 243 data->virt_adaps[num] =
235 i2c_add_mux_adapter(adap, &client->dev, client, 244 i2c_add_mux_adapter(adap, &client->dev, client,
236 force, num, class, pca954x_select_chan, 245 force, num, class, pca954x_select_chan,
237 (pdata && pdata->modes[num].deselect_on_exit) 246 (idle_disconnect_pd || idle_disconnect_dt)
238 ? pca954x_deselect_mux : NULL); 247 ? pca954x_deselect_mux : NULL);
239 248
240 if (data->virt_adaps[num] == NULL) { 249 if (data->virt_adaps[num] == NULL) {
diff --git a/include/linux/i2c.h b/include/linux/i2c.h
index 7c7695940ddd..f17da50402a4 100644
--- a/include/linux/i2c.h
+++ b/include/linux/i2c.h
@@ -130,8 +130,6 @@ extern s32 i2c_smbus_write_i2c_block_data(const struct i2c_client *client,
130 * @probe: Callback for device binding 130 * @probe: Callback for device binding
131 * @remove: Callback for device unbinding 131 * @remove: Callback for device unbinding
132 * @shutdown: Callback for device shutdown 132 * @shutdown: Callback for device shutdown
133 * @suspend: Callback for device suspend
134 * @resume: Callback for device resume
135 * @alert: Alert callback, for example for the SMBus alert protocol 133 * @alert: Alert callback, for example for the SMBus alert protocol
136 * @command: Callback for bus-wide signaling (optional) 134 * @command: Callback for bus-wide signaling (optional)
137 * @driver: Device driver model driver 135 * @driver: Device driver model driver
@@ -174,8 +172,6 @@ struct i2c_driver {
174 172
175 /* driver model interfaces that don't relate to enumeration */ 173 /* driver model interfaces that don't relate to enumeration */
176 void (*shutdown)(struct i2c_client *); 174 void (*shutdown)(struct i2c_client *);
177 int (*suspend)(struct i2c_client *, pm_message_t mesg);
178 int (*resume)(struct i2c_client *);
179 175
180 /* Alert callback, for example for the SMBus alert protocol. 176 /* Alert callback, for example for the SMBus alert protocol.
181 * The format and meaning of the data value depends on the protocol. 177 * The format and meaning of the data value depends on the protocol.
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-23 17:01:43 -0400