Merge tag 'v4.15-next-dts64' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux into next/dt

Pull "arm64: Updates of aarch64 DTS for v4.15-next" from Matthias Brugger

- mt8173 add cpufreq related nodes
  supply nodes
  frequency/voltage operation table

- mt2712 add cpufreq related nodes
  fixed regulator
  supply nodes
  frequency/voltage operation table
- mt2712 add clock contoller nodes
- mt2712 add scpsys node

* tag 'v4.15-next-dts64' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux:
  arm64: dts: Add power controller device node of MT2712
  arm64: dts: mediatek: add mt2712 cpufreq related device nodes
  arm64: dts: mt2712: Add clock controller device nodes
  arm64: dts: mediatek: add mt8173 cpufreq related device nodes
  dt-bindings: soc: add MT2712 power dt-bindings

6 files changed, 352 insertions, 0 deletions

diff --git a/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt b/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt
index 40056f7990f8..76bf45b893fa 100644
--- a/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt
+++ b/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt
@@ -12,11 +12,13 @@ power/power_domain.txt. It provides the power domains defined in
 - include/dt-bindings/power/mt8173-power.h
 - include/dt-bindings/power/mt6797-power.h
 - include/dt-bindings/power/mt2701-power.h
+- include/dt-bindings/power/mt2712-power.h
 - include/dt-bindings/power/mt7622-power.h
 
 Required properties:
 - compatible: Should be one of:
         - "mediatek,mt2701-scpsys"
+        - "mediatek,mt2712-scpsys"
         - "mediatek,mt6797-scpsys"
         - "mediatek,mt7622-scpsys"
         - "mediatek,mt8173-scpsys"
@@ -27,6 +29,7 @@ Required properties:
                       These are clocks which hardware needs to be
                       enabled before enabling certain power domains.
         Required clocks for MT2701: "mm", "mfg", "ethif"
+        Required clocks for MT2712: "mm", "mfg", "venc", "jpgdec", "audio", "vdec"
         Required clocks for MT6797: "mm", "mfg", "vdec"
         Required clocks for MT7622: "hif_sel"
         Required clocks for MT8173: "mm", "mfg", "venc", "venc_lt"
diff --git a/arch/arm64/boot/dts/mediatek/mt2712-evb.dts b/arch/arm64/boot/dts/mediatek/mt2712-evb.dts
index 8c804df3da4e..10f9c76cd105 100644
--- a/arch/arm64/boot/dts/mediatek/mt2712-evb.dts
+++ b/arch/arm64/boot/dts/mediatek/mt2712-evb.dts
@@ -24,6 +24,33 @@
         chosen {
                 stdout-path = "serial0:921600n8";
         };
+
+        cpus_fixed_vproc0: fixedregulator@0 {
+                compatible = "regulator-fixed";
+                regulator-name = "vproc_buck0";
+                regulator-min-microvolt = <1000000>;
+                regulator-max-microvolt = <1000000>;
+        };
+
+        cpus_fixed_vproc1: fixedregulator@1 {
+                compatible = "regulator-fixed";
+                regulator-name = "vproc_buck1";
+                regulator-min-microvolt = <1000000>;
+                regulator-max-microvolt = <1000000>;
+        };
+
+};
+
+&cpu0 {
+        proc-supply = <&cpus_fixed_vproc0>;
+};
+
+&cpu1 {
+        proc-supply = <&cpus_fixed_vproc0>;
+};
+
+&cpu2 {
+        proc-supply = <&cpus_fixed_vproc1>;
 };
 
 &uart0 {
diff --git a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
index 5d4e406bb35d..fdf66f4fe7c3 100644
--- a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
@@ -5,8 +5,10 @@
  * SPDX-License-Identifier: (GPL-2.0 OR MIT)
  */
 
+#include <dt-bindings/clock/mt2712-clk.h>
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/power/mt2712-power.h>
 
 / {
         compatible = "mediatek,mt2712";
@@ -14,6 +16,48 @@
         #address-cells = <2>;
         #size-cells = <2>;
 
+        cluster0_opp: opp_table0 {
+                compatible = "operating-points-v2";
+                opp-shared;
+                opp00 {
+                        opp-hz = /bits/ 64 <598000000>;
+                        opp-microvolt = <1000000>;
+                };
+                opp01 {
+                        opp-hz = /bits/ 64 <702000000>;
+                        opp-microvolt = <1000000>;
+                };
+                opp02 {
+                        opp-hz = /bits/ 64 <793000000>;
+                        opp-microvolt = <1000000>;
+                };
+        };
+
+        cluster1_opp: opp_table1 {
+                compatible = "operating-points-v2";
+                opp-shared;
+                opp00 {
+                        opp-hz = /bits/ 64 <598000000>;
+                        opp-microvolt = <1000000>;
+                };
+                opp01 {
+                        opp-hz = /bits/ 64 <702000000>;
+                        opp-microvolt = <1000000>;
+                };
+                opp02 {
+                        opp-hz = /bits/ 64 <793000000>;
+                        opp-microvolt = <1000000>;
+                };
+                opp03 {
+                        opp-hz = /bits/ 64 <897000000>;
+                        opp-microvolt = <1000000>;
+                };
+                opp04 {
+                        opp-hz = /bits/ 64 <1001000000>;
+                        opp-microvolt = <1000000>;
+                };
+        };
+
         cpus {
                 #address-cells = <1>;
                 #size-cells = <0>;
@@ -39,6 +83,11 @@
                         device_type = "cpu";
                         compatible = "arm,cortex-a35";
                         reg = <0x000>;
+                        clocks = <&mcucfg CLK_MCU_MP0_SEL>,
+                                <&topckgen CLK_TOP_F_MP0_PLL1>;
+                        clock-names = "cpu", "intermediate";
+                        proc-supply = <&cpus_fixed_vproc0>;
+                        operating-points-v2 = <&cluster0_opp>;
                         cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
                 };
 
@@ -47,6 +96,11 @@
                         compatible = "arm,cortex-a35";
                         reg = <0x001>;
                         enable-method = "psci";
+                        clocks = <&mcucfg CLK_MCU_MP0_SEL>,
+                                <&topckgen CLK_TOP_F_MP0_PLL1>;
+                        clock-names = "cpu", "intermediate";
+                        proc-supply = <&cpus_fixed_vproc0>;
+                        operating-points-v2 = <&cluster0_opp>;
                         cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
                 };
 
@@ -55,6 +109,11 @@
                         compatible = "arm,cortex-a72";
                         reg = <0x200>;
                         enable-method = "psci";
+                        clocks = <&mcucfg CLK_MCU_MP2_SEL>,
+                                <&topckgen CLK_TOP_F_BIG_PLL1>;
+                        clock-names = "cpu", "intermediate";
+                        proc-supply = <&cpus_fixed_vproc1>;
+                        operating-points-v2 = <&cluster1_opp>;
                         cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
                 };
 
@@ -98,6 +157,48 @@
                 #clock-cells = <0>;
         };
 
+        clk26m: oscillator@0 {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <26000000>;
+                clock-output-names = "clk26m";
+        };
+
+        clk32k: oscillator@1 {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <32768>;
+                clock-output-names = "clk32k";
+        };
+
+        clkfpc: oscillator@2 {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <50000000>;
+                clock-output-names = "clkfpc";
+        };
+
+        clkaud_ext_i_0: oscillator@3 {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <6500000>;
+                clock-output-names = "clkaud_ext_i_0";
+        };
+
+        clkaud_ext_i_1: oscillator@4 {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <196608000>;
+                clock-output-names = "clkaud_ext_i_1";
+        };
+
+        clkaud_ext_i_2: oscillator@5 {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <180633600>;
+                clock-output-names = "clkaud_ext_i_2";
+        };
+
         timer {
                 compatible = "arm,armv8-timer";
                 interrupt-parent = <&gic>;
@@ -111,6 +212,39 @@
                               (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_LOW)>;
         };
 
+        topckgen: syscon@10000000 {
+                compatible = "mediatek,mt2712-topckgen", "syscon";
+                reg = <0 0x10000000 0 0x1000>;
+                #clock-cells = <1>;
+        };
+
+        infracfg: syscon@10001000 {
+                compatible = "mediatek,mt2712-infracfg", "syscon";
+                reg = <0 0x10001000 0 0x1000>;
+                #clock-cells = <1>;
+        };
+
+        pericfg: syscon@10003000 {
+                compatible = "mediatek,mt2712-pericfg", "syscon";
+                reg = <0 0x10003000 0 0x1000>;
+                #clock-cells = <1>;
+        };
+
+        scpsys: scpsys@10006000 {
+                compatible = "mediatek,mt2712-scpsys", "syscon";
+                #power-domain-cells = <1>;
+                reg = <0 0x10006000 0 0x1000>;
+                clocks = <&topckgen CLK_TOP_MM_SEL>,
+                         <&topckgen CLK_TOP_MFG_SEL>,
+                         <&topckgen CLK_TOP_VENC_SEL>,
+                         <&topckgen CLK_TOP_JPGDEC_SEL>,
+                         <&topckgen CLK_TOP_A1SYS_HP_SEL>,
+                         <&topckgen CLK_TOP_VDEC_SEL>;
+                clock-names = "mm", "mfg", "venc",
+                        "jpgdec", "audio", "vdec";
+                infracfg = <&infracfg>;
+        };
+
         uart5: serial@1000f000 {
                 compatible = "mediatek,mt2712-uart",
                              "mediatek,mt6577-uart";
@@ -121,6 +255,18 @@
                 status = "disabled";
         };
 
+        apmixedsys: syscon@10209000 {
+                compatible = "mediatek,mt2712-apmixedsys", "syscon";
+                reg = <0 0x10209000 0 0x1000>;
+                #clock-cells = <1>;
+        };
+
+        mcucfg: syscon@10220000 {
+                compatible = "mediatek,mt2712-mcucfg", "syscon";
+                reg = <0 0x10220000 0 0x1000>;
+                #clock-cells = <1>;
+        };
+
         sysirq: interrupt-controller@10220a80 {
                 compatible = "mediatek,mt2712-sysirq",
                              "mediatek,mt6577-sysirq";
@@ -192,5 +338,47 @@
                 clock-names = "baud", "bus";
                 status = "disabled";
         };
+
+        mfgcfg: syscon@13000000 {
+                compatible = "mediatek,mt2712-mfgcfg", "syscon";
+                reg = <0 0x13000000 0 0x1000>;
+                #clock-cells = <1>;
+        };
+
+        mmsys: syscon@14000000 {
+                compatible = "mediatek,mt2712-mmsys", "syscon";
+                reg = <0 0x14000000 0 0x1000>;
+                #clock-cells = <1>;
+        };
+
+        imgsys: syscon@15000000 {
+                compatible = "mediatek,mt2712-imgsys", "syscon";
+                reg = <0 0x15000000 0 0x1000>;
+                #clock-cells = <1>;
+        };
+
+        bdpsys: syscon@15010000 {
+                compatible = "mediatek,mt2712-bdpsys", "syscon";
+                reg = <0 0x15010000 0 0x1000>;
+                #clock-cells = <1>;
+        };
+
+        vdecsys: syscon@16000000 {
+                compatible = "mediatek,mt2712-vdecsys", "syscon";
+                reg = <0 0x16000000 0 0x1000>;
+                #clock-cells = <1>;
+        };
+
+        vencsys: syscon@18000000 {
+                compatible = "mediatek,mt2712-vencsys", "syscon";
+                reg = <0 0x18000000 0 0x1000>;
+                #clock-cells = <1>;
+        };
+
+        jpgdecsys: syscon@19000000 {
+                compatible = "mediatek,mt2712-jpgdecsys", "syscon";
+                reg = <0 0x19000000 0 0x1000>;
+                #clock-cells = <1>;
+        };
 };
 
diff --git a/arch/arm64/boot/dts/mediatek/mt8173-evb.dts b/arch/arm64/boot/dts/mediatek/mt8173-evb.dts
index 1c3634fa94bf..369dfcdd2f97 100644
--- a/arch/arm64/boot/dts/mediatek/mt8173-evb.dts
+++ b/arch/arm64/boot/dts/mediatek/mt8173-evb.dts
@@ -74,6 +74,24 @@
         status = "okay";
 };
 
+&cpu0 {
+        proc-supply = <&mt6397_vpca15_reg>;
+};
+
+&cpu1 {
+        proc-supply = <&mt6397_vpca15_reg>;
+};
+
+&cpu2 {
+        proc-supply = <&da9211_vcpu_reg>;
+        sram-supply = <&mt6397_vsramca7_reg>;
+};
+
+&cpu3 {
+        proc-supply = <&da9211_vcpu_reg>;
+        sram-supply = <&mt6397_vsramca7_reg>;
+};
+
 &dpi0 {
         status = "okay";
 };
diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
index 26396ef53bde..31bc593cc71b 100644
--- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
@@ -51,6 +51,80 @@
                 mdp_wrot1 = &mdp_wrot1;
         };
 
+        cluster0_opp: opp_table0 {
+                compatible = "operating-points-v2";
+                opp-shared;
+                opp-507000000 {
+                        opp-hz = /bits/ 64 <507000000>;
+                        opp-microvolt = <859000>;
+                };
+                opp-702000000 {
+                        opp-hz = /bits/ 64 <702000000>;
+                        opp-microvolt = <908000>;
+                };
+                opp-1001000000 {
+                        opp-hz = /bits/ 64 <1001000000>;
+                        opp-microvolt = <983000>;
+                };
+                opp-1105000000 {
+                        opp-hz = /bits/ 64 <1105000000>;
+                        opp-microvolt = <1009000>;
+                };
+                opp-1209000000 {
+                        opp-hz = /bits/ 64 <1209000000>;
+                        opp-microvolt = <1034000>;
+                };
+                opp-1300000000 {
+                        opp-hz = /bits/ 64 <1300000000>;
+                        opp-microvolt = <1057000>;
+                };
+                opp-1508000000 {
+                        opp-hz = /bits/ 64 <1508000000>;
+                        opp-microvolt = <1109000>;
+                };
+                opp-1703000000 {
+                        opp-hz = /bits/ 64 <1703000000>;
+                        opp-microvolt = <1125000>;
+                };
+        };
+
+        cluster1_opp: opp_table1 {
+                compatible = "operating-points-v2";
+                opp-shared;
+                opp-507000000 {
+                        opp-hz = /bits/ 64 <507000000>;
+                        opp-microvolt = <828000>;
+                };
+                opp-702000000 {
+                        opp-hz = /bits/ 64 <702000000>;
+                        opp-microvolt = <867000>;
+                };
+                opp-1001000000 {
+                        opp-hz = /bits/ 64 <1001000000>;
+                        opp-microvolt = <927000>;
+                };
+                opp-1209000000 {
+                        opp-hz = /bits/ 64 <1209000000>;
+                        opp-microvolt = <968000>;
+                };
+                opp-1404000000 {
+                        opp-hz = /bits/ 64 <1404000000>;
+                        opp-microvolt = <1007000>;
+                };
+                opp-1612000000 {
+                        opp-hz = /bits/ 64 <1612000000>;
+                        opp-microvolt = <1049000>;
+                };
+                opp-1807000000 {
+                        opp-hz = /bits/ 64 <1807000000>;
+                        opp-microvolt = <1089000>;
+                };
+                opp-2106000000 {
+                        opp-hz = /bits/ 64 <2106000000>;
+                        opp-microvolt = <1125000>;
+                };
+        };
+
         cpus {
                 #address-cells = <1>;
                 #size-cells = <0>;
@@ -81,6 +155,10 @@
                         reg = <0x000>;
                         enable-method = "psci";
                         cpu-idle-states = <&CPU_SLEEP_0>;
+                        clocks = <&infracfg CLK_INFRA_CA53SEL>,
+                                 <&apmixedsys CLK_APMIXED_MAINPLL>;
+                        clock-names = "cpu", "intermediate";
+                        operating-points-v2 = <&cluster0_opp>;
                 };
 
                 cpu1: cpu@1 {
@@ -89,6 +167,10 @@
                         reg = <0x001>;
                         enable-method = "psci";
                         cpu-idle-states = <&CPU_SLEEP_0>;
+                        clocks = <&infracfg CLK_INFRA_CA53SEL>,
+                                 <&apmixedsys CLK_APMIXED_MAINPLL>;
+                        clock-names = "cpu", "intermediate";
+                        operating-points-v2 = <&cluster0_opp>;
                 };
 
                 cpu2: cpu@100 {
@@ -97,6 +179,10 @@
                         reg = <0x100>;
                         enable-method = "psci";
                         cpu-idle-states = <&CPU_SLEEP_0>;
+                        clocks = <&infracfg CLK_INFRA_CA57SEL>,
+                                 <&apmixedsys CLK_APMIXED_MAINPLL>;
+                        clock-names = "cpu", "intermediate";
+                        operating-points-v2 = <&cluster1_opp>;
                 };
 
                 cpu3: cpu@101 {
@@ -105,6 +191,10 @@
                         reg = <0x101>;
                         enable-method = "psci";
                         cpu-idle-states = <&CPU_SLEEP_0>;
+                        clocks = <&infracfg CLK_INFRA_CA57SEL>,
+                                 <&apmixedsys CLK_APMIXED_MAINPLL>;
+                        clock-names = "cpu", "intermediate";
+                        operating-points-v2 = <&cluster1_opp>;
                 };
 
                 idle-states {
diff --git a/include/dt-bindings/power/mt2712-power.h b/include/dt-bindings/power/mt2712-power.h
new file mode 100644
index 000000000000..92b46d772fae
--- /dev/null
+++ b/include/dt-bindings/power/mt2712-power.h
@@ -0,0 +1,26 @@
+/*
+ * Copyright (C) 2017 MediaTek Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See http://www.gnu.org/licenses/gpl-2.0.html for more details.
+ */
+
+#ifndef _DT_BINDINGS_POWER_MT2712_POWER_H
+#define _DT_BINDINGS_POWER_MT2712_POWER_H
+
+#define MT2712_POWER_DOMAIN_MM          0
+#define MT2712_POWER_DOMAIN_VDEC        1
+#define MT2712_POWER_DOMAIN_VENC        2
+#define MT2712_POWER_DOMAIN_ISP         3
+#define MT2712_POWER_DOMAIN_AUDIO       4
+#define MT2712_POWER_DOMAIN_USB         5
+#define MT2712_POWER_DOMAIN_USB2        6
+#define MT2712_POWER_DOMAIN_MFG         7
+
+#endif /* _DT_BINDINGS_POWER_MT2712_POWER_H */