aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorArnd Bergmann <arnd@arndb.de>2016-09-14 11:24:08 -0400
committerArnd Bergmann <arnd@arndb.de>2016-09-14 11:25:32 -0400
commit291e287b97a665360875d52b649ed80506c9c51d (patch)
treed3618265c2cb2e128b9d863535ca18c61e243094
parent3073be6c29487ca81fcb5efd1748249a6f153c17 (diff)
parentf606193a10e7d0eb6766ae525e9051417a59f8d9 (diff)
Merge tag 'v4.9-rockchip-dts64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into next/dt64
Pull "Rockchip dts64 changes for 4.9" from Heiko Stübner: 64bit Rockchip devicetree changes containing support for the recently added firmware reboot-flag support, one new board the Tronsmart Orion based on the rk3368 and a large number of newly supported peripherals for the rk3399 (type-c phy, usb2 phy, pcie controller and pcie phy, gmac, arm-pmu using ppi partitioning, efuse, saradc) as well as some smaller housekeeping and non-critical fixes. * tag 'v4.9-rockchip-dts64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: (22 commits) arm64: dts: rockchip: add Type-C phy for RK3399 arm64: dts: rockchip: enable the gmac for rk3399 evb board arm64: dts: rockchip: add the gmac needed node for rk3399 arm64: dts: rockchip: support the pmu node for rk3399 arm64: dts: rockchip: change all interrupts cells to 4 on rk3399 SoCs arm64: dts: rockchip: add the tcpc for rk3399 power domain arm64: dts: rockchip: add efuse0 device node for rk3399 arm64: dts: rockchip: configure PCIe support for rk3399-evb arm64: dts: rockchip: add the PCIe controller support for RK3399 arm64: dts: rockchip: add the PCIe PHY for RK3399 arm64: dts: rockchip: add the gmac power domain on rk3399 arm64: dts: rockchip: Add pinctrl entry for 32k clock on rk3399 arm64: dts: rockchip: set to CCI clock of RK3399 to 600M arm64: dts: rockchip: fix the address map for WDT0 and WDT1 arm64: dts: rockchip: add the saradc for rk3399 arm64: dts: rockchip: configure usb2-phy support for rk3399-evb arm64: dts: rockchip: add usb2-phy support for rk3399 arm64: dts: rockchip: add syscon-reboot-mode DT node soc: rockchip: add reboot-mode header arm64: dts: rockchip: remove broken-cd from sdio0 ...
Diffstat
-rw-r--r--Documentation/devicetree/bindings/arm/rockchip.txt4
-rw-r--r--arch/arm64/boot/dts/rockchip/Makefile1
-rw-r--r--arch/arm64/boot/dts/rockchip/rk3368-orion-r68-meta.dts382
-rw-r--r--arch/arm64/boot/dts/rockchip/rk3368-r88.dts1
-rw-r--r--arch/arm64/boot/dts/rockchip/rk3368.dtsi10
-rw-r--r--arch/arm64/boot/dts/rockchip/rk3399-evb.dts87
-rw-r--r--arch/arm64/boot/dts/rockchip/rk3399.dtsi607
-rw-r--r--include/dt-bindings/soc/rockchip,boot-mode.h15
8 files changed, 1053 insertions, 54 deletions
diff --git a/Documentation/devicetree/bindings/arm/rockchip.txt b/Documentation/devicetree/bindings/arm/rockchip.txt
index 666864517069..41efeece2e79 100644
--- a/Documentation/devicetree/bindings/arm/rockchip.txt
+++ b/Documentation/devicetree/bindings/arm/rockchip.txt
@@ -113,3 +113,7 @@ Rockchip platforms device tree bindings
113- Rockchip RK3399 evb: 113- Rockchip RK3399 evb:
114 Required root node properties: 114 Required root node properties:
115 - compatible = "rockchip,rk3399-evb", "rockchip,rk3399"; 115 - compatible = "rockchip,rk3399-evb", "rockchip,rk3399";
116
117- Tronsmart Orion R68 Meta
118 Required root node properties:
119 - compatible = "tronsmart,orion-r68-meta", "rockchip,rk3368";
diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile
index 7037a161b6ef..87669f656454 100644
--- a/arch/arm64/boot/dts/rockchip/Makefile
+++ b/arch/arm64/boot/dts/rockchip/Makefile
@@ -1,5 +1,6 @@
1dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-evb-act8846.dtb 1dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-evb-act8846.dtb
2dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-geekbox.dtb 2dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-geekbox.dtb
3dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-orion-r68-meta.dtb
3dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-r88.dtb 4dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-r88.dtb
4dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-evb.dtb 5dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-evb.dtb
5 6
diff --git a/arch/arm64/boot/dts/rockchip/rk3368-orion-r68-meta.dts b/arch/arm64/boot/dts/rockchip/rk3368-orion-r68-meta.dts
new file mode 100644
index 000000000000..5797933ef80e
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3368-orion-r68-meta.dts
@@ -0,0 +1,382 @@
1/*
2 * Copyright (c) 2016 Matthias Brugger <mbrugger@suse.com>
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
13 *
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * Or, alternatively,
20 *
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
28 * conditions:
29 *
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
32 *
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
41 */
42
43/dts-v1/;
44#include <dt-bindings/input/input.h>
45#include "rk3368.dtsi"
46
47/ {
48 model = "Rockchip Orion R68";
49 compatible = "tronsmart,orion-r68-meta", "rockchip,rk3368";
50
51 chosen {
52 stdout-path = "serial2:115200n8";
53 };
54
55 memory {
56 device_type = "memory";
57 reg = <0x0 0x0 0x0 0x80000000>;
58 };
59
60 emmc_pwrseq: emmc-pwrseq {
61 compatible = "mmc-pwrseq-emmc";
62 pinctrl-0 = <&emmc_reset>;
63 pinctrl-names = "default";
64 reset-gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>;
65 };
66
67 ext_gmac: external-gmac-clock {
68 compatible = "fixed-clock";
69 #clock-cells = <0>;
70 clock-frequency = <125000000>;
71 clock-output-names = "ext_gmac";
72 };
73
74 keys: gpio-keys {
75 compatible = "gpio-keys";
76 pinctrl-names = "default";
77 pinctrl-0 = <&pwr_key>;
78
79 power {
80 wakeup-source;
81 gpios = <&gpio0 5 GPIO_ACTIVE_HIGH>;
82 label = "GPIO Power";
83 linux,code = <KEY_POWER>;
84 };
85 };
86
87 leds: gpio-leds {
88 compatible = "gpio-leds";
89
90 red {
91 gpios = <&gpio3 29 GPIO_ACTIVE_HIGH>;
92 label = "orion:red:led";
93 pinctrl-names = "default";
94 pinctrl-0 = <&led_ctl>;
95 default-state = "on";
96 };
97
98 blue {
99 gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>;
100 label = "orion:blue:led";
101 pinctrl-names = "default";
102 pinctrl-0 = <&stby_pwren>;
103 default-state = "off";
104 };
105 };
106
107 vcc_18: vcc18-regulator {
108 compatible = "regulator-fixed";
109 regulator-name = "vcc_18";
110 regulator-min-microvolt = <1800000>;
111 regulator-max-microvolt = <1800000>;
112 regulator-always-on;
113 regulator-boot-on;
114 vin-supply = <&vcc_sys>;
115 };
116
117 /* supplies both host and otg */
118 vcc_host: vcc-host-regulator {
119 compatible = "regulator-fixed";
120 gpio = <&gpio0 4 GPIO_ACTIVE_LOW>;
121 pinctrl-names = "default";
122 pinctrl-0 = <&host_vbus_drv>;
123 regulator-name = "vcc_host";
124 regulator-always-on;
125 regulator-boot-on;
126 vin-supply = <&vcc_sys>;
127 };
128
129 vcc_io: vcc-io-regulator {
130 compatible = "regulator-fixed";
131 regulator-name = "vcc_io";
132 regulator-min-microvolt = <3300000>;
133 regulator-max-microvolt = <3300000>;
134 regulator-always-on;
135 regulator-boot-on;
136 vin-supply = <&vcc_sys>;
137 };
138
139 vcc_lan: vcc-lan-regulator {
140 compatible = "regulator-fixed";
141 regulator-name = "vcc_lan";
142 regulator-min-microvolt = <3300000>;
143 regulator-max-microvolt = <3300000>;
144 regulator-always-on;
145 regulator-boot-on;
146 vin-supply = <&vcc_io>;
147 };
148
149 vcc_sd: vcc-sd-regulator {
150 compatible = "regulator-fixed";
151 regulator-name = "vcc_sd";
152 gpio = <&gpio3 11 GPIO_ACTIVE_LOW>;
153 regulator-min-microvolt = <1800000>;
154 regulator-max-microvolt = <3300000>;
155 regulator-always-on;
156 regulator-boot-on;
157 vin-supply = <&vcc_io>;
158 };
159
160 vcc_sys: vcc-sys-regulator {
161 compatible = "regulator-fixed";
162 regulator-name = "vcc_sys";
163 regulator-min-microvolt = <5000000>;
164 regulator-max-microvolt = <5000000>;
165 regulator-always-on;
166 regulator-boot-on;
167 };
168
169 vccio_sd: vcc-io-sd-regulator {
170 compatible = "regulator-fixed";
171 regulator-name= "vccio_sd";
172 regulator-min-microvolt = <1800000>;
173 regulator-max-microvolt = <3300000>;
174 regulator-always-on;
175 regulator-boot-on;
176 vin-supply = <&vcc_io>;
177 };
178
179 vccio_wl: vccio-wl-regulator {
180 compatible = "regulator-fixed";
181 regulator-name = "vccio_wl";
182 regulator-min-microvolt = <3300000>;
183 regulator-max-microvolt = <3300000>;
184 regulator-always-on;
185 regulator-boot-on;
186 vin-supply = <&vcc_io>;
187 };
188
189 vdd_10: vdd-10-regulator {
190 compatible = "regulator-fixed";
191 regulator-name = "vdd_10";
192 regulator-min-microvolt = <1000000>;
193 regulator-max-microvolt = <1000000>;
194 regulator-always-on;
195 regulator-boot-on;
196 vin-supply = <&vcc_sys>;
197 };
198};
199
200&emmc {
201 bus-width = <8>;
202 cap-mmc-highspeed;
203 disable-wp;
204 keep-power-in-suspend;
205 mmc-pwrseq = <&emmc_pwrseq>;
206 mmc-hs200-1_2v;
207 mmc-hs200-1_8v;
208 non-removable;
209 num-slots = <1>;
210 pinctrl-names = "default";
211 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
212 status = "okay";
213};
214
215&gmac {
216 assigned-clocks = <&cru SCLK_MAC>;
217 assigned-clock-parents = <&ext_gmac>;
218 clock_in_out = "input";
219 phy-supply = <&vcc_lan>;
220 phy-mode = "rgmii";
221 pinctrl-names = "default";
222 pinctrl-0 = <&rgmii_pins>;
223 snps,reset-gpio = <&gpio3 12 0>;
224 snps,reset-active-low;
225 snps,reset-delays-us = <0 10000 1000000>;
226 tx_delay = <0x30>;
227 rx_delay = <0x10>;
228 status = "ok";
229};
230
231&i2c0 {
232 status = "okay";
233
234 vdd_cpu: syr827@40 {
235 compatible = "silergy,syr827";
236 reg = <0x40>;
237 fcs,suspend-voltage-selector = <1>;
238 regulator-name = "vdd_cpu";
239 regulator-enable-ramp-delay = <300>;
240 regulator-min-microvolt = <712500>;
241 regulator-max-microvolt = <1500000>;
242 regulator-ramp-delay = <8000>;
243 regulator-always-on;
244 regulator-boot-on;
245 vin-supply = <&vcc_sys>;
246 };
247
248 hym8563: hym8563@51 {
249 compatible = "haoyu,hym8563";
250 reg = <0x51>;
251 #clock-cells = <0>;
252 clock-frequency = <32768>;
253 clock-output-names = "xin32k";
254 /* rtc_int is not connected */
255 };
256};
257
258&pinctrl {
259 pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma {
260 bias-disable;
261 drive-strength = <8>;
262 };
263
264 pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma {
265 bias-pull-up;
266 drive-strength = <8>;
267 };
268
269 emmc {
270 emmc_bus8: emmc-bus8 {
271 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,
272 <1 19 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,
273 <1 20 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,
274 <1 21 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,
275 <1 22 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,
276 <1 23 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,
277 <1 24 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,
278 <1 25 RK_FUNC_2 &pcfg_pull_up_drv_8ma>;
279 };
280
281 emmc-clk {
282 rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none_drv_8ma>;
283 };
284
285 emmc-cmd {
286 rockchip,pins = <1 26 RK_FUNC_2 &pcfg_pull_up_drv_8ma>;
287 };
288
289 emmc_reset: emmc-reset {
290 rockchip,pins = <2 3 RK_FUNC_GPIO &pcfg_pull_none>;
291 };
292 };
293
294 keys {
295 pwr_key: pwr-key {
296 rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_down>;
297 };
298 };
299
300 leds {
301 stby_pwren: stby-pwren {
302 rockchip,pins = <0 12 RK_FUNC_GPIO &pcfg_pull_none>;
303 };
304
305 led_ctl: led-ctl {
306 rockchip,pins = <3 29 RK_FUNC_GPIO &pcfg_pull_none>;
307 };
308 };
309
310 sdmmc {
311 sdmmc_clk: sdmmc-clk {
312 rockchip,pins = <2 9 RK_FUNC_1 &pcfg_pull_none_drv_8ma>;
313 };
314
315 sdmmc_cmd: sdmmc-cmd {
316 rockchip,pins = <2 10 RK_FUNC_1 &pcfg_pull_up_drv_8ma>;
317 };
318
319 sdmmc_cd: sdmmc-cd {
320 rockchip,pins = <2 11 RK_FUNC_1 &pcfg_pull_up_drv_8ma>;
321 };
322
323 sdmmc_bus1: sdmmc-bus1 {
324 rockchip,pins = <2 5 RK_FUNC_1 &pcfg_pull_up_drv_8ma>;
325 };
326
327 sdmmc_bus4: sdmmc-bus4 {
328 rockchip,pins = <2 5 RK_FUNC_1 &pcfg_pull_up_drv_8ma>,
329 <2 6 RK_FUNC_1 &pcfg_pull_up_drv_8ma>,
330 <2 7 RK_FUNC_1 &pcfg_pull_up_drv_8ma>,
331 <2 8 RK_FUNC_1 &pcfg_pull_up_drv_8ma>;
332 };
333 };
334
335 usb {
336 host_vbus_drv: host-vbus-drv {
337 rockchip,pins = <0 4 RK_FUNC_GPIO &pcfg_pull_none>;
338 };
339 };
340};
341
342&saradc {
343 vref-supply = <&vcc_18>;
344 status = "okay";
345};
346
347&sdmmc {
348 bus-width = <4>;
349 clock-frequency = <50000000>;
350 clock-freq-min-max = <400000 50000000>;
351 cap-sd-highspeed;
352 card-detect-delay = <200>;
353 keep-power-in-suspend;
354 num-slots = <1>;
355 pinctrl-names = "default";
356 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
357 vmmc-supply = <&vcc_sd>;
358 vqmmc-supply = <&vccio_sd>;
359 status = "okay";
360};
361
362&uart2 {
363 status = "okay";
364};
365
366&uart4 {
367 pinctrl-names = "default";
368 pinctrl-0 = <&uart4_xfer>;
369 status = "okay";
370};
371
372&usb_host0_ehci {
373 status = "okay";
374};
375
376&usb_otg {
377 status = "okay";
378};
379
380&wdt {
381 status = "okay";
382};
diff --git a/arch/arm64/boot/dts/rockchip/rk3368-r88.dts b/arch/arm64/boot/dts/rockchip/rk3368-r88.dts
index 82a32e5591e2..eed1ef6669ff 100644
--- a/arch/arm64/boot/dts/rockchip/rk3368-r88.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3368-r88.dts
@@ -248,7 +248,6 @@
248&sdio0 { 248&sdio0 {
249 assigned-clocks = <&cru SCLK_SDIO0>; 249 assigned-clocks = <&cru SCLK_SDIO0>;
250 assigned-clock-parents = <&cru PLL_CPLL>; 250 assigned-clock-parents = <&cru PLL_CPLL>;
251 broken-cd;
252 bus-width = <4>; 251 bus-width = <4>;
253 cap-sd-highspeed; 252 cap-sd-highspeed;
254 cap-sdio-irq; 253 cap-sdio-irq;
diff --git a/arch/arm64/boot/dts/rockchip/rk3368.dtsi b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
index d02a900378e1..6a5eeea44b63 100644
--- a/arch/arm64/boot/dts/rockchip/rk3368.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
@@ -45,6 +45,7 @@
45#include <dt-bindings/interrupt-controller/irq.h> 45#include <dt-bindings/interrupt-controller/irq.h>
46#include <dt-bindings/interrupt-controller/arm-gic.h> 46#include <dt-bindings/interrupt-controller/arm-gic.h>
47#include <dt-bindings/pinctrl/rockchip.h> 47#include <dt-bindings/pinctrl/rockchip.h>
48#include <dt-bindings/soc/rockchip,boot-mode.h>
48#include <dt-bindings/thermal/thermal.h> 49#include <dt-bindings/thermal/thermal.h>
49 50
50/ { 51/ {
@@ -639,6 +640,15 @@
639 compatible = "rockchip,rk3368-pmu-io-voltage-domain"; 640 compatible = "rockchip,rk3368-pmu-io-voltage-domain";
640 status = "disabled"; 641 status = "disabled";
641 }; 642 };
643
644 reboot-mode {
645 compatible = "syscon-reboot-mode";
646 offset = <0x200>;
647 mode-normal = <BOOT_NORMAL>;
648 mode-recovery = <BOOT_RECOVERY>;
649 mode-bootloader = <BOOT_FASTBOOT>;
650 mode-loader = <BOOT_BL_DOWNLOAD>;
651 };
642 }; 652 };
643 653
644 cru: clock-controller@ff760000 { 654 cru: clock-controller@ff760000 {
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-evb.dts b/arch/arm64/boot/dts/rockchip/rk3399-evb.dts
index d33aa06d46f5..8e82497925fe 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-evb.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3399-evb.dts
@@ -49,6 +49,13 @@
49 compatible = "rockchip,rk3399-evb", "rockchip,rk3399", 49 compatible = "rockchip,rk3399-evb", "rockchip,rk3399",
50 "google,rk3399evb-rev2"; 50 "google,rk3399evb-rev2";
51 51
52 clkin_gmac: external-gmac-clock {
53 compatible = "fixed-clock";
54 clock-frequency = <125000000>;
55 clock-output-names = "clkin_gmac";
56 #clock-cells = <0>;
57 };
58
52 vdd_center: vdd-center { 59 vdd_center: vdd-center {
53 compatible = "pwm-regulator"; 60 compatible = "pwm-regulator";
54 pwms = <&pwm3 0 25000 0>; 61 pwms = <&pwm3 0 25000 0>;
@@ -69,18 +76,61 @@
69 regulator-max-microvolt = <3300000>; 76 regulator-max-microvolt = <3300000>;
70 }; 77 };
71 78
79 vcc5v0_sys: vcc5v0-sys {
80 compatible = "regulator-fixed";
81 regulator-name = "vcc5v0_sys";
82 regulator-always-on;
83 regulator-boot-on;
84 regulator-min-microvolt = <5000000>;
85 regulator-max-microvolt = <5000000>;
86 };
87
88 vcc5v0_host: vcc5v0-host-regulator {
89 compatible = "regulator-fixed";
90 enable-active-high;
91 gpio = <&gpio4 25 GPIO_ACTIVE_HIGH>;
92 pinctrl-names = "default";
93 pinctrl-0 = <&vcc5v0_host_en>;
94 regulator-name = "vcc5v0_host";
95 vin-supply = <&vcc5v0_sys>;
96 };
97
72 vcc_phy: vcc-phy-regulator { 98 vcc_phy: vcc-phy-regulator {
73 compatible = "regulator-fixed"; 99 compatible = "regulator-fixed";
74 regulator-name = "vcc_phy"; 100 regulator-name = "vcc_phy";
75 regulator-always-on; 101 regulator-always-on;
76 regulator-boot-on; 102 regulator-boot-on;
77 }; 103 };
104
105 vcc_phy: vcc-phy-regulator {
106 compatible = "regulator-fixed";
107 regulator-name = "vcc_phy";
108 regulator-always-on;
109 regulator-boot-on;
110 };
111
78}; 112};
79 113
80&emmc_phy { 114&emmc_phy {
81 status = "okay"; 115 status = "okay";
82}; 116};
83 117
118&gmac {
119 assigned-clocks = <&cru SCLK_RMII_SRC>;
120 assigned-clock-parents = <&clkin_gmac>;
121 clock_in_out = "input";
122 phy-supply = <&vcc_phy>;
123 phy-mode = "rgmii";
124 pinctrl-names = "default";
125 pinctrl-0 = <&rgmii_pins>;
126 snps,reset-gpio = <&gpio3 15 GPIO_ACTIVE_LOW>;
127 snps,reset-active-low;
128 snps,reset-delays-us = <0 10000 50000>;
129 tx_delay = <0x28>;
130 rx_delay = <0x11>;
131 status = "okay";
132};
133
84&pwm0 { 134&pwm0 {
85 status = "okay"; 135 status = "okay";
86}; 136};
@@ -101,6 +151,36 @@
101 status = "okay"; 151 status = "okay";
102}; 152};
103 153
154&pcie_phy {
155 status = "disabled";
156};
157
158&pcie0 {
159 ep-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;
160 num-lanes = <4>;
161 pinctrl-names = "default";
162 pinctrl-0 = <&pcie_clkreqn>;
163 status = "disabled";
164};
165
166&u2phy0 {
167 status = "okay";
168};
169
170&u2phy0_host {
171 phy-supply = <&vcc5v0_host>;
172 status = "okay";
173};
174
175&u2phy1 {
176 status = "okay";
177};
178
179&u2phy1_host {
180 phy-supply = <&vcc5v0_host>;
181 status = "okay";
182};
183
104&uart2 { 184&uart2 {
105 status = "okay"; 185 status = "okay";
106}; 186};
@@ -133,4 +213,11 @@
133 <1 18 RK_FUNC_GPIO &pcfg_pull_down>; 213 <1 18 RK_FUNC_GPIO &pcfg_pull_down>;
134 }; 214 };
135 }; 215 };
216
217 usb2 {
218 vcc5v0_host_en: vcc5v0-host-en {
219 rockchip,pins =
220 <4 25 RK_FUNC_GPIO &pcfg_pull_none>;
221 };
222 };
136}; 223};
diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index a6dd623a8845..b65c193dc64e 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -45,6 +45,7 @@
45#include <dt-bindings/interrupt-controller/arm-gic.h> 45#include <dt-bindings/interrupt-controller/arm-gic.h>
46#include <dt-bindings/interrupt-controller/irq.h> 46#include <dt-bindings/interrupt-controller/irq.h>
47#include <dt-bindings/pinctrl/rockchip.h> 47#include <dt-bindings/pinctrl/rockchip.h>
48#include <dt-bindings/power/rk3399-power.h>
48#include <dt-bindings/thermal/thermal.h> 49#include <dt-bindings/thermal/thermal.h>
49 50
50/ { 51/ {
@@ -152,6 +153,16 @@
152 }; 153 };
153 }; 154 };
154 155
156 pmu_a53 {
157 compatible = "arm,cortex-a53-pmu";
158 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>;
159 };
160
161 pmu_a72 {
162 compatible = "arm,cortex-a72-pmu";
163 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster1>;
164 };
165
155 psci { 166 psci {
156 compatible = "arm,psci-1.0"; 167 compatible = "arm,psci-1.0";
157 method = "smc"; 168 method = "smc";
@@ -159,10 +170,10 @@
159 170
160 timer { 171 timer {
161 compatible = "arm,armv8-timer"; 172 compatible = "arm,armv8-timer";
162 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 173 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>,
163 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 174 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>,
164 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 175 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>,
165 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 176 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>;
166 }; 177 };
167 178
168 xin24m: xin24m { 179 xin24m: xin24m {
@@ -181,8 +192,8 @@
181 dmac_bus: dma-controller@ff6d0000 { 192 dmac_bus: dma-controller@ff6d0000 {
182 compatible = "arm,pl330", "arm,primecell"; 193 compatible = "arm,pl330", "arm,primecell";
183 reg = <0x0 0xff6d0000 0x0 0x4000>; 194 reg = <0x0 0xff6d0000 0x0 0x4000>;
184 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 195 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH 0>,
185 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 196 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0>;
186 #dma-cells = <1>; 197 #dma-cells = <1>;
187 clocks = <&cru ACLK_DMAC0_PERILP>; 198 clocks = <&cru ACLK_DMAC0_PERILP>;
188 clock-names = "apb_pclk"; 199 clock-names = "apb_pclk";
@@ -191,19 +202,39 @@
191 dmac_peri: dma-controller@ff6e0000 { 202 dmac_peri: dma-controller@ff6e0000 {
192 compatible = "arm,pl330", "arm,primecell"; 203 compatible = "arm,pl330", "arm,primecell";
193 reg = <0x0 0xff6e0000 0x0 0x4000>; 204 reg = <0x0 0xff6e0000 0x0 0x4000>;
194 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 205 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH 0>,
195 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 206 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0>;
196 #dma-cells = <1>; 207 #dma-cells = <1>;
197 clocks = <&cru ACLK_DMAC1_PERILP>; 208 clocks = <&cru ACLK_DMAC1_PERILP>;
198 clock-names = "apb_pclk"; 209 clock-names = "apb_pclk";
199 }; 210 };
200 }; 211 };
201 212
213 gmac: ethernet@fe300000 {
214 compatible = "rockchip,rk3399-gmac";
215 reg = <0x0 0xfe300000 0x0 0x10000>;
216 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH 0>;
217 interrupt-names = "macirq";
218 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
219 <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>,
220 <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>,
221 <&cru PCLK_GMAC>;
222 clock-names = "stmmaceth", "mac_clk_rx",
223 "mac_clk_tx", "clk_mac_ref",
224 "clk_mac_refout", "aclk_mac",
225 "pclk_mac";
226 power-domains = <&power RK3399_PD_GMAC>;
227 resets = <&cru SRST_A_GMAC>;
228 reset-names = "stmmaceth";
229 rockchip,grf = <&grf>;
230 status = "disabled";
231 };
232
202 sdio0: dwmmc@fe310000 { 233 sdio0: dwmmc@fe310000 {
203 compatible = "rockchip,rk3399-dw-mshc", 234 compatible = "rockchip,rk3399-dw-mshc",
204 "rockchip,rk3288-dw-mshc"; 235 "rockchip,rk3288-dw-mshc";
205 reg = <0x0 0xfe310000 0x0 0x4000>; 236 reg = <0x0 0xfe310000 0x0 0x4000>;
206 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 237 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH 0>;
207 clock-freq-min-max = <400000 150000000>; 238 clock-freq-min-max = <400000 150000000>;
208 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, 239 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
209 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 240 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
@@ -216,7 +247,7 @@
216 compatible = "rockchip,rk3399-dw-mshc", 247 compatible = "rockchip,rk3399-dw-mshc",
217 "rockchip,rk3288-dw-mshc"; 248 "rockchip,rk3288-dw-mshc";
218 reg = <0x0 0xfe320000 0x0 0x4000>; 249 reg = <0x0 0xfe320000 0x0 0x4000>;
219 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 250 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>;
220 clock-freq-min-max = <400000 150000000>; 251 clock-freq-min-max = <400000 150000000>;
221 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 252 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
222 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 253 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
@@ -228,7 +259,7 @@
228 sdhci: sdhci@fe330000 { 259 sdhci: sdhci@fe330000 {
229 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1"; 260 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
230 reg = <0x0 0xfe330000 0x0 0x10000>; 261 reg = <0x0 0xfe330000 0x0 0x10000>;
231 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 262 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0>;
232 arasan,soc-ctl-syscon = <&grf>; 263 arasan,soc-ctl-syscon = <&grf>;
233 assigned-clocks = <&cru SCLK_EMMC>; 264 assigned-clocks = <&cru SCLK_EMMC>;
234 assigned-clock-rates = <200000000>; 265 assigned-clock-rates = <200000000>;
@@ -241,19 +272,60 @@
241 status = "disabled"; 272 status = "disabled";
242 }; 273 };
243 274
275 pcie0: pcie@f8000000 {
276 compatible = "rockchip,rk3399-pcie";
277 reg = <0x0 0xf8000000 0x0 0x2000000>,
278 <0x0 0xfd000000 0x0 0x1000000>;
279 reg-names = "axi-base", "apb-base";
280 #address-cells = <3>;
281 #size-cells = <2>;
282 #interrupt-cells = <1>;
283 bus-range = <0x0 0x1>;
284 clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
285 <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>;
286 clock-names = "aclk", "aclk-perf",
287 "hclk", "pm";
288 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>,
289 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>,
290 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 0>;
291 interrupt-names = "sys", "legacy", "client";
292 interrupt-map-mask = <0 0 0 7>;
293 interrupt-map = <0 0 0 1 &pcie0_intc 0>,
294 <0 0 0 2 &pcie0_intc 1>,
295 <0 0 0 3 &pcie0_intc 2>,
296 <0 0 0 4 &pcie0_intc 3>;
297 msi-map = <0x0 &its 0x0 0x1000>;
298 phys = <&pcie_phy>;
299 phy-names = "pcie-phy";
300 ranges = <0x83000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x600000
301 0x81000000 0x0 0xfa600000 0x0 0xfa600000 0x0 0x100000>;
302 resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,
303 <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>;
304 reset-names = "core", "mgmt", "mgmt-sticky", "pipe";
305 status = "disabled";
306
307 pcie0_intc: interrupt-controller {
308 interrupt-controller;
309 #address-cells = <0>;
310 #interrupt-cells = <1>;
311 };
312 };
313
244 usb_host0_ehci: usb@fe380000 { 314 usb_host0_ehci: usb@fe380000 {
245 compatible = "generic-ehci"; 315 compatible = "generic-ehci";
246 reg = <0x0 0xfe380000 0x0 0x20000>; 316 reg = <0x0 0xfe380000 0x0 0x20000>;
247 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 317 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH 0>;
248 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>; 318 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>;
249 clock-names = "hclk_host0", "hclk_host0_arb"; 319 clock-names = "hclk_host0", "hclk_host0_arb";
320 phys = <&u2phy0_host>;
321 phy-names = "usb";
250 status = "disabled"; 322 status = "disabled";
251 }; 323 };
252 324
253 usb_host0_ohci: usb@fe3a0000 { 325 usb_host0_ohci: usb@fe3a0000 {
254 compatible = "generic-ohci"; 326 compatible = "generic-ohci";
255 reg = <0x0 0xfe3a0000 0x0 0x20000>; 327 reg = <0x0 0xfe3a0000 0x0 0x20000>;
256 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 328 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>;
257 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>; 329 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>;
258 clock-names = "hclk_host0", "hclk_host0_arb"; 330 clock-names = "hclk_host0", "hclk_host0_arb";
259 status = "disabled"; 331 status = "disabled";
@@ -262,16 +334,18 @@
262 usb_host1_ehci: usb@fe3c0000 { 334 usb_host1_ehci: usb@fe3c0000 {
263 compatible = "generic-ehci"; 335 compatible = "generic-ehci";
264 reg = <0x0 0xfe3c0000 0x0 0x20000>; 336 reg = <0x0 0xfe3c0000 0x0 0x20000>;
265 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 337 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH 0>;
266 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>; 338 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>;
267 clock-names = "hclk_host1", "hclk_host1_arb"; 339 clock-names = "hclk_host1", "hclk_host1_arb";
340 phys = <&u2phy1_host>;
341 phy-names = "usb";
268 status = "disabled"; 342 status = "disabled";
269 }; 343 };
270 344
271 usb_host1_ohci: usb@fe3e0000 { 345 usb_host1_ohci: usb@fe3e0000 {
272 compatible = "generic-ohci"; 346 compatible = "generic-ohci";
273 reg = <0x0 0xfe3e0000 0x0 0x20000>; 347 reg = <0x0 0xfe3e0000 0x0 0x20000>;
274 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 348 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH 0>;
275 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>; 349 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>;
276 clock-names = "hclk_host1", "hclk_host1_arb"; 350 clock-names = "hclk_host1", "hclk_host1_arb";
277 status = "disabled"; 351 status = "disabled";
@@ -279,7 +353,7 @@
279 353
280 gic: interrupt-controller@fee00000 { 354 gic: interrupt-controller@fee00000 {
281 compatible = "arm,gic-v3"; 355 compatible = "arm,gic-v3";
282 #interrupt-cells = <3>; 356 #interrupt-cells = <4>;
283 #address-cells = <2>; 357 #address-cells = <2>;
284 #size-cells = <2>; 358 #size-cells = <2>;
285 ranges; 359 ranges;
@@ -290,12 +364,34 @@
290 <0x0 0xfff00000 0 0x10000>, /* GICC */ 364 <0x0 0xfff00000 0 0x10000>, /* GICC */
291 <0x0 0xfff10000 0 0x10000>, /* GICH */ 365 <0x0 0xfff10000 0 0x10000>, /* GICH */
292 <0x0 0xfff20000 0 0x10000>; /* GICV */ 366 <0x0 0xfff20000 0 0x10000>; /* GICV */
293 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 367 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
294 its: interrupt-controller@fee20000 { 368 its: interrupt-controller@fee20000 {
295 compatible = "arm,gic-v3-its"; 369 compatible = "arm,gic-v3-its";
296 msi-controller; 370 msi-controller;
297 reg = <0x0 0xfee20000 0x0 0x20000>; 371 reg = <0x0 0xfee20000 0x0 0x20000>;
298 }; 372 };
373
374 ppi-partitions {
375 ppi_cluster0: interrupt-partition-0 {
376 affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>;
377 };
378
379 ppi_cluster1: interrupt-partition-1 {
380 affinity = <&cpu_b0 &cpu_b1>;
381 };
382 };
383 };
384
385 saradc: saradc@ff100000 {
386 compatible = "rockchip,rk3399-saradc";
387 reg = <0x0 0xff100000 0x0 0x100>;
388 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH 0>;
389 #io-channel-cells = <1>;
390 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
391 clock-names = "saradc", "apb_pclk";
392 resets = <&cru SRST_P_SARADC>;
393 reset-names = "saradc-apb";
394 status = "disabled";
299 }; 395 };
300 396
301 i2c1: i2c@ff110000 { 397 i2c1: i2c@ff110000 {
@@ -305,7 +401,7 @@
305 assigned-clock-rates = <200000000>; 401 assigned-clock-rates = <200000000>;
306 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>; 402 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
307 clock-names = "i2c", "pclk"; 403 clock-names = "i2c", "pclk";
308 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 404 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH 0>;
309 pinctrl-names = "default"; 405 pinctrl-names = "default";
310 pinctrl-0 = <&i2c1_xfer>; 406 pinctrl-0 = <&i2c1_xfer>;
311 #address-cells = <1>; 407 #address-cells = <1>;
@@ -320,7 +416,7 @@
320 assigned-clock-rates = <200000000>; 416 assigned-clock-rates = <200000000>;
321 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>; 417 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
322 clock-names = "i2c", "pclk"; 418 clock-names = "i2c", "pclk";
323 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 419 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH 0>;
324 pinctrl-names = "default"; 420 pinctrl-names = "default";
325 pinctrl-0 = <&i2c2_xfer>; 421 pinctrl-0 = <&i2c2_xfer>;
326 #address-cells = <1>; 422 #address-cells = <1>;
@@ -335,7 +431,7 @@
335 assigned-clock-rates = <200000000>; 431 assigned-clock-rates = <200000000>;
336 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>; 432 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
337 clock-names = "i2c", "pclk"; 433 clock-names = "i2c", "pclk";
338 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 434 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH 0>;
339 pinctrl-names = "default"; 435 pinctrl-names = "default";
340 pinctrl-0 = <&i2c3_xfer>; 436 pinctrl-0 = <&i2c3_xfer>;
341 #address-cells = <1>; 437 #address-cells = <1>;
@@ -350,7 +446,7 @@
350 assigned-clock-rates = <200000000>; 446 assigned-clock-rates = <200000000>;
351 clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>; 447 clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>;
352 clock-names = "i2c", "pclk"; 448 clock-names = "i2c", "pclk";
353 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 449 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>;
354 pinctrl-names = "default"; 450 pinctrl-names = "default";
355 pinctrl-0 = <&i2c5_xfer>; 451 pinctrl-0 = <&i2c5_xfer>;
356 #address-cells = <1>; 452 #address-cells = <1>;
@@ -365,7 +461,7 @@
365 assigned-clock-rates = <200000000>; 461 assigned-clock-rates = <200000000>;
366 clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>; 462 clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>;
367 clock-names = "i2c", "pclk"; 463 clock-names = "i2c", "pclk";
368 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 464 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH 0>;
369 pinctrl-names = "default"; 465 pinctrl-names = "default";
370 pinctrl-0 = <&i2c6_xfer>; 466 pinctrl-0 = <&i2c6_xfer>;
371 #address-cells = <1>; 467 #address-cells = <1>;
@@ -380,7 +476,7 @@
380 assigned-clock-rates = <200000000>; 476 assigned-clock-rates = <200000000>;
381 clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>; 477 clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>;
382 clock-names = "i2c", "pclk"; 478 clock-names = "i2c", "pclk";
383 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 479 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH 0>;
384 pinctrl-names = "default"; 480 pinctrl-names = "default";
385 pinctrl-0 = <&i2c7_xfer>; 481 pinctrl-0 = <&i2c7_xfer>;
386 #address-cells = <1>; 482 #address-cells = <1>;
@@ -393,7 +489,7 @@
393 reg = <0x0 0xff180000 0x0 0x100>; 489 reg = <0x0 0xff180000 0x0 0x100>;
394 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 490 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
395 clock-names = "baudclk", "apb_pclk"; 491 clock-names = "baudclk", "apb_pclk";
396 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 492 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>;
397 reg-shift = <2>; 493 reg-shift = <2>;
398 reg-io-width = <4>; 494 reg-io-width = <4>;
399 pinctrl-names = "default"; 495 pinctrl-names = "default";
@@ -406,7 +502,7 @@
406 reg = <0x0 0xff190000 0x0 0x100>; 502 reg = <0x0 0xff190000 0x0 0x100>;
407 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 503 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
408 clock-names = "baudclk", "apb_pclk"; 504 clock-names = "baudclk", "apb_pclk";
409 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 505 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH 0>;
410 reg-shift = <2>; 506 reg-shift = <2>;
411 reg-io-width = <4>; 507 reg-io-width = <4>;
412 pinctrl-names = "default"; 508 pinctrl-names = "default";
@@ -419,7 +515,7 @@
419 reg = <0x0 0xff1a0000 0x0 0x100>; 515 reg = <0x0 0xff1a0000 0x0 0x100>;
420 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 516 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
421 clock-names = "baudclk", "apb_pclk"; 517 clock-names = "baudclk", "apb_pclk";
422 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 518 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>;
423 reg-shift = <2>; 519 reg-shift = <2>;
424 reg-io-width = <4>; 520 reg-io-width = <4>;
425 pinctrl-names = "default"; 521 pinctrl-names = "default";
@@ -432,7 +528,7 @@
432 reg = <0x0 0xff1b0000 0x0 0x100>; 528 reg = <0x0 0xff1b0000 0x0 0x100>;
433 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 529 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
434 clock-names = "baudclk", "apb_pclk"; 530 clock-names = "baudclk", "apb_pclk";
435 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 531 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>;
436 reg-shift = <2>; 532 reg-shift = <2>;
437 reg-io-width = <4>; 533 reg-io-width = <4>;
438 pinctrl-names = "default"; 534 pinctrl-names = "default";
@@ -445,7 +541,7 @@
445 reg = <0x0 0xff1c0000 0x0 0x1000>; 541 reg = <0x0 0xff1c0000 0x0 0x1000>;
446 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; 542 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
447 clock-names = "spiclk", "apb_pclk"; 543 clock-names = "spiclk", "apb_pclk";
448 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 544 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH 0>;
449 pinctrl-names = "default"; 545 pinctrl-names = "default";
450 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>; 546 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
451 #address-cells = <1>; 547 #address-cells = <1>;
@@ -458,7 +554,7 @@
458 reg = <0x0 0xff1d0000 0x0 0x1000>; 554 reg = <0x0 0xff1d0000 0x0 0x1000>;
459 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; 555 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
460 clock-names = "spiclk", "apb_pclk"; 556 clock-names = "spiclk", "apb_pclk";
461 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 557 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH 0>;
462 pinctrl-names = "default"; 558 pinctrl-names = "default";
463 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>; 559 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
464 #address-cells = <1>; 560 #address-cells = <1>;
@@ -471,7 +567,7 @@
471 reg = <0x0 0xff1e0000 0x0 0x1000>; 567 reg = <0x0 0xff1e0000 0x0 0x1000>;
472 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>; 568 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
473 clock-names = "spiclk", "apb_pclk"; 569 clock-names = "spiclk", "apb_pclk";
474 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 570 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH 0>;
475 pinctrl-names = "default"; 571 pinctrl-names = "default";
476 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>; 572 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
477 #address-cells = <1>; 573 #address-cells = <1>;
@@ -484,7 +580,7 @@
484 reg = <0x0 0xff1f0000 0x0 0x1000>; 580 reg = <0x0 0xff1f0000 0x0 0x1000>;
485 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>; 581 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
486 clock-names = "spiclk", "apb_pclk"; 582 clock-names = "spiclk", "apb_pclk";
487 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 583 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH 0>;
488 pinctrl-names = "default"; 584 pinctrl-names = "default";
489 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>; 585 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
490 #address-cells = <1>; 586 #address-cells = <1>;
@@ -497,7 +593,7 @@
497 reg = <0x0 0xff200000 0x0 0x1000>; 593 reg = <0x0 0xff200000 0x0 0x1000>;
498 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>; 594 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
499 clock-names = "spiclk", "apb_pclk"; 595 clock-names = "spiclk", "apb_pclk";
500 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>; 596 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH 0>;
501 pinctrl-names = "default"; 597 pinctrl-names = "default";
502 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>; 598 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
503 #address-cells = <1>; 599 #address-cells = <1>;
@@ -577,7 +673,7 @@
577 tsadc: tsadc@ff260000 { 673 tsadc: tsadc@ff260000 {
578 compatible = "rockchip,rk3399-tsadc"; 674 compatible = "rockchip,rk3399-tsadc";
579 reg = <0x0 0xff260000 0x0 0x100>; 675 reg = <0x0 0xff260000 0x0 0x100>;
580 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 676 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>;
581 assigned-clocks = <&cru SCLK_TSADC>; 677 assigned-clocks = <&cru SCLK_TSADC>;
582 assigned-clock-rates = <750000>; 678 assigned-clock-rates = <750000>;
583 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; 679 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
@@ -594,6 +690,203 @@
594 status = "disabled"; 690 status = "disabled";
595 }; 691 };
596 692
693 qos_gmac: qos@ffa5c000 {
694 compatible = "syscon";
695 reg = <0x0 0xffa5c000 0x0 0x20>;
696 };
697
698 qos_hdcp: qos@ffa90000 {
699 compatible = "syscon";
700 reg = <0x0 0xffa90000 0x0 0x20>;
701 };
702
703 qos_iep: qos@ffa98000 {
704 compatible = "syscon";
705 reg = <0x0 0xffa98000 0x0 0x20>;
706 };
707
708 qos_isp0_m0: qos@ffaa0000 {
709 compatible = "syscon";
710 reg = <0x0 0xffaa0000 0x0 0x20>;
711 };
712
713 qos_isp0_m1: qos@ffaa0080 {
714 compatible = "syscon";
715 reg = <0x0 0xffaa0080 0x0 0x20>;
716 };
717
718 qos_isp1_m0: qos@ffaa8000 {
719 compatible = "syscon";
720 reg = <0x0 0xffaa8000 0x0 0x20>;
721 };
722
723 qos_isp1_m1: qos@ffaa8080 {
724 compatible = "syscon";
725 reg = <0x0 0xffaa8080 0x0 0x20>;
726 };
727
728 qos_rga_r: qos@ffab0000 {
729 compatible = "syscon";
730 reg = <0x0 0xffab0000 0x0 0x20>;
731 };
732
733 qos_rga_w: qos@ffab0080 {
734 compatible = "syscon";
735 reg = <0x0 0xffab0080 0x0 0x20>;
736 };
737
738 qos_video_m0: qos@ffab8000 {
739 compatible = "syscon";
740 reg = <0x0 0xffab8000 0x0 0x20>;
741 };
742
743 qos_video_m1_r: qos@ffac0000 {
744 compatible = "syscon";
745 reg = <0x0 0xffac0000 0x0 0x20>;
746 };
747
748 qos_video_m1_w: qos@ffac0080 {
749 compatible = "syscon";
750 reg = <0x0 0xffac0080 0x0 0x20>;
751 };
752
753 qos_vop_big_r: qos@ffac8000 {
754 compatible = "syscon";
755 reg = <0x0 0xffac8000 0x0 0x20>;
756 };
757
758 qos_vop_big_w: qos@ffac8080 {
759 compatible = "syscon";
760 reg = <0x0 0xffac8080 0x0 0x20>;
761 };
762
763 qos_vop_little: qos@ffad0000 {
764 compatible = "syscon";
765 reg = <0x0 0xffad0000 0x0 0x20>;
766 };
767
768 qos_gpu: qos@ffae0000 {
769 compatible = "syscon";
770 reg = <0x0 0xffae0000 0x0 0x20>;
771 };
772
773 pmu: power-management@ff310000 {
774 compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd";
775 reg = <0x0 0xff310000 0x0 0x1000>;
776
777 /*
778 * Note: RK3399 supports 6 voltage domains including VD_CORE_L,
779 * VD_CORE_B, VD_CENTER, VD_GPU, VD_LOGIC and VD_PMU.
780 * Some of the power domains are grouped together for every
781 * voltage domain.
782 * The detail contents as below.
783 */
784 power: power-controller {
785 compatible = "rockchip,rk3399-power-controller";
786 #power-domain-cells = <1>;
787 #address-cells = <1>;
788 #size-cells = <0>;
789
790 /* These power domains are grouped by VD_CENTER */
791 pd_iep@RK3399_PD_IEP {
792 reg = <RK3399_PD_IEP>;
793 clocks = <&cru ACLK_IEP>,
794 <&cru HCLK_IEP>;
795 pm_qos = <&qos_iep>;
796 };
797 pd_rga@RK3399_PD_RGA {
798 reg = <RK3399_PD_RGA>;
799 clocks = <&cru ACLK_RGA>,
800 <&cru HCLK_RGA>;
801 pm_qos = <&qos_rga_r>,
802 <&qos_rga_w>;
803 };
804 pd_vcodec@RK3399_PD_VCODEC {
805 reg = <RK3399_PD_VCODEC>;
806 clocks = <&cru ACLK_VCODEC>,
807 <&cru HCLK_VCODEC>;
808 pm_qos = <&qos_video_m0>;
809 };
810 pd_vdu@RK3399_PD_VDU {
811 reg = <RK3399_PD_VDU>;
812 clocks = <&cru ACLK_VDU>,
813 <&cru HCLK_VDU>;
814 pm_qos = <&qos_video_m1_r>,
815 <&qos_video_m1_w>;
816 };
817
818 /* These power domains are grouped by VD_GPU */
819 pd_gpu@RK3399_PD_GPU {
820 reg = <RK3399_PD_GPU>;
821 clocks = <&cru ACLK_GPU>;
822 pm_qos = <&qos_gpu>;
823 };
824
825 /* These power domains are grouped by VD_LOGIC */
826 pd_gmac@RK3399_PD_GMAC {
827 reg = <RK3399_PD_GMAC>;
828 clocks = <&cru ACLK_GMAC>;
829 pm_qos = <&qos_gmac>;
830 };
831 pd_vio@RK3399_PD_VIO {
832 reg = <RK3399_PD_VIO>;
833 #address-cells = <1>;
834 #size-cells = <0>;
835
836 pd_hdcp@RK3399_PD_HDCP {
837 reg = <RK3399_PD_HDCP>;
838 clocks = <&cru ACLK_HDCP>,
839 <&cru HCLK_HDCP>,
840 <&cru PCLK_HDCP>;
841 pm_qos = <&qos_hdcp>;
842 };
843 pd_isp0@RK3399_PD_ISP0 {
844 reg = <RK3399_PD_ISP0>;
845 clocks = <&cru ACLK_ISP0>,
846 <&cru HCLK_ISP0>;
847 pm_qos = <&qos_isp0_m0>,
848 <&qos_isp0_m1>;
849 };
850 pd_isp1@RK3399_PD_ISP1 {
851 reg = <RK3399_PD_ISP1>;
852 clocks = <&cru ACLK_ISP1>,
853 <&cru HCLK_ISP1>;
854 pm_qos = <&qos_isp1_m0>,
855 <&qos_isp1_m1>;
856 };
857 pd_tcpc0@RK3399_PD_TCPC0 {
858 reg = <RK3399_PD_TCPD0>;
859 clocks = <&cru SCLK_UPHY0_TCPDCORE>,
860 <&cru SCLK_UPHY0_TCPDPHY_REF>;
861 };
862 pd_tcpc1@RK3399_PD_TCPC1 {
863 reg = <RK3399_PD_TCPD1>;
864 clocks = <&cru SCLK_UPHY1_TCPDCORE>,
865 <&cru SCLK_UPHY1_TCPDPHY_REF>;
866 };
867 pd_vo@RK3399_PD_VO {
868 reg = <RK3399_PD_VO>;
869 #address-cells = <1>;
870 #size-cells = <0>;
871
872 pd_vopb@RK3399_PD_VOPB {
873 reg = <RK3399_PD_VOPB>;
874 clocks = <&cru ACLK_VOP0>,
875 <&cru HCLK_VOP0>;
876 pm_qos = <&qos_vop_big_r>,
877 <&qos_vop_big_w>;
878 };
879 pd_vopl@RK3399_PD_VOPL {
880 reg = <RK3399_PD_VOPL>;
881 clocks = <&cru ACLK_VOP1>,
882 <&cru HCLK_VOP1>;
883 pm_qos = <&qos_vop_little>;
884 };
885 };
886 };
887 };
888 };
889
597 pmugrf: syscon@ff320000 { 890 pmugrf: syscon@ff320000 {
598 compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd"; 891 compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd";
599 reg = <0x0 0xff320000 0x0 0x1000>; 892 reg = <0x0 0xff320000 0x0 0x1000>;
@@ -611,7 +904,7 @@
611 reg = <0x0 0xff350000 0x0 0x1000>; 904 reg = <0x0 0xff350000 0x0 0x1000>;
612 clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>; 905 clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>;
613 clock-names = "spiclk", "apb_pclk"; 906 clock-names = "spiclk", "apb_pclk";
614 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 907 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH 0>;
615 pinctrl-names = "default"; 908 pinctrl-names = "default";
616 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>; 909 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
617 #address-cells = <1>; 910 #address-cells = <1>;
@@ -624,7 +917,7 @@
624 reg = <0x0 0xff370000 0x0 0x100>; 917 reg = <0x0 0xff370000 0x0 0x100>;
625 clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>; 918 clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>;
626 clock-names = "baudclk", "apb_pclk"; 919 clock-names = "baudclk", "apb_pclk";
627 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 920 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH 0>;
628 reg-shift = <2>; 921 reg-shift = <2>;
629 reg-io-width = <4>; 922 reg-io-width = <4>;
630 pinctrl-names = "default"; 923 pinctrl-names = "default";
@@ -639,7 +932,7 @@
639 assigned-clock-rates = <200000000>; 932 assigned-clock-rates = <200000000>;
640 clocks = <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>; 933 clocks = <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>;
641 clock-names = "i2c", "pclk"; 934 clock-names = "i2c", "pclk";
642 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 935 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH 0>;
643 pinctrl-names = "default"; 936 pinctrl-names = "default";
644 pinctrl-0 = <&i2c0_xfer>; 937 pinctrl-0 = <&i2c0_xfer>;
645 #address-cells = <1>; 938 #address-cells = <1>;
@@ -654,7 +947,7 @@
654 assigned-clock-rates = <200000000>; 947 assigned-clock-rates = <200000000>;
655 clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>; 948 clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>;
656 clock-names = "i2c", "pclk"; 949 clock-names = "i2c", "pclk";
657 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 950 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH 0>;
658 pinctrl-names = "default"; 951 pinctrl-names = "default";
659 pinctrl-0 = <&i2c4_xfer>; 952 pinctrl-0 = <&i2c4_xfer>;
660 #address-cells = <1>; 953 #address-cells = <1>;
@@ -669,7 +962,7 @@
669 assigned-clock-rates = <200000000>; 962 assigned-clock-rates = <200000000>;
670 clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>; 963 clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>;
671 clock-names = "i2c", "pclk"; 964 clock-names = "i2c", "pclk";
672 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 965 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>;
673 pinctrl-names = "default"; 966 pinctrl-names = "default";
674 pinctrl-0 = <&i2c8_xfer>; 967 pinctrl-0 = <&i2c8_xfer>;
675 #address-cells = <1>; 968 #address-cells = <1>;
@@ -721,6 +1014,35 @@
721 status = "disabled"; 1014 status = "disabled";
722 }; 1015 };
723 1016
1017 efuse0: efuse@ff690000 {
1018 compatible = "rockchip,rk3399-efuse";
1019 reg = <0x0 0xff690000 0x0 0x80>;
1020 #address-cells = <1>;
1021 #size-cells = <1>;
1022 clocks = <&cru PCLK_EFUSE1024NS>;
1023 clock-names = "pclk_efuse";
1024
1025 /* Data cells */
1026 cpub_leakage: cpu-leakage@17 {
1027 reg = <0x17 0x1>;
1028 };
1029 gpu_leakage: gpu-leakage@18 {
1030 reg = <0x18 0x1>;
1031 };
1032 center_leakage: center-leakage@19 {
1033 reg = <0x19 0x1>;
1034 };
1035 cpul_leakage: cpu-leakage@1a {
1036 reg = <0x1a 0x1>;
1037 };
1038 logic_leakage: logic-leakage@1b {
1039 reg = <0x1b 0x1>;
1040 };
1041 wafer_info: wafer-info@1c {
1042 reg = <0x1c 0x1>;
1043 };
1044 };
1045
724 pmucru: pmu-clock-controller@ff750000 { 1046 pmucru: pmu-clock-controller@ff750000 {
725 compatible = "rockchip,rk3399-pmucru"; 1047 compatible = "rockchip,rk3399-pmucru";
726 reg = <0x0 0xff750000 0x0 0x1000>; 1048 reg = <0x0 0xff750000 0x0 0x1000>;
@@ -741,7 +1063,7 @@
741 <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>, 1063 <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
742 <&cru PCLK_PERIHP>, 1064 <&cru PCLK_PERIHP>,
743 <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>, 1065 <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
744 <&cru PCLK_PERILP0>, 1066 <&cru PCLK_PERILP0>, <&cru ACLK_CCI>,
745 <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>; 1067 <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>;
746 assigned-clock-rates = 1068 assigned-clock-rates =
747 <594000000>, <800000000>, 1069 <594000000>, <800000000>,
@@ -749,7 +1071,7 @@
749 <150000000>, <75000000>, 1071 <150000000>, <75000000>,
750 <37500000>, 1072 <37500000>,
751 <100000000>, <100000000>, 1073 <100000000>, <100000000>,
752 <50000000>, 1074 <50000000>, <600000000>,
753 <100000000>, <50000000>; 1075 <100000000>, <50000000>;
754 }; 1076 };
755 1077
@@ -764,6 +1086,40 @@
764 status = "disabled"; 1086 status = "disabled";
765 }; 1087 };
766 1088
1089 u2phy0: usb2-phy@e450 {
1090 compatible = "rockchip,rk3399-usb2phy";
1091 reg = <0xe450 0x10>;
1092 clocks = <&cru SCLK_USB2PHY0_REF>;
1093 clock-names = "phyclk";
1094 #clock-cells = <0>;
1095 clock-output-names = "clk_usbphy0_480m";
1096 status = "disabled";
1097
1098 u2phy0_host: host-port {
1099 #phy-cells = <0>;
1100 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>;
1101 interrupt-names = "linestate";
1102 status = "disabled";
1103 };
1104 };
1105
1106 u2phy1: usb2-phy@e460 {
1107 compatible = "rockchip,rk3399-usb2phy";
1108 reg = <0xe460 0x10>;
1109 clocks = <&cru SCLK_USB2PHY1_REF>;
1110 clock-names = "phyclk";
1111 #clock-cells = <0>;
1112 clock-output-names = "clk_usbphy1_480m";
1113 status = "disabled";
1114
1115 u2phy1_host: host-port {
1116 #phy-cells = <0>;
1117 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>;
1118 interrupt-names = "linestate";
1119 status = "disabled";
1120 };
1121 };
1122
767 emmc_phy: phy@f780 { 1123 emmc_phy: phy@f780 {
768 compatible = "rockchip,rk3399-emmc-phy"; 1124 compatible = "rockchip,rk3399-emmc-phy";
769 reg = <0xf780 0x24>; 1125 reg = <0xf780 0x24>;
@@ -772,19 +1128,85 @@
772 #phy-cells = <0>; 1128 #phy-cells = <0>;
773 status = "disabled"; 1129 status = "disabled";
774 }; 1130 };
1131
1132 pcie_phy: pcie-phy {
1133 compatible = "rockchip,rk3399-pcie-phy";
1134 clocks = <&cru SCLK_PCIEPHY_REF>;
1135 clock-names = "refclk";
1136 #phy-cells = <0>;
1137 resets = <&cru SRST_PCIEPHY>;
1138 reset-names = "phy";
1139 status = "disabled";
1140 };
775 }; 1141 };
776 1142
777 watchdog@ff840000 { 1143 tcphy0: phy@ff7c0000 {
1144 compatible = "rockchip,rk3399-typec-phy";
1145 reg = <0x0 0xff7c0000 0x0 0x40000>;
1146 clocks = <&cru SCLK_UPHY0_TCPDCORE>,
1147 <&cru SCLK_UPHY0_TCPDPHY_REF>;
1148 clock-names = "tcpdcore", "tcpdphy-ref";
1149 assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>;
1150 assigned-clock-rates = <50000000>;
1151 resets = <&cru SRST_UPHY0>,
1152 <&cru SRST_UPHY0_PIPE_L00>,
1153 <&cru SRST_P_UPHY0_TCPHY>;
1154 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
1155 rockchip,grf = <&grf>;
1156 rockchip,typec-conn-dir = <0xe580 0 16>;
1157 rockchip,usb3tousb2-en = <0xe580 3 19>;
1158 rockchip,external-psm = <0xe588 14 30>;
1159 rockchip,pipe-status = <0xe5c0 0 0>;
1160 status = "disabled";
1161
1162 tcphy0_dp: dp-port {
1163 #phy-cells = <0>;
1164 };
1165
1166 tcphy0_usb3: usb3-port {
1167 #phy-cells = <0>;
1168 };
1169 };
1170
1171 tcphy1: phy@ff800000 {
1172 compatible = "rockchip,rk3399-typec-phy";
1173 reg = <0x0 0xff800000 0x0 0x40000>;
1174 clocks = <&cru SCLK_UPHY1_TCPDCORE>,
1175 <&cru SCLK_UPHY1_TCPDPHY_REF>;
1176 clock-names = "tcpdcore", "tcpdphy-ref";
1177 assigned-clocks = <&cru SCLK_UPHY1_TCPDCORE>;
1178 assigned-clock-rates = <50000000>;
1179 resets = <&cru SRST_UPHY1>,
1180 <&cru SRST_UPHY1_PIPE_L00>,
1181 <&cru SRST_P_UPHY1_TCPHY>;
1182 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
1183 rockchip,grf = <&grf>;
1184 rockchip,typec-conn-dir = <0xe58c 0 16>;
1185 rockchip,usb3tousb2-en = <0xe58c 3 19>;
1186 rockchip,external-psm = <0xe594 14 30>;
1187 rockchip,pipe-status = <0xe5c0 16 16>;
1188 status = "disabled";
1189
1190 tcphy1_dp: dp-port {
1191 #phy-cells = <0>;
1192 };
1193
1194 tcphy1_usb3: usb3-port {
1195 #phy-cells = <0>;
1196 };
1197 };
1198
1199 watchdog@ff848000 {
778 compatible = "snps,dw-wdt"; 1200 compatible = "snps,dw-wdt";
779 reg = <0x0 0xff840000 0x0 0x100>; 1201 reg = <0x0 0xff848000 0x0 0x100>;
780 clocks = <&cru PCLK_WDT>; 1202 clocks = <&cru PCLK_WDT>;
781 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 1203 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>;
782 }; 1204 };
783 1205
784 rktimer: rktimer@ff850000 { 1206 rktimer: rktimer@ff850000 {
785 compatible = "rockchip,rk3399-timer"; 1207 compatible = "rockchip,rk3399-timer";
786 reg = <0x0 0xff850000 0x0 0x1000>; 1208 reg = <0x0 0xff850000 0x0 0x1000>;
787 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 1209 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH 0>;
788 clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>; 1210 clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>;
789 clock-names = "pclk", "timer"; 1211 clock-names = "pclk", "timer";
790 }; 1212 };
@@ -792,7 +1214,7 @@
792 spdif: spdif@ff870000 { 1214 spdif: spdif@ff870000 {
793 compatible = "rockchip,rk3399-spdif"; 1215 compatible = "rockchip,rk3399-spdif";
794 reg = <0x0 0xff870000 0x0 0x1000>; 1216 reg = <0x0 0xff870000 0x0 0x1000>;
795 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 1217 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH 0>;
796 dmas = <&dmac_bus 7>; 1218 dmas = <&dmac_bus 7>;
797 dma-names = "tx"; 1219 dma-names = "tx";
798 clock-names = "mclk", "hclk"; 1220 clock-names = "mclk", "hclk";
@@ -806,7 +1228,7 @@
806 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s"; 1228 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
807 reg = <0x0 0xff880000 0x0 0x1000>; 1229 reg = <0x0 0xff880000 0x0 0x1000>;
808 rockchip,grf = <&grf>; 1230 rockchip,grf = <&grf>;
809 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 1231 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH 0>;
810 dmas = <&dmac_bus 0>, <&dmac_bus 1>; 1232 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
811 dma-names = "tx", "rx"; 1233 dma-names = "tx", "rx";
812 clock-names = "i2s_clk", "i2s_hclk"; 1234 clock-names = "i2s_clk", "i2s_hclk";
@@ -819,7 +1241,7 @@
819 i2s1: i2s@ff890000 { 1241 i2s1: i2s@ff890000 {
820 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s"; 1242 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
821 reg = <0x0 0xff890000 0x0 0x1000>; 1243 reg = <0x0 0xff890000 0x0 0x1000>;
822 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 1244 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH 0>;
823 dmas = <&dmac_bus 2>, <&dmac_bus 3>; 1245 dmas = <&dmac_bus 2>, <&dmac_bus 3>;
824 dma-names = "tx", "rx"; 1246 dma-names = "tx", "rx";
825 clock-names = "i2s_clk", "i2s_hclk"; 1247 clock-names = "i2s_clk", "i2s_hclk";
@@ -832,7 +1254,7 @@
832 i2s2: i2s@ff8a0000 { 1254 i2s2: i2s@ff8a0000 {
833 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s"; 1255 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
834 reg = <0x0 0xff8a0000 0x0 0x1000>; 1256 reg = <0x0 0xff8a0000 0x0 0x1000>;
835 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 1257 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH 0>;
836 dmas = <&dmac_bus 4>, <&dmac_bus 5>; 1258 dmas = <&dmac_bus 4>, <&dmac_bus 5>;
837 dma-names = "tx", "rx"; 1259 dma-names = "tx", "rx";
838 clock-names = "i2s_clk", "i2s_hclk"; 1260 clock-names = "i2s_clk", "i2s_hclk";
@@ -852,7 +1274,7 @@
852 compatible = "rockchip,gpio-bank"; 1274 compatible = "rockchip,gpio-bank";
853 reg = <0x0 0xff720000 0x0 0x100>; 1275 reg = <0x0 0xff720000 0x0 0x100>;
854 clocks = <&pmucru PCLK_GPIO0_PMU>; 1276 clocks = <&pmucru PCLK_GPIO0_PMU>;
855 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1277 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH 0>;
856 1278
857 gpio-controller; 1279 gpio-controller;
858 #gpio-cells = <0x2>; 1280 #gpio-cells = <0x2>;
@@ -865,7 +1287,7 @@
865 compatible = "rockchip,gpio-bank"; 1287 compatible = "rockchip,gpio-bank";
866 reg = <0x0 0xff730000 0x0 0x100>; 1288 reg = <0x0 0xff730000 0x0 0x100>;
867 clocks = <&pmucru PCLK_GPIO1_PMU>; 1289 clocks = <&pmucru PCLK_GPIO1_PMU>;
868 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 1290 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH 0>;
869 1291
870 gpio-controller; 1292 gpio-controller;
871 #gpio-cells = <0x2>; 1293 #gpio-cells = <0x2>;
@@ -878,7 +1300,7 @@
878 compatible = "rockchip,gpio-bank"; 1300 compatible = "rockchip,gpio-bank";
879 reg = <0x0 0xff780000 0x0 0x100>; 1301 reg = <0x0 0xff780000 0x0 0x100>;
880 clocks = <&cru PCLK_GPIO2>; 1302 clocks = <&cru PCLK_GPIO2>;
881 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 1303 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH 0>;
882 1304
883 gpio-controller; 1305 gpio-controller;
884 #gpio-cells = <0x2>; 1306 #gpio-cells = <0x2>;
@@ -891,7 +1313,7 @@
891 compatible = "rockchip,gpio-bank"; 1313 compatible = "rockchip,gpio-bank";
892 reg = <0x0 0xff788000 0x0 0x100>; 1314 reg = <0x0 0xff788000 0x0 0x100>;
893 clocks = <&cru PCLK_GPIO3>; 1315 clocks = <&cru PCLK_GPIO3>;
894 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 1316 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>;
895 1317
896 gpio-controller; 1318 gpio-controller;
897 #gpio-cells = <0x2>; 1319 #gpio-cells = <0x2>;
@@ -904,7 +1326,7 @@
904 compatible = "rockchip,gpio-bank"; 1326 compatible = "rockchip,gpio-bank";
905 reg = <0x0 0xff790000 0x0 0x100>; 1327 reg = <0x0 0xff790000 0x0 0x100>;
906 clocks = <&cru PCLK_GPIO4>; 1328 clocks = <&cru PCLK_GPIO4>;
907 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 1329 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>;
908 1330
909 gpio-controller; 1331 gpio-controller;
910 #gpio-cells = <0x2>; 1332 #gpio-cells = <0x2>;
@@ -955,6 +1377,72 @@
955 drive-strength = <13>; 1377 drive-strength = <13>;
956 }; 1378 };
957 1379
1380 clock {
1381 clk_32k: clk-32k {
1382 rockchip,pins = <0 0 RK_FUNC_2 &pcfg_pull_none>;
1383 };
1384 };
1385
1386 gmac {
1387 rgmii_pins: rgmii-pins {
1388 rockchip,pins =
1389 /* mac_txclk */
1390 <3 17 RK_FUNC_1 &pcfg_pull_none_13ma>,
1391 /* mac_rxclk */
1392 <3 14 RK_FUNC_1 &pcfg_pull_none>,
1393 /* mac_mdio */
1394 <3 13 RK_FUNC_1 &pcfg_pull_none>,
1395 /* mac_txen */
1396 <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
1397 /* mac_clk */
1398 <3 11 RK_FUNC_1 &pcfg_pull_none>,
1399 /* mac_rxdv */
1400 <3 9 RK_FUNC_1 &pcfg_pull_none>,
1401 /* mac_mdc */
1402 <3 8 RK_FUNC_1 &pcfg_pull_none>,
1403 /* mac_rxd1 */
1404 <3 7 RK_FUNC_1 &pcfg_pull_none>,
1405 /* mac_rxd0 */
1406 <3 6 RK_FUNC_1 &pcfg_pull_none>,
1407 /* mac_txd1 */
1408 <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
1409 /* mac_txd0 */
1410 <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>,
1411 /* mac_rxd3 */
1412 <3 3 RK_FUNC_1 &pcfg_pull_none>,
1413 /* mac_rxd2 */
1414 <3 2 RK_FUNC_1 &pcfg_pull_none>,
1415 /* mac_txd3 */
1416 <3 1 RK_FUNC_1 &pcfg_pull_none_13ma>,
1417 /* mac_txd2 */
1418 <3 0 RK_FUNC_1 &pcfg_pull_none_13ma>;
1419 };
1420
1421 rmii_pins: rmii-pins {
1422 rockchip,pins =
1423 /* mac_mdio */
1424 <3 13 RK_FUNC_1 &pcfg_pull_none>,
1425 /* mac_txen */
1426 <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
1427 /* mac_clk */
1428 <3 11 RK_FUNC_1 &pcfg_pull_none>,
1429 /* mac_rxer */
1430 <3 10 RK_FUNC_1 &pcfg_pull_none>,
1431 /* mac_rxdv */
1432 <3 9 RK_FUNC_1 &pcfg_pull_none>,
1433 /* mac_mdc */
1434 <3 8 RK_FUNC_1 &pcfg_pull_none>,
1435 /* mac_rxd1 */
1436 <3 7 RK_FUNC_1 &pcfg_pull_none>,
1437 /* mac_rxd0 */
1438 <3 6 RK_FUNC_1 &pcfg_pull_none>,
1439 /* mac_txd1 */
1440 <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
1441 /* mac_txd0 */
1442 <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>;
1443 };
1444 };
1445
958 i2c0 { 1446 i2c0 {
959 i2c0_xfer: i2c0-xfer { 1447 i2c0_xfer: i2c0-xfer {
960 rockchip,pins = 1448 rockchip,pins =
@@ -1326,5 +1814,18 @@
1326 <1 14 RK_FUNC_1 &pcfg_pull_none>; 1814 <1 14 RK_FUNC_1 &pcfg_pull_none>;
1327 }; 1815 };
1328 }; 1816 };
1817
1818 pcie {
1819 pcie_clkreqn: pci-clkreqn {
1820 rockchip,pins =
1821 <2 26 RK_FUNC_2 &pcfg_pull_none>;
1822 };
1823
1824 pcie_clkreqnb: pci-clkreqnb {
1825 rockchip,pins =
1826 <4 24 RK_FUNC_1 &pcfg_pull_none>;
1827 };
1828 };
1829
1329 }; 1830 };
1330}; 1831};
diff --git a/include/dt-bindings/soc/rockchip,boot-mode.h b/include/dt-bindings/soc/rockchip,boot-mode.h
new file mode 100644
index 000000000000..ae7c867e736a
--- /dev/null
+++ b/include/dt-bindings/soc/rockchip,boot-mode.h
@@ -0,0 +1,15 @@
1#ifndef __ROCKCHIP_BOOT_MODE_H
2#define __ROCKCHIP_BOOT_MODE_H
3
4/*high 24 bits is tag, low 8 bits is type*/
5#define REBOOT_FLAG 0x5242C300
6/* normal boot */
7#define BOOT_NORMAL (REBOOT_FLAG + 0)
8/* enter bootloader rockusb mode */
9#define BOOT_BL_DOWNLOAD (REBOOT_FLAG + 1)
10/* enter recovery */
11#define BOOT_RECOVERY (REBOOT_FLAG + 3)
12 /* enter fastboot mode */
13#define BOOT_FASTBOOT (REBOOT_FLAG + 9)
14
15#endif
generated by cgit v1.2.2 (git 2.25.0) at 2025-09-06 00:56:52 -0400