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authorArd Biesheuvel <ard.biesheuvel@linaro.org>2017-07-12 10:44:14 -0400
committerWill Deacon <will.deacon@arm.com>2017-07-25 05:04:42 -0400
commit288be97cc74e31b7871c75eb11a8dd768dcb535d (patch)
treec2e64b697b8e1196a8b3e15b625e072de1d21636
parentece4b206be9934b3bb32adb1261545ead831c993 (diff)
arm64/lib: copy_page: use consistent prefetch stride
The optional prefetch instructions in the copy_page() routine are inconsistent: at the start of the function, two cachelines are prefetched beyond the one being loaded in the first iteration, but in the loop, the prefetch is one more line ahead. This appears to be unintentional, so let's fix it. While at it, fix the comment style and white space. Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Will Deacon <will.deacon@arm.com>
-rw-r--r--arch/arm64/lib/copy_page.S9
1 files changed, 5 insertions, 4 deletions
diff --git a/arch/arm64/lib/copy_page.S b/arch/arm64/lib/copy_page.S
index c3cd65e31814..076c43715e64 100644
--- a/arch/arm64/lib/copy_page.S
+++ b/arch/arm64/lib/copy_page.S
@@ -30,9 +30,10 @@
30 */ 30 */
31ENTRY(copy_page) 31ENTRY(copy_page)
32alternative_if ARM64_HAS_NO_HW_PREFETCH 32alternative_if ARM64_HAS_NO_HW_PREFETCH
33 # Prefetch two cache lines ahead. 33 // Prefetch three cache lines ahead.
34 prfm pldl1strm, [x1, #128] 34 prfm pldl1strm, [x1, #128]
35 prfm pldl1strm, [x1, #256] 35 prfm pldl1strm, [x1, #256]
36 prfm pldl1strm, [x1, #384]
36alternative_else_nop_endif 37alternative_else_nop_endif
37 38
38 ldp x2, x3, [x1] 39 ldp x2, x3, [x1]
@@ -50,7 +51,7 @@ alternative_else_nop_endif
50 subs x18, x18, #128 51 subs x18, x18, #128
51 52
52alternative_if ARM64_HAS_NO_HW_PREFETCH 53alternative_if ARM64_HAS_NO_HW_PREFETCH
53 prfm pldl1strm, [x1, #384] 54 prfm pldl1strm, [x1, #384]
54alternative_else_nop_endif 55alternative_else_nop_endif
55 56
56 stnp x2, x3, [x0] 57 stnp x2, x3, [x0]