aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorIdo Schimmel <idosch@mellanox.com>2018-10-11 03:48:08 -0400
committerDavid S. Miller <davem@davemloft.net>2018-10-11 13:08:23 -0400
commit27f68c0850aa4565b3f126441fdc0fb3f1f2f8db (patch)
treea13c333bdb06afdb966d32b4c34ca2e8d66b0275
parent0933781f11e71350e60ba4466fab5cae6fab4293 (diff)
mlxsw: reg: Add Monitoring Parsing State Register
This register is used for setting up the parsing for hash, policy-engine and routing. Signed-off-by: Ido Schimmel <idosch@mellanox.com> Reviewed-by: Petr Machata <petrm@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
-rw-r--r--drivers/net/ethernet/mellanox/mlxsw/reg.h44
1 files changed, 44 insertions, 0 deletions
diff --git a/drivers/net/ethernet/mellanox/mlxsw/reg.h b/drivers/net/ethernet/mellanox/mlxsw/reg.h
index 068af0ea7574..32cb6718bb17 100644
--- a/drivers/net/ethernet/mellanox/mlxsw/reg.h
+++ b/drivers/net/ethernet/mellanox/mlxsw/reg.h
@@ -8348,6 +8348,49 @@ static inline void mlxsw_reg_mgpc_pack(char *payload, u32 counter_index,
8348 mlxsw_reg_mgpc_opcode_set(payload, opcode); 8348 mlxsw_reg_mgpc_opcode_set(payload, opcode);
8349} 8349}
8350 8350
8351/* MPRS - Monitoring Parsing State Register
8352 * ----------------------------------------
8353 * The MPRS register is used for setting up the parsing for hash,
8354 * policy-engine and routing.
8355 */
8356#define MLXSW_REG_MPRS_ID 0x9083
8357#define MLXSW_REG_MPRS_LEN 0x14
8358
8359MLXSW_REG_DEFINE(mprs, MLXSW_REG_MPRS_ID, MLXSW_REG_MPRS_LEN);
8360
8361/* reg_mprs_parsing_depth
8362 * Minimum parsing depth.
8363 * Need to enlarge parsing depth according to L3, MPLS, tunnels, ACL
8364 * rules, traps, hash, etc. Default is 96 bytes. Reserved when SwitchX-2.
8365 * Access: RW
8366 */
8367MLXSW_ITEM32(reg, mprs, parsing_depth, 0x00, 0, 16);
8368
8369/* reg_mprs_parsing_en
8370 * Parsing enable.
8371 * Bit 0 - Enable parsing of NVE of types VxLAN, VxLAN-GPE, GENEVE and
8372 * NVGRE. Default is enabled. Reserved when SwitchX-2.
8373 * Access: RW
8374 */
8375MLXSW_ITEM32(reg, mprs, parsing_en, 0x04, 0, 16);
8376
8377/* reg_mprs_vxlan_udp_dport
8378 * VxLAN UDP destination port.
8379 * Used for identifying VxLAN packets and for dport field in
8380 * encapsulation. Default is 4789.
8381 * Access: RW
8382 */
8383MLXSW_ITEM32(reg, mprs, vxlan_udp_dport, 0x10, 0, 16);
8384
8385static inline void mlxsw_reg_mprs_pack(char *payload, u16 parsing_depth,
8386 u16 vxlan_udp_dport)
8387{
8388 MLXSW_REG_ZERO(mprs, payload);
8389 mlxsw_reg_mprs_parsing_depth_set(payload, parsing_depth);
8390 mlxsw_reg_mprs_parsing_en_set(payload, true);
8391 mlxsw_reg_mprs_vxlan_udp_dport_set(payload, vxlan_udp_dport);
8392}
8393
8351/* TNGCR - Tunneling NVE General Configuration Register 8394/* TNGCR - Tunneling NVE General Configuration Register
8352 * ---------------------------------------------------- 8395 * ----------------------------------------------------
8353 * The TNGCR register is used for setting up the NVE Tunneling configuration. 8396 * The TNGCR register is used for setting up the NVE Tunneling configuration.
@@ -9356,6 +9399,7 @@ static const struct mlxsw_reg_info *mlxsw_reg_infos[] = {
9356 MLXSW_REG(mcc), 9399 MLXSW_REG(mcc),
9357 MLXSW_REG(mcda), 9400 MLXSW_REG(mcda),
9358 MLXSW_REG(mgpc), 9401 MLXSW_REG(mgpc),
9402 MLXSW_REG(mprs),
9359 MLXSW_REG(tngcr), 9403 MLXSW_REG(tngcr),
9360 MLXSW_REG(tnumt), 9404 MLXSW_REG(tnumt),
9361 MLXSW_REG(tnqcr), 9405 MLXSW_REG(tnqcr),