arm64: renesas: r8a7795: Add Renesas R8A7795 SoC support

Initial version of Renesas R-Car H3 support (V10)

Signed-off-by: Gaku Inami <gaku.inami.xw@bp.renesas.com>
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Magnus Damm <damm+renesas@opensource.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>

5 files changed, 105 insertions, 0 deletions

diff --git a/Documentation/devicetree/bindings/arm/shmobile.txt b/Documentation/devicetree/bindings/arm/shmobile.txt
index 40bb9007cd0d..6712ebbe5f49 100644
--- a/Documentation/devicetree/bindings/arm/shmobile.txt
+++ b/Documentation/devicetree/bindings/arm/shmobile.txt
@@ -27,6 +27,8 @@ SoCs:
     compatible = "renesas,r8a7793"
   - R-Car E2 (R8A77940)
     compatible = "renesas,r8a7794"
+  - R-Car H3 (R8A77950)
+    compatible = "renesas,r8a7795"
 
 
 Boards:
diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
index 4043c35962cc..8446f27b18df 100644
--- a/arch/arm64/Kconfig.platforms
+++ b/arch/arm64/Kconfig.platforms
@@ -67,6 +67,23 @@ config ARCH_SEATTLE
         help
           This enables support for AMD Seattle SOC Family
 
+config ARCH_SHMOBILE
+        bool
+
+config ARCH_RENESAS
+        bool "Renesas SoC Platforms"
+        select ARCH_SHMOBILE
+        select PINCTRL
+        select PM_GENERIC_DOMAINS if PM
+        help
+          This enables support for the ARMv8 based Renesas SoCs.
+
+config ARCH_R8A7795
+        bool "Renesas R-Car H3 SoC Platform"
+        depends on ARCH_RENESAS
+        help
+          This enables support for the Renesas R-Car H3 SoC.
+
 config ARCH_STRATIX10
         bool "Altera's Stratix 10 SoCFPGA Family"
         help
diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
index eb3c42d97175..0e775e4d6a00 100644
--- a/arch/arm64/boot/dts/Makefile
+++ b/arch/arm64/boot/dts/Makefile
@@ -10,6 +10,7 @@ dts-dirs += hisilicon
 dts-dirs += marvell
 dts-dirs += mediatek
 dts-dirs += qcom
+dts-dirs += renesas
 dts-dirs += rockchip
 dts-dirs += sprd
 dts-dirs += xilinx
diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile
new file mode 100644
index 000000000000..fec69f46d65b
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/Makefile
@@ -0,0 +1,2 @@
+always          := $(dtb-y)
+clean-files     := *.dtb
diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
new file mode 100644
index 000000000000..8d7552020daf
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
@@ -0,0 +1,83 @@
+/*
+ * Device Tree Source for the r8a7795 SoC
+ *
+ * Copyright (C) 2015 Renesas Electronics Corp.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2.  This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+        compatible = "renesas,r8a7795";
+        #address-cells = <2>;
+        #size-cells = <2>;
+
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                /* 1 core only at this point */
+                a57_0: cpu@0 {
+                        compatible = "arm,cortex-a57", "arm,armv8";
+                        reg = <0x0>;
+                        device_type = "cpu";
+                };
+        };
+
+        extal_clk: extal {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                /* This value must be overridden by the board */
+                clock-frequency = <0>;
+        };
+
+        extalr_clk: extalr {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                /* This value must be overridden by the board */
+                clock-frequency = <0>;
+        };
+
+        soc {
+                compatible = "simple-bus";
+                interrupt-parent = <&gic>;
+                #address-cells = <2>;
+                #size-cells = <2>;
+                ranges;
+
+                gic: interrupt-controller@0xf1010000 {
+                        compatible = "arm,gic-400";
+                        #interrupt-cells = <3>;
+                        #address-cells = <0>;
+                        interrupt-controller;
+                        reg = <0x0 0xf1010000 0 0x1000>,
+                              <0x0 0xf1020000 0 0x2000>;
+                        interrupts = <GIC_PPI 9
+                                        (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
+                };
+
+                timer {
+                        compatible = "arm,armv8-timer";
+                        interrupts = <GIC_PPI 13
+                                        (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
+                                     <GIC_PPI 14
+                                        (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
+                                     <GIC_PPI 11
+                                        (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
+                                     <GIC_PPI 10
+                                        (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
+                };
+
+                cpg: clock-controller@e6150000 {
+                        compatible = "renesas,r8a7795-cpg-mssr";
+                        reg = <0 0xe6150000 0 0x1000>;
+                        clocks = <&extal_clk>, <&extalr_clk>;
+                        clock-names = "extal", "extalr";
+                        #clock-cells = <2>;
+                        #power-domain-cells = <0>;
+                };
+        };
+};