diff options
author | Rob Rice <rob.rice@broadcom.com> | 2017-02-03 12:55:34 -0500 |
---|---|---|
committer | Florian Fainelli <f.fainelli@gmail.com> | 2017-03-05 19:57:06 -0500 |
commit | 264f5f2673d6c60de7233b8437b56717475a48f3 (patch) | |
tree | 367b72f7b8ace4ad434f0ac62f4c775e0b97acfa | |
parent | c1ae3cfa0e89fa1a7ecc4c99031f5e9ae99d9201 (diff) |
arm64: dts: NS2: Add Broadcom SPU driver DT entry
Add Northstar2 device tree entry for Broadcom Secure Processing Unit
(SPU) crypto hardware.
Signed-off-by: Steve Lin <steven.lin1@broadcom.com>
Signed-off-by: Rob Rice <rob.rice@broadcom.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
-rw-r--r-- | arch/arm64/boot/dts/broadcom/ns2.dtsi | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/broadcom/ns2.dtsi b/arch/arm64/boot/dts/broadcom/ns2.dtsi index 9f9e203c09c5..b8503fc1bb54 100644 --- a/arch/arm64/boot/dts/broadcom/ns2.dtsi +++ b/arch/arm64/boot/dts/broadcom/ns2.dtsi | |||
@@ -217,6 +217,12 @@ | |||
217 | brcm,use-bcm-hdr; | 217 | brcm,use-bcm-hdr; |
218 | }; | 218 | }; |
219 | 219 | ||
220 | crypto0: crypto@612d0000 { | ||
221 | compatible = "brcm,spum-crypto"; | ||
222 | reg = <0x612d0000 0x900>; | ||
223 | mboxes = <&pdc0 0>; | ||
224 | }; | ||
225 | |||
220 | pdc1: iproc-pdc1@612e0000 { | 226 | pdc1: iproc-pdc1@612e0000 { |
221 | compatible = "brcm,iproc-pdc-mbox"; | 227 | compatible = "brcm,iproc-pdc-mbox"; |
222 | reg = <0x612e0000 0x445>; /* PDC FS1 regs */ | 228 | reg = <0x612e0000 0x445>; /* PDC FS1 regs */ |
@@ -226,6 +232,12 @@ | |||
226 | brcm,use-bcm-hdr; | 232 | brcm,use-bcm-hdr; |
227 | }; | 233 | }; |
228 | 234 | ||
235 | crypto1: crypto@612f0000 { | ||
236 | compatible = "brcm,spum-crypto"; | ||
237 | reg = <0x612f0000 0x900>; | ||
238 | mboxes = <&pdc1 0>; | ||
239 | }; | ||
240 | |||
229 | pdc2: iproc-pdc2@61300000 { | 241 | pdc2: iproc-pdc2@61300000 { |
230 | compatible = "brcm,iproc-pdc-mbox"; | 242 | compatible = "brcm,iproc-pdc-mbox"; |
231 | reg = <0x61300000 0x445>; /* PDC FS2 regs */ | 243 | reg = <0x61300000 0x445>; /* PDC FS2 regs */ |
@@ -235,6 +247,12 @@ | |||
235 | brcm,use-bcm-hdr; | 247 | brcm,use-bcm-hdr; |
236 | }; | 248 | }; |
237 | 249 | ||
250 | crypto2: crypto@61310000 { | ||
251 | compatible = "brcm,spum-crypto"; | ||
252 | reg = <0x61310000 0x900>; | ||
253 | mboxes = <&pdc2 0>; | ||
254 | }; | ||
255 | |||
238 | pdc3: iproc-pdc3@61320000 { | 256 | pdc3: iproc-pdc3@61320000 { |
239 | compatible = "brcm,iproc-pdc-mbox"; | 257 | compatible = "brcm,iproc-pdc-mbox"; |
240 | reg = <0x61320000 0x445>; /* PDC FS3 regs */ | 258 | reg = <0x61320000 0x445>; /* PDC FS3 regs */ |
@@ -244,6 +262,12 @@ | |||
244 | brcm,use-bcm-hdr; | 262 | brcm,use-bcm-hdr; |
245 | }; | 263 | }; |
246 | 264 | ||
265 | crypto3: crypto@61330000 { | ||
266 | compatible = "brcm,spum-crypto"; | ||
267 | reg = <0x61330000 0x900>; | ||
268 | mboxes = <&pdc3 0>; | ||
269 | }; | ||
270 | |||
247 | dma0: dma@61360000 { | 271 | dma0: dma@61360000 { |
248 | compatible = "arm,pl330", "arm,primecell"; | 272 | compatible = "arm,pl330", "arm,primecell"; |
249 | reg = <0x61360000 0x1000>; | 273 | reg = <0x61360000 0x1000>; |