Merge tag 'for_3.18/samsung-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/tfiga/samsung-clk into clk-next

Samsung clock patches for v3.18

1) non-critical fixes (without the need to push to stable)

fa0111be4ff3 clk: samsung: exynos4: remove duplicate div_core2 divider clock instantiation
b511593d7165 clk: samsung: exynos4: fix g3d clocks
c14254300131 clk: samsung: exynos4: add missing smmu_g2d clock and update comments
22842d244af3 clk: samsung: exynos5260: fix typo in clock name
e82ba578ccde clk: samsung: exynos3250: fix width field of mout_mmc0/1
59037b92f440 clk: samsung: exynos3250: fix width and shift of div_spi0_isp clock
5ce37f266650 clk: samsung: exynos3250: fix mout_cam_blk parent list

2) Clock driver extensions

07ccf02ba5c3 dt-bindings: clk: samsung: Document the DMC domain of Exynos3250 CMU
d0e73eaf1925 ARM: dts: exynos3250: Add CMU node for DMC domain clocks
e3c3f19bc618 clk: samsung: exynos3250: Register DMC clk provider
4676f0aab9dc clk: samsung: exynos4: add support for MOUT_HDMI and MOUT_MIXER clocks

7 files changed, 257 insertions, 20 deletions

diff --git a/Documentation/devicetree/bindings/clock/exynos3250-clock.txt b/Documentation/devicetree/bindings/clock/exynos3250-clock.txt
index aadc9c59e2d1..f57d9dd9ea85 100644
--- a/Documentation/devicetree/bindings/clock/exynos3250-clock.txt
+++ b/Documentation/devicetree/bindings/clock/exynos3250-clock.txt
@@ -7,6 +7,8 @@ Required Properties:
 
 - compatible: should be one of the following.
   - "samsung,exynos3250-cmu" - controller compatible with Exynos3250 SoC.
+  - "samsung,exynos3250-cmu-dmc" - controller compatible with
+    Exynos3250 SoC for Dynamic Memory Controller domain.
 
 - reg: physical base address of the controller and length of memory mapped
   region.
@@ -20,7 +22,7 @@ All available clocks are defined as preprocessor macros in
 dt-bindings/clock/exynos3250.h header and can be used in device
 tree sources.
 
-Example 1: An example of a clock controller node is listed below.
+Example 1: Examples of clock controller nodes are listed below.
 
         cmu: clock-controller@10030000 {
                 compatible = "samsung,exynos3250-cmu";
@@ -28,6 +30,12 @@ Example 1: An example of a clock controller node is listed below.
                 #clock-cells = <1>;
         };
 
+        cmu_dmc: clock-controller@105C0000 {
+                compatible = "samsung,exynos3250-cmu-dmc";
+                reg = <0x105C0000 0x2000>;
+                #clock-cells = <1>;
+        };
+
 Example 2: UART controller node that consumes the clock generated by the clock
            controller. Refer to the standard clock bindings for information
            about 'clocks' and 'clock-names' property.
diff --git a/arch/arm/boot/dts/exynos3250.dtsi b/arch/arm/boot/dts/exynos3250.dtsi
index 1d52de6370d5..72bf1b573788 100644
--- a/arch/arm/boot/dts/exynos3250.dtsi
+++ b/arch/arm/boot/dts/exynos3250.dtsi
@@ -163,6 +163,12 @@
                         #clock-cells = <1>;
                 };
 
+                cmu_dmc: clock-controller@105C0000 {
+                        compatible = "samsung,exynos3250-cmu-dmc";
+                        reg = <0x105C0000 0x2000>;
+                        #clock-cells = <1>;
+                };
+
                 rtc: rtc@10070000 {
                         compatible = "samsung,s3c6410-rtc";
                         reg = <0x10070000 0x100>;
diff --git a/drivers/clk/samsung/clk-exynos3250.c b/drivers/clk/samsung/clk-exynos3250.c
index dc85f8e7a2d7..6e6cca392082 100644
--- a/drivers/clk/samsung/clk-exynos3250.c
+++ b/drivers/clk/samsung/clk-exynos3250.c
@@ -110,7 +110,14 @@ enum exynos3250_plls {
         nr_plls
 };
 
+/* list of PLLs in DMC block to be registered */
+enum exynos3250_dmc_plls {
+        bpll, epll,
+        nr_dmc_plls
+};
+
 static void __iomem *reg_base;
+static void __iomem *dmc_reg_base;
 
 /*
  * Support for CMU save/restore across system suspends
@@ -266,6 +273,7 @@ PNAME(group_sclk_cam_blk_p)	= { "xxti", "xusbxti",
                                     "none", "none", "none",
                                     "none", "div_mpll_pre",
                                     "mout_epll_user", "mout_vpll",
+                                    "none", "none", "none",
                                     "div_cam_blk_320", };
 PNAME(group_sclk_fimd0_p)       = { "xxti", "xusbxti",
                                     "m_bitclkhsdiv4_2l", "none",
@@ -353,8 +361,8 @@ static struct samsung_mux_clock mux_clks[] __initdata = {
 
         /* SRC_FSYS */
         MUX(CLK_MOUT_TSADC, "mout_tsadc", group_sclk_p, SRC_FSYS, 28, 4),
-        MUX(CLK_MOUT_MMC1, "mout_mmc1", group_sclk_p, SRC_FSYS, 4, 3),
-        MUX(CLK_MOUT_MMC0, "mout_mmc0", group_sclk_p, SRC_FSYS, 0, 3),
+        MUX(CLK_MOUT_MMC1, "mout_mmc1", group_sclk_p, SRC_FSYS, 4, 4),
+        MUX(CLK_MOUT_MMC0, "mout_mmc0", group_sclk_p, SRC_FSYS, 0, 4),
 
         /* SRC_PERIL0 */
         MUX(CLK_MOUT_UART1, "mout_uart1", group_sclk_p, SRC_PERIL0, 4, 4),
@@ -423,7 +431,7 @@ static struct samsung_div_clock div_clks[] __initdata = {
         DIV(CLK_DIV_SPI1_ISP, "div_spi1_isp", "mout_spi1_isp", DIV_ISP, 16, 4),
         DIV_F(CLK_DIV_SPI0_ISP_PRE, "div_spi0_isp_pre", "div_spi0_isp",
                 DIV_ISP, 8, 8, CLK_SET_RATE_PARENT, 0),
-        DIV(CLK_DIV_SPI0_ISP, "div_spi0_isp", "mout_spi0_isp", DIV_ISP, 0, 4),
+        DIV(CLK_DIV_SPI0_ISP, "div_spi0_isp", "mout_spi0_isp", DIV_ISP, 4, 4),
 
         /* DIV_FSYS0 */
         DIV_F(CLK_DIV_TSADC_PRE, "div_tsadc_pre", "div_tsadc", DIV_FSYS0, 8, 8,
@@ -724,6 +732,25 @@ static struct samsung_pll_rate_table exynos3250_pll_rates[] = {
         { /* sentinel */ }
 };
 
+/* EPLL */
+static struct samsung_pll_rate_table exynos3250_epll_rates[] = {
+        PLL_36XX_RATE(800000000, 200, 3, 1,     0),
+        PLL_36XX_RATE(288000000,  96, 2, 2,     0),
+        PLL_36XX_RATE(192000000, 128, 2, 3,     0),
+        PLL_36XX_RATE(144000000,  96, 2, 3,     0),
+        PLL_36XX_RATE( 96000000, 128, 2, 4,     0),
+        PLL_36XX_RATE( 84000000, 112, 2, 4,     0),
+        PLL_36XX_RATE( 80000004, 106, 2, 4, 43691),
+        PLL_36XX_RATE( 73728000,  98, 2, 4, 19923),
+        PLL_36XX_RATE( 67737598, 270, 3, 5, 62285),
+        PLL_36XX_RATE( 65535999, 174, 2, 5, 49982),
+        PLL_36XX_RATE( 50000000, 200, 3, 5,     0),
+        PLL_36XX_RATE( 49152002, 131, 2, 5,  4719),
+        PLL_36XX_RATE( 48000000, 128, 2, 5,     0),
+        PLL_36XX_RATE( 45158401, 180, 3, 5, 41524),
+        { /* sentinel */ }
+};
+
 /* VPLL */
 static struct samsung_pll_rate_table exynos3250_vpll_rates[] = {
         PLL_36XX_RATE(600000000, 100, 2, 1,     0),
@@ -821,3 +848,172 @@ static void __init exynos3250_cmu_init(struct device_node *np)
         samsung_clk_of_add_provider(np, ctx);
 }
 CLK_OF_DECLARE(exynos3250_cmu, "samsung,exynos3250-cmu", exynos3250_cmu_init);
+
+/*
+ * CMU DMC
+ */
+
+#define BPLL_LOCK               0x0118
+#define BPLL_CON0               0x0218
+#define BPLL_CON1               0x021c
+#define BPLL_CON2               0x0220
+#define SRC_DMC                 0x0300
+#define DIV_DMC1                0x0504
+#define GATE_BUS_DMC0           0x0700
+#define GATE_BUS_DMC1           0x0704
+#define GATE_BUS_DMC2           0x0708
+#define GATE_BUS_DMC3           0x070c
+#define GATE_SCLK_DMC           0x0800
+#define GATE_IP_DMC0            0x0900
+#define GATE_IP_DMC1            0x0904
+#define EPLL_LOCK               0x1110
+#define EPLL_CON0               0x1114
+#define EPLL_CON1               0x1118
+#define EPLL_CON2               0x111c
+#define SRC_EPLL                0x1120
+
+/*
+ * Support for CMU save/restore across system suspends
+ */
+#ifdef CONFIG_PM_SLEEP
+static struct samsung_clk_reg_dump *exynos3250_dmc_clk_regs;
+
+static unsigned long exynos3250_cmu_dmc_clk_regs[] __initdata = {
+        BPLL_LOCK,
+        BPLL_CON0,
+        BPLL_CON1,
+        BPLL_CON2,
+        SRC_DMC,
+        DIV_DMC1,
+        GATE_BUS_DMC0,
+        GATE_BUS_DMC1,
+        GATE_BUS_DMC2,
+        GATE_BUS_DMC3,
+        GATE_SCLK_DMC,
+        GATE_IP_DMC0,
+        GATE_IP_DMC1,
+        EPLL_LOCK,
+        EPLL_CON0,
+        EPLL_CON1,
+        EPLL_CON2,
+        SRC_EPLL,
+};
+
+static int exynos3250_dmc_clk_suspend(void)
+{
+        samsung_clk_save(dmc_reg_base, exynos3250_dmc_clk_regs,
+                                ARRAY_SIZE(exynos3250_cmu_dmc_clk_regs));
+        return 0;
+}
+
+static void exynos3250_dmc_clk_resume(void)
+{
+        samsung_clk_restore(dmc_reg_base, exynos3250_dmc_clk_regs,
+                                ARRAY_SIZE(exynos3250_cmu_dmc_clk_regs));
+}
+
+static struct syscore_ops exynos3250_dmc_clk_syscore_ops = {
+        .suspend = exynos3250_dmc_clk_suspend,
+        .resume = exynos3250_dmc_clk_resume,
+};
+
+static void exynos3250_dmc_clk_sleep_init(void)
+{
+        exynos3250_dmc_clk_regs =
+                samsung_clk_alloc_reg_dump(exynos3250_cmu_dmc_clk_regs,
+                                   ARRAY_SIZE(exynos3250_cmu_dmc_clk_regs));
+        if (!exynos3250_dmc_clk_regs) {
+                pr_warn("%s: Failed to allocate sleep save data\n", __func__);
+                goto err;
+        }
+
+        register_syscore_ops(&exynos3250_dmc_clk_syscore_ops);
+        return;
+err:
+        kfree(exynos3250_dmc_clk_regs);
+}
+#else
+static inline void exynos3250_dmc_clk_sleep_init(void) { }
+#endif
+
+PNAME(mout_epll_p)      = { "fin_pll", "fout_epll", };
+PNAME(mout_bpll_p)      = { "fin_pll", "fout_bpll", };
+PNAME(mout_mpll_mif_p)  = { "fin_pll", "sclk_mpll_mif", };
+PNAME(mout_dphy_p)      = { "mout_mpll_mif", "mout_bpll", };
+
+static struct samsung_mux_clock dmc_mux_clks[] __initdata = {
+        /*
+         * NOTE: Following table is sorted by register address in ascending
+         * order and then bitfield shift in descending order, as it is done
+         * in the User's Manual. When adding new entries, please make sure
+         * that the order is preserved, to avoid merge conflicts and make
+         * further work with defined data easier.
+         */
+
+        /* SRC_DMC */
+        MUX(CLK_MOUT_MPLL_MIF, "mout_mpll_mif", mout_mpll_mif_p, SRC_DMC, 12, 1),
+        MUX(CLK_MOUT_BPLL, "mout_bpll", mout_bpll_p, SRC_DMC, 10, 1),
+        MUX(CLK_MOUT_DPHY, "mout_dphy", mout_dphy_p, SRC_DMC, 8, 1),
+        MUX(CLK_MOUT_DMC_BUS, "mout_dmc_bus", mout_dphy_p, SRC_DMC,  4, 1),
+
+        /* SRC_EPLL */
+        MUX(CLK_MOUT_EPLL, "mout_epll", mout_epll_p, SRC_EPLL, 4, 1),
+};
+
+static struct samsung_div_clock dmc_div_clks[] __initdata = {
+        /*
+         * NOTE: Following table is sorted by register address in ascending
+         * order and then bitfield shift in descending order, as it is done
+         * in the User's Manual. When adding new entries, please make sure
+         * that the order is preserved, to avoid merge conflicts and make
+         * further work with defined data easier.
+         */
+
+        /* DIV_DMC1 */
+        DIV(CLK_DIV_DMC, "div_dmc", "div_dmc_pre", DIV_DMC1, 27, 3),
+        DIV(CLK_DIV_DPHY, "div_dphy", "mout_dphy", DIV_DMC1, 23, 3),
+        DIV(CLK_DIV_DMC_PRE, "div_dmc_pre", "mout_dmc_bus", DIV_DMC1, 19, 2),
+        DIV(CLK_DIV_DMCP, "div_dmcp", "div_dmcd", DIV_DMC1, 15, 3),
+        DIV(CLK_DIV_DMCD, "div_dmcd", "div_dmc", DIV_DMC1, 11, 3),
+};
+
+static struct samsung_pll_clock exynos3250_dmc_plls[nr_dmc_plls] __initdata = {
+        [bpll] = PLL(pll_35xx, CLK_FOUT_BPLL, "fout_bpll", "fin_pll",
+                        BPLL_LOCK, BPLL_CON0, NULL),
+        [epll] = PLL(pll_36xx, CLK_FOUT_EPLL, "fout_epll", "fin_pll",
+                        EPLL_LOCK, EPLL_CON0, NULL),
+};
+
+static void __init exynos3250_cmu_dmc_init(struct device_node *np)
+{
+        struct samsung_clk_provider *ctx;
+
+        dmc_reg_base = of_iomap(np, 0);
+        if (!dmc_reg_base)
+                panic("%s: failed to map registers\n", __func__);
+
+        ctx = samsung_clk_init(np, dmc_reg_base, NR_CLKS_DMC);
+        if (!ctx)
+                panic("%s: unable to allocate context.\n", __func__);
+
+        exynos3250_dmc_plls[bpll].rate_table = exynos3250_pll_rates;
+        exynos3250_dmc_plls[epll].rate_table = exynos3250_epll_rates;
+
+        pr_err("CLK registering epll bpll: %d, %d, %d, %d\n",
+                        exynos3250_dmc_plls[bpll].rate_table[0].rate,
+                        exynos3250_dmc_plls[bpll].rate_table[0].mdiv,
+                        exynos3250_dmc_plls[bpll].rate_table[0].pdiv,
+                        exynos3250_dmc_plls[bpll].rate_table[0].sdiv
+              );
+        samsung_clk_register_pll(ctx, exynos3250_dmc_plls,
+                                ARRAY_SIZE(exynos3250_dmc_plls), dmc_reg_base);
+
+        samsung_clk_register_mux(ctx, dmc_mux_clks, ARRAY_SIZE(dmc_mux_clks));
+        samsung_clk_register_div(ctx, dmc_div_clks, ARRAY_SIZE(dmc_div_clks));
+
+        exynos3250_dmc_clk_sleep_init();
+
+        samsung_clk_of_add_provider(np, ctx);
+}
+CLK_OF_DECLARE(exynos3250_cmu_dmc, "samsung,exynos3250-cmu-dmc",
+                exynos3250_cmu_dmc_init);
diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c
index ac163d7f5bc3..940f02837b82 100644
--- a/drivers/clk/samsung/clk-exynos4.c
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -517,7 +517,7 @@ static struct samsung_fixed_factor_clock exynos4_fixed_factor_clks[] __initdata
         FFACTOR(0, "sclk_apll_div_2", "sclk_apll", 1, 2, 0),
         FFACTOR(0, "fout_mpll_div_2", "fout_mpll", 1, 2, 0),
         FFACTOR(0, "fout_apll_div_2", "fout_apll", 1, 2, 0),
-        FFACTOR(0, "arm_clk_div_2", "arm_clk", 1, 2, 0),
+        FFACTOR(0, "arm_clk_div_2", "div_core2", 1, 2, 0),
 };
 
 static struct samsung_fixed_factor_clock exynos4210_fixed_factor_clks[] __initdata = {
@@ -535,7 +535,7 @@ static struct samsung_fixed_factor_clock exynos4x12_fixed_factor_clks[] __initda
 static struct samsung_mux_clock exynos4_mux_clks[] __initdata = {
         MUX_FA(CLK_MOUT_APLL, "mout_apll", mout_apll_p, SRC_CPU, 0, 1,
                         CLK_SET_RATE_PARENT, 0, "mout_apll"),
-        MUX(0, "mout_hdmi", mout_hdmi_p, SRC_TV, 0, 1),
+        MUX(CLK_MOUT_HDMI, "mout_hdmi", mout_hdmi_p, SRC_TV, 0, 1),
         MUX(0, "mout_mfc1", sclk_evpll_p, SRC_MFC, 4, 1),
         MUX(0, "mout_mfc", mout_mfc_p, SRC_MFC, 8, 1),
         MUX_F(CLK_MOUT_G3D1, "mout_g3d1", sclk_evpll_p, SRC_G3D, 4, 1,
@@ -569,7 +569,7 @@ static struct samsung_mux_clock exynos4210_mux_clks[] __initdata = {
         MUX(0, "mout_aclk100", sclk_ampll_p4210, SRC_TOP0, 16, 1),
         MUX(0, "mout_aclk160", sclk_ampll_p4210, SRC_TOP0, 20, 1),
         MUX(0, "mout_aclk133", sclk_ampll_p4210, SRC_TOP0, 24, 1),
-        MUX(0, "mout_mixer", mout_mixer_p4210, SRC_TV, 4, 1),
+        MUX(CLK_MOUT_MIXER, "mout_mixer", mout_mixer_p4210, SRC_TV, 4, 1),
         MUX(0, "mout_dac", mout_dac_p4210, SRC_TV, 8, 1),
         MUX(0, "mout_g2d0", sclk_ampll_p4210, E4210_SRC_IMAGE, 0, 1),
         MUX(0, "mout_g2d1", sclk_evpll_p, E4210_SRC_IMAGE, 4, 1),
@@ -719,7 +719,7 @@ static struct samsung_div_clock exynos4_div_clks[] __initdata = {
         DIV(0, "div_periph", "div_core2", DIV_CPU0, 12, 3),
         DIV(0, "div_atb", "mout_core", DIV_CPU0, 16, 3),
         DIV(0, "div_pclk_dbg", "div_atb", DIV_CPU0, 20, 3),
-        DIV(0, "div_core2", "div_core", DIV_CPU0, 28, 3),
+        DIV(CLK_ARM_CLK, "div_core2", "div_core", DIV_CPU0, 28, 3),
         DIV(0, "div_copy", "mout_hpm", DIV_CPU1, 0, 3),
         DIV(0, "div_hpm", "div_copy", DIV_CPU1, 4, 3),
         DIV(0, "div_clkout_cpu", "mout_clkout_cpu", CLKOUT_CMU_CPU, 8, 6),
@@ -733,8 +733,7 @@ static struct samsung_div_clock exynos4_div_clks[] __initdata = {
         DIV(0, "div_csis0", "mout_csis0", DIV_CAM, 24, 4),
         DIV(0, "div_csis1", "mout_csis1", DIV_CAM, 28, 4),
         DIV(CLK_SCLK_MFC, "sclk_mfc", "mout_mfc", DIV_MFC, 0, 4),
-        DIV_F(0, "div_g3d", "mout_g3d", DIV_G3D, 0, 4,
-                        CLK_SET_RATE_PARENT, 0),
+        DIV(CLK_SCLK_G3D, "sclk_g3d", "mout_g3d", DIV_G3D, 0, 4),
         DIV(0, "div_fimd0", "mout_fimd0", DIV_LCD0, 0, 4),
         DIV(0, "div_mipi0", "mout_mipi0", DIV_LCD0, 16, 4),
         DIV(0, "div_audio0", "mout_audio0", DIV_MAUDIO, 0, 4),
@@ -769,7 +768,6 @@ static struct samsung_div_clock exynos4_div_clks[] __initdata = {
         DIV(0, "div_spi_pre2", "div_spi2", DIV_PERIL2, 8, 8),
         DIV(0, "div_audio1", "mout_audio1", DIV_PERIL4, 0, 4),
         DIV(0, "div_audio2", "mout_audio2", DIV_PERIL4, 16, 4),
-        DIV(CLK_ARM_CLK, "arm_clk", "div_core2", DIV_CPU0, 28, 3),
         DIV(CLK_SCLK_APLL, "sclk_apll", "mout_apll", DIV_CPU0, 24, 3),
         DIV_F(0, "div_mipi_pre0", "div_mipi0", DIV_LCD0, 20, 4,
                         CLK_SET_RATE_PARENT, 0),
@@ -857,8 +855,7 @@ static struct samsung_gate_clock exynos4_gate_clks[] __initdata = {
                 0),
         GATE(CLK_TSI, "tsi", "aclk133", GATE_IP_FSYS, 4, 0, 0),
         GATE(CLK_SROMC, "sromc", "aclk133", GATE_IP_FSYS, 11, 0, 0),
-        GATE(CLK_SCLK_G3D, "sclk_g3d", "div_g3d", GATE_IP_G3D, 0,
-                        CLK_SET_RATE_PARENT, 0),
+        GATE(CLK_G3D, "g3d", "aclk200", GATE_IP_G3D, 0, 0, 0),
         GATE(CLK_PPMUG3D, "ppmug3d", "aclk200", GATE_IP_G3D, 1, 0, 0),
         GATE(CLK_USB_DEVICE, "usb_device", "aclk133", GATE_IP_FSYS, 13, 0, 0),
         GATE(CLK_ONENAND, "onenand", "aclk133", GATE_IP_FSYS, 15, 0, 0),
@@ -1183,6 +1180,7 @@ static struct samsung_gate_clock exynos4x12_gate_clks[] __initdata = {
         GATE(CLK_SPI1_ISP, "spi1_isp", "aclk200", E4X12_GATE_ISP1, 13,
                         CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
         GATE(CLK_G2D, "g2d", "aclk200", GATE_IP_DMC, 23, 0, 0),
+        GATE(CLK_SMMU_G2D, "smmu_g2d", "aclk200", GATE_IP_DMC, 24, 0, 0),
         GATE(CLK_TMU_APBIF, "tmu_apbif", "aclk100", E4X12_GATE_IP_PERIR, 17, 0,
                 0),
 };
@@ -1486,7 +1484,7 @@ static void __init exynos4_clk_init(struct device_node *np,
                 exynos4_soc == EXYNOS4210 ? "Exynos4210" : "Exynos4x12",
                 _get_rate("sclk_apll"), _get_rate("sclk_mpll"),
                 _get_rate("sclk_epll"), _get_rate("sclk_vpll"),
-                _get_rate("arm_clk"));
+                _get_rate("div_core2"));
 }
 
 
diff --git a/drivers/clk/samsung/clk-exynos5260.c b/drivers/clk/samsung/clk-exynos5260.c
index ce3de97e5f11..2527e39aadcf 100644
--- a/drivers/clk/samsung/clk-exynos5260.c
+++ b/drivers/clk/samsung/clk-exynos5260.c
@@ -1581,7 +1581,7 @@ struct samsung_fixed_rate_clock fixed_rate_clks[] __initdata = {
         FRATE(PHYCLK_HDMI_LINK_O_TMDS_CLKHI, "phyclk_hdmi_link_o_tmds_clkhi",
                         NULL, CLK_IS_ROOT, 125000000),
         FRATE(PHYCLK_MIPI_DPHY_4L_M_TXBYTECLKHS,
-                        "phyclk_mipi_dphy_4l_m_txbyteclkhs" , NULL,
+                        "phyclk_mipi_dphy_4l_m_txbyte_clkhs" , NULL,
                         CLK_IS_ROOT, 187500000),
         FRATE(PHYCLK_DPTX_PHY_O_REF_CLK_24M, "phyclk_dptx_phy_o_ref_clk_24m",
                         NULL, CLK_IS_ROOT, 24000000),
diff --git a/include/dt-bindings/clock/exynos3250.h b/include/dt-bindings/clock/exynos3250.h
index b535e9da7de6..961b9c130ea9 100644
--- a/include/dt-bindings/clock/exynos3250.h
+++ b/include/dt-bindings/clock/exynos3250.h
@@ -255,4 +255,31 @@
  */
 #define CLK_NR_CLKS                     248
 
+/*
+ * CMU DMC
+ */
+
+#define CLK_FOUT_BPLL                   1
+#define CLK_FOUT_EPLL                   2
+
+/* Muxes */
+#define CLK_MOUT_MPLL_MIF               8
+#define CLK_MOUT_BPLL                   9
+#define CLK_MOUT_DPHY                   10
+#define CLK_MOUT_DMC_BUS                11
+#define CLK_MOUT_EPLL                   12
+
+/* Dividers */
+#define CLK_DIV_DMC                     16
+#define CLK_DIV_DPHY                    17
+#define CLK_DIV_DMC_PRE                 18
+#define CLK_DIV_DMCP                    19
+#define CLK_DIV_DMCD                    20
+
+/*
+ * Total number of clocks of main CMU.
+ * NOTE: Must be equal to last clock ID increased by one.
+ */
+#define NR_CLKS_DMC                     21
+
 #endif /* _DT_BINDINGS_CLOCK_SAMSUNG_EXYNOS3250_CLOCK_H */
diff --git a/include/dt-bindings/clock/exynos4.h b/include/dt-bindings/clock/exynos4.h
index 459bd2bd411f..34fe28c622d0 100644
--- a/include/dt-bindings/clock/exynos4.h
+++ b/include/dt-bindings/clock/exynos4.h
@@ -115,11 +115,11 @@
 #define CLK_SMMU_MFCR           275
 #define CLK_G3D                 276
 #define CLK_G2D                 277
-#define CLK_ROTATOR             278 /* Exynos4210 only */
-#define CLK_MDMA                279 /* Exynos4210 only */
-#define CLK_SMMU_G2D            280 /* Exynos4210 only */
-#define CLK_SMMU_ROTATOR        281 /* Exynos4210 only */
-#define CLK_SMMU_MDMA           282 /* Exynos4210 only */
+#define CLK_ROTATOR             278
+#define CLK_MDMA                279
+#define CLK_SMMU_G2D            280
+#define CLK_SMMU_ROTATOR        281
+#define CLK_SMMU_MDMA           282
 #define CLK_FIMD0               283
 #define CLK_MIE0                284
 #define CLK_MDNIE0              285 /* Exynos4412 only */
@@ -234,6 +234,8 @@
 #define CLK_MOUT_G3D1           393
 #define CLK_MOUT_G3D            394
 #define CLK_ACLK400_MCUISP      395 /* Exynos4x12 only */
+#define CLK_MOUT_HDMI           396
+#define CLK_MOUT_MIXER          397
 
 /* gate clocks - ppmu */
 #define CLK_PPMULEFT            400