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authorVille Syrjälä <ville.syrjala@linux.intel.com>2015-06-02 08:37:37 -0400
committerJani Nikula <jani.nikula@intel.com>2015-06-03 07:11:35 -0400
commit2441f8779e886d74389bf78aad149dc99876a900 (patch)
tree582433fd5adb653c92707e9944e859586e4457fc
parent9cc83020616d38339e6c29dc44536e9806abfdb0 (diff)
drm/i915: Apply WaDisableAsyncFlipPerfMode via LRIs on gen8
MI_MODE is saved in the logical context so WaDisableAsyncFlipPerfMode must be applied using LRIs on gen8. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
-rw-r--r--drivers/gpu/drm/i915/intel_ringbuffer.c10
1 files changed, 8 insertions, 2 deletions
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 06f4b22c6327..b70d25bffb60 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -802,6 +802,9 @@ static int bdw_init_workarounds(struct intel_engine_cs *ring)
802 802
803 WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING); 803 WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING);
804 804
805 /* WaDisableAsyncFlipPerfMode:bdw */
806 WA_SET_BIT_MASKED(MI_MODE, ASYNC_FLIP_PERF_DISABLE);
807
805 /* WaDisablePartialInstShootdown:bdw */ 808 /* WaDisablePartialInstShootdown:bdw */
806 /* WaDisableThreadStallDopClockGating:bdw (pre-production) */ 809 /* WaDisableThreadStallDopClockGating:bdw (pre-production) */
807 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, 810 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
@@ -865,6 +868,9 @@ static int chv_init_workarounds(struct intel_engine_cs *ring)
865 868
866 WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING); 869 WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING);
867 870
871 /* WaDisableAsyncFlipPerfMode:chv */
872 WA_SET_BIT_MASKED(MI_MODE, ASYNC_FLIP_PERF_DISABLE);
873
868 /* WaDisablePartialInstShootdown:chv */ 874 /* WaDisablePartialInstShootdown:chv */
869 /* WaDisableThreadStallDopClockGating:chv */ 875 /* WaDisableThreadStallDopClockGating:chv */
870 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, 876 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
@@ -1109,9 +1115,9 @@ static int init_render_ring(struct intel_engine_cs *ring)
1109 * to use MI_WAIT_FOR_EVENT within the CS. It should already be 1115 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
1110 * programmed to '1' on all products. 1116 * programmed to '1' on all products.
1111 * 1117 *
1112 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv 1118 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv
1113 */ 1119 */
1114 if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 9) 1120 if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8)
1115 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE)); 1121 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
1116 1122
1117 /* Required for the hardware to program scanline values for waiting */ 1123 /* Required for the hardware to program scanline values for waiting */