x86/bugs: Rename SSBD_NO to SSB_NO

The "336996 Speculative Execution Side Channel Mitigations" from
May defines this as SSB_NO, hence lets sync-up.

Signed-off-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>

2 files changed, 2 insertions, 2 deletions

diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index 562414d5b834..fda2114197b3 100644
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -70,7 +70,7 @@
 #define MSR_IA32_ARCH_CAPABILITIES      0x0000010a
 #define ARCH_CAP_RDCL_NO                (1 << 0)   /* Not susceptible to Meltdown */
 #define ARCH_CAP_IBRS_ALL               (1 << 1)   /* Enhanced IBRS support */
-#define ARCH_CAP_SSBD_NO                (1 << 4)   /*
+#define ARCH_CAP_SSB_NO                 (1 << 4)   /*
                                                     * Not susceptible to Speculative Store Bypass
                                                     * attack, so no Speculative Store Bypass
                                                     * control required.
diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
index b4247ed0c81e..78decc3e3067 100644
--- a/arch/x86/kernel/cpu/common.c
+++ b/arch/x86/kernel/cpu/common.c
@@ -974,7 +974,7 @@ static void __init cpu_set_bug_bits(struct cpuinfo_x86 *c)
                 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, ia32_cap);
 
         if (!x86_match_cpu(cpu_no_spec_store_bypass) &&
-           !(ia32_cap & ARCH_CAP_SSBD_NO))
+           !(ia32_cap & ARCH_CAP_SSB_NO))
                 setup_force_cpu_bug(X86_BUG_SPEC_STORE_BYPASS);
 
         if (x86_match_cpu(cpu_no_speculation))