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authorSujith Manoharan <c_manoha@qca.qualcomm.com>2015-02-02 07:51:12 -0500
committerKalle Valo <kvalo@codeaurora.org>2015-02-06 01:39:37 -0500
commit23ee7c33aa7caae5985a919e597ba2e355d540ea (patch)
treea17e78bdd62d3adbf6c9ef63c26f73605a55b560
parentb6f68b1ecbffc0aec1704c731c3b99acbe3becfd (diff)
ath9k: Clear TSF2 properly
Chips in the AR9003 family have a second TSF, which needs to be cleared when putting the card to sleep. Signed-off-by: Sujith Manoharan <c_manoha@qca.qualcomm.com> Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
-rw-r--r--drivers/net/wireless/ath/ath9k/ar9003_wow.c9
-rw-r--r--drivers/net/wireless/ath/ath9k/reg.h2
2 files changed, 11 insertions, 0 deletions
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_wow.c b/drivers/net/wireless/ath/ath9k/ar9003_wow.c
index cf45b91f0a60..2dc50a0eedc4 100644
--- a/drivers/net/wireless/ath/ath9k/ar9003_wow.c
+++ b/drivers/net/wireless/ath/ath9k/ar9003_wow.c
@@ -35,6 +35,15 @@ static void ath9k_hw_set_powermode_wow_sleep(struct ath_hw *ah)
35 return; 35 return;
36 } 36 }
37 37
38 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
39 if (!REG_READ(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL))
40 REG_CLR_BIT(ah, AR_DIRECT_CONNECT, AR_DC_TSF2_ENABLE);
41 } else if (AR_SREV_9485(ah)){
42 if (!(REG_READ(ah, AR_NDP2_TIMER_MODE) &
43 AR_GEN_TIMERS2_MODE_ENABLE_MASK))
44 REG_CLR_BIT(ah, AR_DIRECT_CONNECT, AR_DC_TSF2_ENABLE);
45 }
46
38 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_ON_INT); 47 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_ON_INT);
39} 48}
40 49
diff --git a/drivers/net/wireless/ath/ath9k/reg.h b/drivers/net/wireless/ath/ath9k/reg.h
index b1b803d05926..9587ec655680 100644
--- a/drivers/net/wireless/ath/ath9k/reg.h
+++ b/drivers/net/wireless/ath/ath9k/reg.h
@@ -1883,6 +1883,7 @@ enum {
1883#define AR_FIRST_NDP_TIMER 7 1883#define AR_FIRST_NDP_TIMER 7
1884#define AR_NDP2_PERIOD 0x81a0 1884#define AR_NDP2_PERIOD 0x81a0
1885#define AR_NDP2_TIMER_MODE 0x81c0 1885#define AR_NDP2_TIMER_MODE 0x81c0
1886#define AR_GEN_TIMERS2_MODE_ENABLE_MASK 0x000000FF
1886 1887
1887#define AR_GEN_TIMERS(_i) (0x8200 + ((_i) << 2)) 1888#define AR_GEN_TIMERS(_i) (0x8200 + ((_i) << 2))
1888#define AR_NEXT_TBTT_TIMER AR_GEN_TIMERS(0) 1889#define AR_NEXT_TBTT_TIMER AR_GEN_TIMERS(0)
@@ -1978,6 +1979,7 @@ enum {
1978 1979
1979#define AR_DIRECT_CONNECT 0x83a0 1980#define AR_DIRECT_CONNECT 0x83a0
1980#define AR_DC_AP_STA_EN 0x00000001 1981#define AR_DC_AP_STA_EN 0x00000001
1982#define AR_DC_TSF2_ENABLE 0x00000001
1981 1983
1982#define AR_AES_MUTE_MASK0 0x805c 1984#define AR_AES_MUTE_MASK0 0x805c
1983#define AR_AES_MUTE_MASK0_FC 0x0000FFFF 1985#define AR_AES_MUTE_MASK0_FC 0x0000FFFF