MIPS: Add CP0 macros for extended EntryLo registers

Add read/write macros to access the upper bits of the
extended EntryLo0 and EntryLo1 registers used by XPA.

Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/8455/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

1 files changed, 40 insertions, 0 deletions

diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index 7ebb6544392e..087b2af00150 100644
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -653,6 +653,7 @@
 #define MIPS_CONF5_NF           (_ULCAST_(1) << 0)
 #define MIPS_CONF5_UFR          (_ULCAST_(1) << 2)
 #define MIPS_CONF5_MRP          (_ULCAST_(1) << 3)
+#define MIPS_CONF5_MVH          (_ULCAST_(1) << 5)
 #define MIPS_CONF5_FRE          (_ULCAST_(1) << 8)
 #define MIPS_CONF5_UFE          (_ULCAST_(1) << 9)
 #define MIPS_CONF5_MSAEN        (_ULCAST_(1) << 27)
@@ -995,6 +996,39 @@ do {									\
         local_irq_restore(__flags);                                     \
 } while (0)
 
+#define __readx_32bit_c0_register(source)                               \
+({                                                                      \
+        unsigned int __res;                                             \
+                                                                        \
+        __asm__ __volatile__(                                           \
+        "       .set    push                                    \n"     \
+        "       .set    noat                                    \n"     \
+        "       .set    mips32r2                                \n"     \
+        "       .insn                                           \n"     \
+        "       # mfhc0 $1, %1                                  \n"     \
+        "       .word   (0x40410000 | ((%1 & 0x1f) << 11))      \n"     \
+        "       move    %0, $1                                  \n"     \
+        "       .set    pop                                     \n"     \
+        : "=r" (__res)                                                  \
+        : "i" (source));                                                \
+        __res;                                                          \
+})
+
+#define __writex_32bit_c0_register(register, value)                     \
+do {                                                                    \
+        __asm__ __volatile__(                                           \
+        "       .set    push                                    \n"     \
+        "       .set    noat                                    \n"     \
+        "       .set    mips32r2                                \n"     \
+        "       move    $1, %0                                  \n"     \
+        "       # mthc0 $1, %1                                  \n"     \
+        "       .insn                                           \n"     \
+        "       .word   (0x40c10000 | ((%1 & 0x1f) << 11))      \n"     \
+        "       .set    pop                                     \n"     \
+        :                                                               \
+        : "r" (value), "i" (register));                                 \
+} while (0)
+
 #define read_c0_index()         __read_32bit_c0_register($0, 0)
 #define write_c0_index(val)     __write_32bit_c0_register($0, 0, val)
 
@@ -1004,9 +1038,15 @@ do {									\
 #define read_c0_entrylo0()      __read_ulong_c0_register($2, 0)
 #define write_c0_entrylo0(val)  __write_ulong_c0_register($2, 0, val)
 
+#define readx_c0_entrylo0()     __readx_32bit_c0_register(2)
+#define writex_c0_entrylo0(val) __writex_32bit_c0_register(2, val)
+
 #define read_c0_entrylo1()      __read_ulong_c0_register($3, 0)
 #define write_c0_entrylo1(val)  __write_ulong_c0_register($3, 0, val)
 
+#define readx_c0_entrylo1()     __readx_32bit_c0_register(3)
+#define writex_c0_entrylo1(val) __writex_32bit_c0_register(3, val)
+
 #define read_c0_conf()          __read_32bit_c0_register($3, 0)
 #define write_c0_conf(val)      __write_32bit_c0_register($3, 0, val)