clk: qcom: add read-only alpha pll post divider operations

Some of the divider settings are preconfigured and should not
be changed by the clock framework during frequency change. This
patch adds the read-only divider operation for QCOM alpha pll
post divider which is equivalent to generic divider operations in
'commit 79c6ab509558 ("clk: divider: add CLK_DIVIDER_READ_ONLY flag")'.

Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>

2 files changed, 26 insertions, 0 deletions

diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c
index 2de66b98e997..6d04cd96482a 100644
--- a/drivers/clk/qcom/clk-alpha-pll.c
+++ b/drivers/clk/qcom/clk-alpha-pll.c
@@ -787,6 +787,25 @@ clk_alpha_pll_postdiv_round_rate(struct clk_hw *hw, unsigned long rate,
                                   pll->width, CLK_DIVIDER_POWER_OF_TWO);
 }
 
+static long
+clk_alpha_pll_postdiv_round_ro_rate(struct clk_hw *hw, unsigned long rate,
+                                    unsigned long *prate)
+{
+        struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
+        u32 ctl, div;
+
+        regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl);
+
+        ctl >>= PLL_POST_DIV_SHIFT;
+        ctl &= BIT(pll->width) - 1;
+        div = 1 << fls(ctl);
+
+        if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT)
+                *prate = clk_hw_round_rate(clk_hw_get_parent(hw), div * rate);
+
+        return DIV_ROUND_UP_ULL((u64)*prate, div);
+}
+
 static int clk_alpha_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate,
                                           unsigned long parent_rate)
 {
@@ -807,3 +826,9 @@ const struct clk_ops clk_alpha_pll_postdiv_ops = {
         .set_rate = clk_alpha_pll_postdiv_set_rate,
 };
 EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_ops);
+
+const struct clk_ops clk_alpha_pll_postdiv_ro_ops = {
+        .round_rate = clk_alpha_pll_postdiv_round_ro_rate,
+        .recalc_rate = clk_alpha_pll_postdiv_recalc_rate,
+};
+EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_ro_ops);
diff --git a/drivers/clk/qcom/clk-alpha-pll.h b/drivers/clk/qcom/clk-alpha-pll.h
index bcc6676a8e7a..7593e8a56cf2 100644
--- a/drivers/clk/qcom/clk-alpha-pll.h
+++ b/drivers/clk/qcom/clk-alpha-pll.h
@@ -107,6 +107,7 @@ extern const struct clk_ops clk_alpha_pll_ops;
 extern const struct clk_ops clk_alpha_pll_hwfsm_ops;
 extern const struct clk_ops clk_alpha_pll_postdiv_ops;
 extern const struct clk_ops clk_alpha_pll_huayra_ops;
+extern const struct clk_ops clk_alpha_pll_postdiv_ro_ops;
 
 void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
                              const struct alpha_pll_config *config);