diff options
author | Anthony Koo <Anthony.Koo@amd.com> | 2017-11-24 15:43:05 -0500 |
---|---|---|
committer | Alex Deucher <alexander.deucher@amd.com> | 2017-12-20 14:46:32 -0500 |
commit | 23bfb33181d2af0109672b5f25f542378e7a01b1 (patch) | |
tree | ad02d5c778cf91a9a408c7299e0ff2921463c1a7 | |
parent | 38cb3e96e0c4362194aab662b424e89da8755561 (diff) |
drm/amd/display: Fix check for whether dmcu fw is running
Signed-off-by: Anthony Koo <Anthony.Koo@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-rw-r--r-- | drivers/gpu/drm/amd/display/dc/core/dc_link.c | 11 | ||||
-rw-r--r-- | drivers/gpu/drm/amd/display/dc/dce/dce_abm.c | 18 | ||||
-rw-r--r-- | drivers/gpu/drm/amd/display/dc/dce/dce_abm.h | 8 | ||||
-rw-r--r-- | drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c | 4 | ||||
-rw-r--r-- | drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c | 34 | ||||
-rw-r--r-- | drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h | 3 | ||||
-rw-r--r-- | drivers/gpu/drm/amd/display/dc/inc/hw/abm.h | 4 | ||||
-rw-r--r-- | drivers/gpu/drm/amd/display/dc/inc/hw/dmcu.h | 1 |
8 files changed, 54 insertions, 29 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c index da83412af306..a37428271573 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c | |||
@@ -1930,12 +1930,18 @@ bool dc_link_set_backlight_level(const struct dc_link *link, uint32_t level, | |||
1930 | { | 1930 | { |
1931 | struct dc *core_dc = link->ctx->dc; | 1931 | struct dc *core_dc = link->ctx->dc; |
1932 | struct abm *abm = core_dc->res_pool->abm; | 1932 | struct abm *abm = core_dc->res_pool->abm; |
1933 | struct dmcu *dmcu = core_dc->res_pool->dmcu; | ||
1933 | unsigned int controller_id = 0; | 1934 | unsigned int controller_id = 0; |
1935 | bool use_smooth_brightness = true; | ||
1934 | int i; | 1936 | int i; |
1935 | 1937 | ||
1936 | if ((abm == NULL) || (abm->funcs->set_backlight_level == NULL)) | 1938 | if ((dmcu == NULL) || |
1939 | (abm == NULL) || | ||
1940 | (abm->funcs->set_backlight_level == NULL)) | ||
1937 | return false; | 1941 | return false; |
1938 | 1942 | ||
1943 | use_smooth_brightness = dmcu->funcs->is_dmcu_initialized(dmcu); | ||
1944 | |||
1939 | dm_logger_write(link->ctx->logger, LOG_BACKLIGHT, | 1945 | dm_logger_write(link->ctx->logger, LOG_BACKLIGHT, |
1940 | "New Backlight level: %d (0x%X)\n", level, level); | 1946 | "New Backlight level: %d (0x%X)\n", level, level); |
1941 | 1947 | ||
@@ -1958,7 +1964,8 @@ bool dc_link_set_backlight_level(const struct dc_link *link, uint32_t level, | |||
1958 | abm, | 1964 | abm, |
1959 | level, | 1965 | level, |
1960 | frame_ramp, | 1966 | frame_ramp, |
1961 | controller_id); | 1967 | controller_id, |
1968 | use_smooth_brightness); | ||
1962 | } | 1969 | } |
1963 | 1970 | ||
1964 | return true; | 1971 | return true; |
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_abm.c b/drivers/gpu/drm/amd/display/dc/dce/dce_abm.c index 3fe8e697483f..b48190f54907 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_abm.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_abm.c | |||
@@ -385,21 +385,12 @@ static bool dce_abm_init_backlight(struct abm *abm) | |||
385 | return true; | 385 | return true; |
386 | } | 386 | } |
387 | 387 | ||
388 | static bool is_dmcu_initialized(struct abm *abm) | ||
389 | { | ||
390 | struct dce_abm *abm_dce = TO_DCE_ABM(abm); | ||
391 | unsigned int dmcu_uc_reset; | ||
392 | |||
393 | REG_GET(DMCU_STATUS, UC_IN_RESET, &dmcu_uc_reset); | ||
394 | |||
395 | return !dmcu_uc_reset; | ||
396 | } | ||
397 | |||
398 | static bool dce_abm_set_backlight_level( | 388 | static bool dce_abm_set_backlight_level( |
399 | struct abm *abm, | 389 | struct abm *abm, |
400 | unsigned int backlight_level, | 390 | unsigned int backlight_level, |
401 | unsigned int frame_ramp, | 391 | unsigned int frame_ramp, |
402 | unsigned int controller_id) | 392 | unsigned int controller_id, |
393 | bool use_smooth_brightness) | ||
403 | { | 394 | { |
404 | struct dce_abm *abm_dce = TO_DCE_ABM(abm); | 395 | struct dce_abm *abm_dce = TO_DCE_ABM(abm); |
405 | 396 | ||
@@ -408,7 +399,7 @@ static bool dce_abm_set_backlight_level( | |||
408 | backlight_level, backlight_level); | 399 | backlight_level, backlight_level); |
409 | 400 | ||
410 | /* If DMCU is in reset state, DMCU is uninitialized */ | 401 | /* If DMCU is in reset state, DMCU is uninitialized */ |
411 | if (is_dmcu_initialized(abm)) | 402 | if (use_smooth_brightness) |
412 | dmcu_set_backlight_level(abm_dce, | 403 | dmcu_set_backlight_level(abm_dce, |
413 | backlight_level, | 404 | backlight_level, |
414 | frame_ramp, | 405 | frame_ramp, |
@@ -425,8 +416,7 @@ static const struct abm_funcs dce_funcs = { | |||
425 | .init_backlight = dce_abm_init_backlight, | 416 | .init_backlight = dce_abm_init_backlight, |
426 | .set_backlight_level = dce_abm_set_backlight_level, | 417 | .set_backlight_level = dce_abm_set_backlight_level, |
427 | .get_current_backlight_8_bit = dce_abm_get_current_backlight_8_bit, | 418 | .get_current_backlight_8_bit = dce_abm_get_current_backlight_8_bit, |
428 | .set_abm_immediate_disable = dce_abm_immediate_disable, | 419 | .set_abm_immediate_disable = dce_abm_immediate_disable |
429 | .is_dmcu_initialized = is_dmcu_initialized | ||
430 | }; | 420 | }; |
431 | 421 | ||
432 | static void dce_abm_construct( | 422 | static void dce_abm_construct( |
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_abm.h b/drivers/gpu/drm/amd/display/dc/dce/dce_abm.h index 59e909ec88f2..ff9436966041 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_abm.h +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_abm.h | |||
@@ -37,8 +37,7 @@ | |||
37 | SR(LVTMA_PWRSEQ_REF_DIV), \ | 37 | SR(LVTMA_PWRSEQ_REF_DIV), \ |
38 | SR(MASTER_COMM_CNTL_REG), \ | 38 | SR(MASTER_COMM_CNTL_REG), \ |
39 | SR(MASTER_COMM_CMD_REG), \ | 39 | SR(MASTER_COMM_CMD_REG), \ |
40 | SR(MASTER_COMM_DATA_REG1), \ | 40 | SR(MASTER_COMM_DATA_REG1) |
41 | SR(DMCU_STATUS) | ||
42 | 41 | ||
43 | #define ABM_DCE110_COMMON_REG_LIST() \ | 42 | #define ABM_DCE110_COMMON_REG_LIST() \ |
44 | ABM_COMMON_REG_LIST_DCE_BASE(), \ | 43 | ABM_COMMON_REG_LIST_DCE_BASE(), \ |
@@ -84,8 +83,7 @@ | |||
84 | ABM_SF(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, mask_sh), \ | 83 | ABM_SF(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, mask_sh), \ |
85 | ABM_SF(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, mask_sh), \ | 84 | ABM_SF(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, mask_sh), \ |
86 | ABM_SF(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE1, mask_sh), \ | 85 | ABM_SF(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE1, mask_sh), \ |
87 | ABM_SF(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE2, mask_sh), \ | 86 | ABM_SF(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE2, mask_sh) |
88 | ABM_SF(DMCU_STATUS, UC_IN_RESET, mask_sh) | ||
89 | 87 | ||
90 | #define ABM_MASK_SH_LIST_DCE110(mask_sh) \ | 88 | #define ABM_MASK_SH_LIST_DCE110(mask_sh) \ |
91 | ABM_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh), \ | 89 | ABM_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh), \ |
@@ -174,7 +172,6 @@ | |||
174 | type MASTER_COMM_CMD_REG_BYTE2; \ | 172 | type MASTER_COMM_CMD_REG_BYTE2; \ |
175 | type BL_PWM_REF_DIV; \ | 173 | type BL_PWM_REF_DIV; \ |
176 | type BL_PWM_EN; \ | 174 | type BL_PWM_EN; \ |
177 | type UC_IN_RESET; \ | ||
178 | type BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN; \ | 175 | type BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN; \ |
179 | type BL_PWM_GRP1_REG_LOCK; \ | 176 | type BL_PWM_GRP1_REG_LOCK; \ |
180 | type BL_PWM_GRP1_REG_UPDATE_PENDING | 177 | type BL_PWM_GRP1_REG_UPDATE_PENDING |
@@ -206,7 +203,6 @@ struct dce_abm_registers { | |||
206 | uint32_t MASTER_COMM_CMD_REG; | 203 | uint32_t MASTER_COMM_CMD_REG; |
207 | uint32_t MASTER_COMM_DATA_REG1; | 204 | uint32_t MASTER_COMM_DATA_REG1; |
208 | uint32_t BIOS_SCRATCH_2; | 205 | uint32_t BIOS_SCRATCH_2; |
209 | uint32_t DMCU_STATUS; | ||
210 | uint32_t BL_PWM_GRP1_REG_LOCK; | 206 | uint32_t BL_PWM_GRP1_REG_LOCK; |
211 | }; | 207 | }; |
212 | 208 | ||
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c b/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c index 9031d22285ea..9e98a5f39a6d 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c | |||
@@ -29,7 +29,6 @@ | |||
29 | #include "fixed32_32.h" | 29 | #include "fixed32_32.h" |
30 | #include "bios_parser_interface.h" | 30 | #include "bios_parser_interface.h" |
31 | #include "dc.h" | 31 | #include "dc.h" |
32 | #include "dce_abm.h" | ||
33 | #include "dmcu.h" | 32 | #include "dmcu.h" |
34 | #if defined(CONFIG_DRM_AMD_DC_DCN1_0) | 33 | #if defined(CONFIG_DRM_AMD_DC_DCN1_0) |
35 | #include "dcn_calcs.h" | 34 | #include "dcn_calcs.h" |
@@ -384,7 +383,6 @@ static int dce112_set_clock( | |||
384 | struct bp_set_dce_clock_parameters dce_clk_params; | 383 | struct bp_set_dce_clock_parameters dce_clk_params; |
385 | struct dc_bios *bp = clk->ctx->dc_bios; | 384 | struct dc_bios *bp = clk->ctx->dc_bios; |
386 | struct dc *core_dc = clk->ctx->dc; | 385 | struct dc *core_dc = clk->ctx->dc; |
387 | struct abm *abm = core_dc->res_pool->abm; | ||
388 | struct dmcu *dmcu = core_dc->res_pool->dmcu; | 386 | struct dmcu *dmcu = core_dc->res_pool->dmcu; |
389 | int actual_clock = requested_clk_khz; | 387 | int actual_clock = requested_clk_khz; |
390 | /* Prepare to program display clock*/ | 388 | /* Prepare to program display clock*/ |
@@ -417,7 +415,7 @@ static int dce112_set_clock( | |||
417 | 415 | ||
418 | bp->funcs->set_dce_clock(bp, &dce_clk_params); | 416 | bp->funcs->set_dce_clock(bp, &dce_clk_params); |
419 | 417 | ||
420 | if (abm->funcs->is_dmcu_initialized(abm) && clk_dce->dfs_bypass_disp_clk != actual_clock) | 418 | if (clk_dce->dfs_bypass_disp_clk != actual_clock) |
421 | dmcu->funcs->set_psr_wait_loop(dmcu, | 419 | dmcu->funcs->set_psr_wait_loop(dmcu, |
422 | actual_clock / 1000 / 7); | 420 | actual_clock / 1000 / 7); |
423 | clk_dce->dfs_bypass_disp_clk = actual_clock; | 421 | clk_dce->dfs_bypass_disp_clk = actual_clock; |
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c b/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c index a6de99db0444..f663adb33584 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c | |||
@@ -263,15 +263,35 @@ static void dce_dmcu_setup_psr(struct dmcu *dmcu, | |||
263 | REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); | 263 | REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); |
264 | } | 264 | } |
265 | 265 | ||
266 | static bool dce_is_dmcu_initialized(struct dmcu *dmcu) | ||
267 | { | ||
268 | struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); | ||
269 | unsigned int dmcu_uc_reset; | ||
270 | |||
271 | /* microcontroller is not running */ | ||
272 | REG_GET(DMCU_STATUS, UC_IN_RESET, &dmcu_uc_reset); | ||
273 | |||
274 | /* DMCU is not running */ | ||
275 | if (dmcu_uc_reset) | ||
276 | return false; | ||
277 | |||
278 | return true; | ||
279 | } | ||
280 | |||
266 | static void dce_psr_wait_loop( | 281 | static void dce_psr_wait_loop( |
267 | struct dmcu *dmcu, | 282 | struct dmcu *dmcu, |
268 | unsigned int wait_loop_number) | 283 | unsigned int wait_loop_number) |
269 | { | 284 | { |
270 | struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); | 285 | struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); |
271 | union dce_dmcu_psr_config_data_wait_loop_reg1 masterCmdData1; | 286 | union dce_dmcu_psr_config_data_wait_loop_reg1 masterCmdData1; |
287 | |||
272 | if (dmcu->cached_wait_loop_number == wait_loop_number) | 288 | if (dmcu->cached_wait_loop_number == wait_loop_number) |
273 | return; | 289 | return; |
274 | 290 | ||
291 | /* DMCU is not running */ | ||
292 | if (!dce_is_dmcu_initialized(dmcu)) | ||
293 | return; | ||
294 | |||
275 | /* waitDMCUReadyForCmd */ | 295 | /* waitDMCUReadyForCmd */ |
276 | REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 1, 10000); | 296 | REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 1, 10000); |
277 | 297 | ||
@@ -691,6 +711,14 @@ static void dcn10_get_psr_wait_loop( | |||
691 | return; | 711 | return; |
692 | } | 712 | } |
693 | 713 | ||
714 | static bool dcn10_is_dmcu_initialized(struct dmcu *dmcu) | ||
715 | { | ||
716 | /* microcontroller is not running */ | ||
717 | if (dmcu->dmcu_state != DMCU_RUNNING) | ||
718 | return false; | ||
719 | return true; | ||
720 | } | ||
721 | |||
694 | #endif | 722 | #endif |
695 | 723 | ||
696 | static const struct dmcu_funcs dce_funcs = { | 724 | static const struct dmcu_funcs dce_funcs = { |
@@ -700,7 +728,8 @@ static const struct dmcu_funcs dce_funcs = { | |||
700 | .setup_psr = dce_dmcu_setup_psr, | 728 | .setup_psr = dce_dmcu_setup_psr, |
701 | .get_psr_state = dce_get_dmcu_psr_state, | 729 | .get_psr_state = dce_get_dmcu_psr_state, |
702 | .set_psr_wait_loop = dce_psr_wait_loop, | 730 | .set_psr_wait_loop = dce_psr_wait_loop, |
703 | .get_psr_wait_loop = dce_get_psr_wait_loop | 731 | .get_psr_wait_loop = dce_get_psr_wait_loop, |
732 | .is_dmcu_initialized = dce_is_dmcu_initialized | ||
704 | }; | 733 | }; |
705 | 734 | ||
706 | #if defined(CONFIG_DRM_AMD_DC_DCN1_0) | 735 | #if defined(CONFIG_DRM_AMD_DC_DCN1_0) |
@@ -711,7 +740,8 @@ static const struct dmcu_funcs dcn10_funcs = { | |||
711 | .setup_psr = dcn10_dmcu_setup_psr, | 740 | .setup_psr = dcn10_dmcu_setup_psr, |
712 | .get_psr_state = dcn10_get_dmcu_psr_state, | 741 | .get_psr_state = dcn10_get_dmcu_psr_state, |
713 | .set_psr_wait_loop = dcn10_psr_wait_loop, | 742 | .set_psr_wait_loop = dcn10_psr_wait_loop, |
714 | .get_psr_wait_loop = dcn10_get_psr_wait_loop | 743 | .get_psr_wait_loop = dcn10_get_psr_wait_loop, |
744 | .is_dmcu_initialized = dcn10_is_dmcu_initialized | ||
715 | }; | 745 | }; |
716 | #endif | 746 | #endif |
717 | 747 | ||
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h b/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h index 4c25e2dd28f8..1d4546f23135 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h | |||
@@ -62,6 +62,8 @@ | |||
62 | DMCU_ENABLE, mask_sh), \ | 62 | DMCU_ENABLE, mask_sh), \ |
63 | DMCU_SF(DMCU_STATUS, \ | 63 | DMCU_SF(DMCU_STATUS, \ |
64 | UC_IN_STOP_MODE, mask_sh), \ | 64 | UC_IN_STOP_MODE, mask_sh), \ |
65 | DMCU_SF(DMCU_STATUS, \ | ||
66 | UC_IN_RESET, mask_sh), \ | ||
65 | DMCU_SF(DMCU_RAM_ACCESS_CTRL, \ | 67 | DMCU_SF(DMCU_RAM_ACCESS_CTRL, \ |
66 | IRAM_HOST_ACCESS_EN, mask_sh), \ | 68 | IRAM_HOST_ACCESS_EN, mask_sh), \ |
67 | DMCU_SF(DMCU_RAM_ACCESS_CTRL, \ | 69 | DMCU_SF(DMCU_RAM_ACCESS_CTRL, \ |
@@ -98,6 +100,7 @@ | |||
98 | type IRAM_RD_ADDR_AUTO_INC; \ | 100 | type IRAM_RD_ADDR_AUTO_INC; \ |
99 | type DMCU_ENABLE; \ | 101 | type DMCU_ENABLE; \ |
100 | type UC_IN_STOP_MODE; \ | 102 | type UC_IN_STOP_MODE; \ |
103 | type UC_IN_RESET; \ | ||
101 | type MASTER_COMM_CMD_REG_BYTE0; \ | 104 | type MASTER_COMM_CMD_REG_BYTE0; \ |
102 | type MASTER_COMM_INTERRUPT; \ | 105 | type MASTER_COMM_INTERRUPT; \ |
103 | type DPHY_RX_FAST_TRAINING_CAPABLE; \ | 106 | type DPHY_RX_FAST_TRAINING_CAPABLE; \ |
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/abm.h b/drivers/gpu/drm/amd/display/dc/inc/hw/abm.h index 48217ecfabd4..a83a48494613 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/abm.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/abm.h | |||
@@ -50,9 +50,9 @@ struct abm_funcs { | |||
50 | bool (*set_backlight_level)(struct abm *abm, | 50 | bool (*set_backlight_level)(struct abm *abm, |
51 | unsigned int backlight_level, | 51 | unsigned int backlight_level, |
52 | unsigned int frame_ramp, | 52 | unsigned int frame_ramp, |
53 | unsigned int controller_id); | 53 | unsigned int controller_id, |
54 | bool use_smooth_brightness); | ||
54 | unsigned int (*get_current_backlight_8_bit)(struct abm *abm); | 55 | unsigned int (*get_current_backlight_8_bit)(struct abm *abm); |
55 | bool (*is_dmcu_initialized)(struct abm *abm); | ||
56 | }; | 56 | }; |
57 | 57 | ||
58 | #endif | 58 | #endif |
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dmcu.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dmcu.h index b59712b41b81..ce206355461b 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/dmcu.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dmcu.h | |||
@@ -63,6 +63,7 @@ struct dmcu_funcs { | |||
63 | unsigned int wait_loop_number); | 63 | unsigned int wait_loop_number); |
64 | void (*get_psr_wait_loop)(struct dmcu *dmcu, | 64 | void (*get_psr_wait_loop)(struct dmcu *dmcu, |
65 | unsigned int *psr_wait_loop_number); | 65 | unsigned int *psr_wait_loop_number); |
66 | bool (*is_dmcu_initialized)(struct dmcu *dmcu); | ||
66 | }; | 67 | }; |
67 | 68 | ||
68 | #endif | 69 | #endif |