diff options
author | Guochun Mao <guochun.mao@mediatek.com> | 2017-12-17 20:47:35 -0500 |
---|---|---|
committer | Cyrille Pitchen <cyrille.pitchen@wedev4u.fr> | 2018-01-14 10:14:06 -0500 |
commit | 23bae78e8a57f0249ed9e3f9c3f40fc1499ce0d4 (patch) | |
tree | abd94206d769302b62395a15b39ea7858319584a | |
parent | a6e4836d6991b86736ed00835ffac94cc2ec5158 (diff) |
mtd: mtk-nor: modify functions' name more generally
Since more and more Mediatek's SoC can use this driver to
control spi-nor flash, functions' name with "mt8173_" is
no longer properly. Replacing "mt8173_" with "mtk_" will
be more accurate to describe these functions' usable scope.
Signed-off-by: Guochun Mao <guochun.mao@mediatek.com>
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@wedev4u.fr>
-rw-r--r-- | drivers/mtd/spi-nor/mtk-quadspi.c | 240 |
1 files changed, 120 insertions, 120 deletions
diff --git a/drivers/mtd/spi-nor/mtk-quadspi.c b/drivers/mtd/spi-nor/mtk-quadspi.c index abe455ccd68b..5442993b71ff 100644 --- a/drivers/mtd/spi-nor/mtk-quadspi.c +++ b/drivers/mtd/spi-nor/mtk-quadspi.c | |||
@@ -110,7 +110,7 @@ | |||
110 | #define MTK_NOR_PRG_REG(n) (MTK_NOR_PRGDATA0_REG + 4 * (n)) | 110 | #define MTK_NOR_PRG_REG(n) (MTK_NOR_PRGDATA0_REG + 4 * (n)) |
111 | #define MTK_NOR_SHREG(n) (MTK_NOR_SHREG0_REG + 4 * (n)) | 111 | #define MTK_NOR_SHREG(n) (MTK_NOR_SHREG0_REG + 4 * (n)) |
112 | 112 | ||
113 | struct mt8173_nor { | 113 | struct mtk_nor { |
114 | struct spi_nor nor; | 114 | struct spi_nor nor; |
115 | struct device *dev; | 115 | struct device *dev; |
116 | void __iomem *base; /* nor flash base address */ | 116 | void __iomem *base; /* nor flash base address */ |
@@ -118,48 +118,48 @@ struct mt8173_nor { | |||
118 | struct clk *nor_clk; | 118 | struct clk *nor_clk; |
119 | }; | 119 | }; |
120 | 120 | ||
121 | static void mt8173_nor_set_read_mode(struct mt8173_nor *mt8173_nor) | 121 | static void mtk_nor_set_read_mode(struct mtk_nor *mtk_nor) |
122 | { | 122 | { |
123 | struct spi_nor *nor = &mt8173_nor->nor; | 123 | struct spi_nor *nor = &mtk_nor->nor; |
124 | 124 | ||
125 | switch (nor->read_proto) { | 125 | switch (nor->read_proto) { |
126 | case SNOR_PROTO_1_1_1: | 126 | case SNOR_PROTO_1_1_1: |
127 | writeb(nor->read_opcode, mt8173_nor->base + | 127 | writeb(nor->read_opcode, mtk_nor->base + |
128 | MTK_NOR_PRGDATA3_REG); | 128 | MTK_NOR_PRGDATA3_REG); |
129 | writeb(MTK_NOR_FAST_READ, mt8173_nor->base + | 129 | writeb(MTK_NOR_FAST_READ, mtk_nor->base + |
130 | MTK_NOR_CFG1_REG); | 130 | MTK_NOR_CFG1_REG); |
131 | break; | 131 | break; |
132 | case SNOR_PROTO_1_1_2: | 132 | case SNOR_PROTO_1_1_2: |
133 | writeb(nor->read_opcode, mt8173_nor->base + | 133 | writeb(nor->read_opcode, mtk_nor->base + |
134 | MTK_NOR_PRGDATA3_REG); | 134 | MTK_NOR_PRGDATA3_REG); |
135 | writeb(MTK_NOR_DUAL_READ_EN, mt8173_nor->base + | 135 | writeb(MTK_NOR_DUAL_READ_EN, mtk_nor->base + |
136 | MTK_NOR_DUAL_REG); | 136 | MTK_NOR_DUAL_REG); |
137 | break; | 137 | break; |
138 | case SNOR_PROTO_1_1_4: | 138 | case SNOR_PROTO_1_1_4: |
139 | writeb(nor->read_opcode, mt8173_nor->base + | 139 | writeb(nor->read_opcode, mtk_nor->base + |
140 | MTK_NOR_PRGDATA4_REG); | 140 | MTK_NOR_PRGDATA4_REG); |
141 | writeb(MTK_NOR_QUAD_READ_EN, mt8173_nor->base + | 141 | writeb(MTK_NOR_QUAD_READ_EN, mtk_nor->base + |
142 | MTK_NOR_DUAL_REG); | 142 | MTK_NOR_DUAL_REG); |
143 | break; | 143 | break; |
144 | default: | 144 | default: |
145 | writeb(MTK_NOR_DUAL_DISABLE, mt8173_nor->base + | 145 | writeb(MTK_NOR_DUAL_DISABLE, mtk_nor->base + |
146 | MTK_NOR_DUAL_REG); | 146 | MTK_NOR_DUAL_REG); |
147 | break; | 147 | break; |
148 | } | 148 | } |
149 | } | 149 | } |
150 | 150 | ||
151 | static int mt8173_nor_execute_cmd(struct mt8173_nor *mt8173_nor, u8 cmdval) | 151 | static int mtk_nor_execute_cmd(struct mtk_nor *mtk_nor, u8 cmdval) |
152 | { | 152 | { |
153 | int reg; | 153 | int reg; |
154 | u8 val = cmdval & 0x1f; | 154 | u8 val = cmdval & 0x1f; |
155 | 155 | ||
156 | writeb(cmdval, mt8173_nor->base + MTK_NOR_CMD_REG); | 156 | writeb(cmdval, mtk_nor->base + MTK_NOR_CMD_REG); |
157 | return readl_poll_timeout(mt8173_nor->base + MTK_NOR_CMD_REG, reg, | 157 | return readl_poll_timeout(mtk_nor->base + MTK_NOR_CMD_REG, reg, |
158 | !(reg & val), 100, 10000); | 158 | !(reg & val), 100, 10000); |
159 | } | 159 | } |
160 | 160 | ||
161 | static int mt8173_nor_do_tx_rx(struct mt8173_nor *mt8173_nor, u8 op, | 161 | static int mtk_nor_do_tx_rx(struct mtk_nor *mtk_nor, u8 op, |
162 | u8 *tx, int txlen, u8 *rx, int rxlen) | 162 | u8 *tx, int txlen, u8 *rx, int rxlen) |
163 | { | 163 | { |
164 | int len = 1 + txlen + rxlen; | 164 | int len = 1 + txlen + rxlen; |
165 | int i, ret, idx; | 165 | int i, ret, idx; |
@@ -167,26 +167,26 @@ static int mt8173_nor_do_tx_rx(struct mt8173_nor *mt8173_nor, u8 op, | |||
167 | if (len > MTK_NOR_MAX_SHIFT) | 167 | if (len > MTK_NOR_MAX_SHIFT) |
168 | return -EINVAL; | 168 | return -EINVAL; |
169 | 169 | ||
170 | writeb(len * 8, mt8173_nor->base + MTK_NOR_CNT_REG); | 170 | writeb(len * 8, mtk_nor->base + MTK_NOR_CNT_REG); |
171 | 171 | ||
172 | /* start at PRGDATA5, go down to PRGDATA0 */ | 172 | /* start at PRGDATA5, go down to PRGDATA0 */ |
173 | idx = MTK_NOR_MAX_RX_TX_SHIFT - 1; | 173 | idx = MTK_NOR_MAX_RX_TX_SHIFT - 1; |
174 | 174 | ||
175 | /* opcode */ | 175 | /* opcode */ |
176 | writeb(op, mt8173_nor->base + MTK_NOR_PRG_REG(idx)); | 176 | writeb(op, mtk_nor->base + MTK_NOR_PRG_REG(idx)); |
177 | idx--; | 177 | idx--; |
178 | 178 | ||
179 | /* program TX data */ | 179 | /* program TX data */ |
180 | for (i = 0; i < txlen; i++, idx--) | 180 | for (i = 0; i < txlen; i++, idx--) |
181 | writeb(tx[i], mt8173_nor->base + MTK_NOR_PRG_REG(idx)); | 181 | writeb(tx[i], mtk_nor->base + MTK_NOR_PRG_REG(idx)); |
182 | 182 | ||
183 | /* clear out rest of TX registers */ | 183 | /* clear out rest of TX registers */ |
184 | while (idx >= 0) { | 184 | while (idx >= 0) { |
185 | writeb(0, mt8173_nor->base + MTK_NOR_PRG_REG(idx)); | 185 | writeb(0, mtk_nor->base + MTK_NOR_PRG_REG(idx)); |
186 | idx--; | 186 | idx--; |
187 | } | 187 | } |
188 | 188 | ||
189 | ret = mt8173_nor_execute_cmd(mt8173_nor, MTK_NOR_PRG_CMD); | 189 | ret = mtk_nor_execute_cmd(mtk_nor, MTK_NOR_PRG_CMD); |
190 | if (ret) | 190 | if (ret) |
191 | return ret; | 191 | return ret; |
192 | 192 | ||
@@ -195,20 +195,20 @@ static int mt8173_nor_do_tx_rx(struct mt8173_nor *mt8173_nor, u8 op, | |||
195 | 195 | ||
196 | /* read out RX data */ | 196 | /* read out RX data */ |
197 | for (i = 0; i < rxlen; i++, idx--) | 197 | for (i = 0; i < rxlen; i++, idx--) |
198 | rx[i] = readb(mt8173_nor->base + MTK_NOR_SHREG(idx)); | 198 | rx[i] = readb(mtk_nor->base + MTK_NOR_SHREG(idx)); |
199 | 199 | ||
200 | return 0; | 200 | return 0; |
201 | } | 201 | } |
202 | 202 | ||
203 | /* Do a WRSR (Write Status Register) command */ | 203 | /* Do a WRSR (Write Status Register) command */ |
204 | static int mt8173_nor_wr_sr(struct mt8173_nor *mt8173_nor, u8 sr) | 204 | static int mtk_nor_wr_sr(struct mtk_nor *mtk_nor, u8 sr) |
205 | { | 205 | { |
206 | writeb(sr, mt8173_nor->base + MTK_NOR_PRGDATA5_REG); | 206 | writeb(sr, mtk_nor->base + MTK_NOR_PRGDATA5_REG); |
207 | writeb(8, mt8173_nor->base + MTK_NOR_CNT_REG); | 207 | writeb(8, mtk_nor->base + MTK_NOR_CNT_REG); |
208 | return mt8173_nor_execute_cmd(mt8173_nor, MTK_NOR_WRSR_CMD); | 208 | return mtk_nor_execute_cmd(mtk_nor, MTK_NOR_WRSR_CMD); |
209 | } | 209 | } |
210 | 210 | ||
211 | static int mt8173_nor_write_buffer_enable(struct mt8173_nor *mt8173_nor) | 211 | static int mtk_nor_write_buffer_enable(struct mtk_nor *mtk_nor) |
212 | { | 212 | { |
213 | u8 reg; | 213 | u8 reg; |
214 | 214 | ||
@@ -216,27 +216,27 @@ static int mt8173_nor_write_buffer_enable(struct mt8173_nor *mt8173_nor) | |||
216 | * 0: pre-fetch buffer use for read | 216 | * 0: pre-fetch buffer use for read |
217 | * 1: pre-fetch buffer use for page program | 217 | * 1: pre-fetch buffer use for page program |
218 | */ | 218 | */ |
219 | writel(MTK_NOR_WR_BUF_ENABLE, mt8173_nor->base + MTK_NOR_CFG2_REG); | 219 | writel(MTK_NOR_WR_BUF_ENABLE, mtk_nor->base + MTK_NOR_CFG2_REG); |
220 | return readb_poll_timeout(mt8173_nor->base + MTK_NOR_CFG2_REG, reg, | 220 | return readb_poll_timeout(mtk_nor->base + MTK_NOR_CFG2_REG, reg, |
221 | 0x01 == (reg & 0x01), 100, 10000); | 221 | 0x01 == (reg & 0x01), 100, 10000); |
222 | } | 222 | } |
223 | 223 | ||
224 | static int mt8173_nor_write_buffer_disable(struct mt8173_nor *mt8173_nor) | 224 | static int mtk_nor_write_buffer_disable(struct mtk_nor *mtk_nor) |
225 | { | 225 | { |
226 | u8 reg; | 226 | u8 reg; |
227 | 227 | ||
228 | writel(MTK_NOR_WR_BUF_DISABLE, mt8173_nor->base + MTK_NOR_CFG2_REG); | 228 | writel(MTK_NOR_WR_BUF_DISABLE, mtk_nor->base + MTK_NOR_CFG2_REG); |
229 | return readb_poll_timeout(mt8173_nor->base + MTK_NOR_CFG2_REG, reg, | 229 | return readb_poll_timeout(mtk_nor->base + MTK_NOR_CFG2_REG, reg, |
230 | MTK_NOR_WR_BUF_DISABLE == (reg & 0x1), 100, | 230 | MTK_NOR_WR_BUF_DISABLE == (reg & 0x1), 100, |
231 | 10000); | 231 | 10000); |
232 | } | 232 | } |
233 | 233 | ||
234 | static void mt8173_nor_set_addr_width(struct mt8173_nor *mt8173_nor) | 234 | static void mtk_nor_set_addr_width(struct mtk_nor *mtk_nor) |
235 | { | 235 | { |
236 | u8 val; | 236 | u8 val; |
237 | struct spi_nor *nor = &mt8173_nor->nor; | 237 | struct spi_nor *nor = &mtk_nor->nor; |
238 | 238 | ||
239 | val = readb(mt8173_nor->base + MTK_NOR_DUAL_REG); | 239 | val = readb(mtk_nor->base + MTK_NOR_DUAL_REG); |
240 | 240 | ||
241 | switch (nor->addr_width) { | 241 | switch (nor->addr_width) { |
242 | case 3: | 242 | case 3: |
@@ -246,115 +246,115 @@ static void mt8173_nor_set_addr_width(struct mt8173_nor *mt8173_nor) | |||
246 | val |= MTK_NOR_4B_ADDR_EN; | 246 | val |= MTK_NOR_4B_ADDR_EN; |
247 | break; | 247 | break; |
248 | default: | 248 | default: |
249 | dev_warn(mt8173_nor->dev, "Unexpected address width %u.\n", | 249 | dev_warn(mtk_nor->dev, "Unexpected address width %u.\n", |
250 | nor->addr_width); | 250 | nor->addr_width); |
251 | break; | 251 | break; |
252 | } | 252 | } |
253 | 253 | ||
254 | writeb(val, mt8173_nor->base + MTK_NOR_DUAL_REG); | 254 | writeb(val, mtk_nor->base + MTK_NOR_DUAL_REG); |
255 | } | 255 | } |
256 | 256 | ||
257 | static void mt8173_nor_set_addr(struct mt8173_nor *mt8173_nor, u32 addr) | 257 | static void mtk_nor_set_addr(struct mtk_nor *mtk_nor, u32 addr) |
258 | { | 258 | { |
259 | int i; | 259 | int i; |
260 | 260 | ||
261 | mt8173_nor_set_addr_width(mt8173_nor); | 261 | mtk_nor_set_addr_width(mtk_nor); |
262 | 262 | ||
263 | for (i = 0; i < 3; i++) { | 263 | for (i = 0; i < 3; i++) { |
264 | writeb(addr & 0xff, mt8173_nor->base + MTK_NOR_RADR0_REG + i * 4); | 264 | writeb(addr & 0xff, mtk_nor->base + MTK_NOR_RADR0_REG + i * 4); |
265 | addr >>= 8; | 265 | addr >>= 8; |
266 | } | 266 | } |
267 | /* Last register is non-contiguous */ | 267 | /* Last register is non-contiguous */ |
268 | writeb(addr & 0xff, mt8173_nor->base + MTK_NOR_RADR3_REG); | 268 | writeb(addr & 0xff, mtk_nor->base + MTK_NOR_RADR3_REG); |
269 | } | 269 | } |
270 | 270 | ||
271 | static ssize_t mt8173_nor_read(struct spi_nor *nor, loff_t from, size_t length, | 271 | static ssize_t mtk_nor_read(struct spi_nor *nor, loff_t from, size_t length, |
272 | u_char *buffer) | 272 | u_char *buffer) |
273 | { | 273 | { |
274 | int i, ret; | 274 | int i, ret; |
275 | int addr = (int)from; | 275 | int addr = (int)from; |
276 | u8 *buf = (u8 *)buffer; | 276 | u8 *buf = (u8 *)buffer; |
277 | struct mt8173_nor *mt8173_nor = nor->priv; | 277 | struct mtk_nor *mtk_nor = nor->priv; |
278 | 278 | ||
279 | /* set mode for fast read mode ,dual mode or quad mode */ | 279 | /* set mode for fast read mode ,dual mode or quad mode */ |
280 | mt8173_nor_set_read_mode(mt8173_nor); | 280 | mtk_nor_set_read_mode(mtk_nor); |
281 | mt8173_nor_set_addr(mt8173_nor, addr); | 281 | mtk_nor_set_addr(mtk_nor, addr); |
282 | 282 | ||
283 | for (i = 0; i < length; i++) { | 283 | for (i = 0; i < length; i++) { |
284 | ret = mt8173_nor_execute_cmd(mt8173_nor, MTK_NOR_PIO_READ_CMD); | 284 | ret = mtk_nor_execute_cmd(mtk_nor, MTK_NOR_PIO_READ_CMD); |
285 | if (ret < 0) | 285 | if (ret < 0) |
286 | return ret; | 286 | return ret; |
287 | buf[i] = readb(mt8173_nor->base + MTK_NOR_RDATA_REG); | 287 | buf[i] = readb(mtk_nor->base + MTK_NOR_RDATA_REG); |
288 | } | 288 | } |
289 | return length; | 289 | return length; |
290 | } | 290 | } |
291 | 291 | ||
292 | static int mt8173_nor_write_single_byte(struct mt8173_nor *mt8173_nor, | 292 | static int mtk_nor_write_single_byte(struct mtk_nor *mtk_nor, |
293 | int addr, int length, u8 *data) | 293 | int addr, int length, u8 *data) |
294 | { | 294 | { |
295 | int i, ret; | 295 | int i, ret; |
296 | 296 | ||
297 | mt8173_nor_set_addr(mt8173_nor, addr); | 297 | mtk_nor_set_addr(mtk_nor, addr); |
298 | 298 | ||
299 | for (i = 0; i < length; i++) { | 299 | for (i = 0; i < length; i++) { |
300 | writeb(*data++, mt8173_nor->base + MTK_NOR_WDATA_REG); | 300 | writeb(*data++, mtk_nor->base + MTK_NOR_WDATA_REG); |
301 | ret = mt8173_nor_execute_cmd(mt8173_nor, MTK_NOR_PIO_WR_CMD); | 301 | ret = mtk_nor_execute_cmd(mtk_nor, MTK_NOR_PIO_WR_CMD); |
302 | if (ret < 0) | 302 | if (ret < 0) |
303 | return ret; | 303 | return ret; |
304 | } | 304 | } |
305 | return 0; | 305 | return 0; |
306 | } | 306 | } |
307 | 307 | ||
308 | static int mt8173_nor_write_buffer(struct mt8173_nor *mt8173_nor, int addr, | 308 | static int mtk_nor_write_buffer(struct mtk_nor *mtk_nor, int addr, |
309 | const u8 *buf) | 309 | const u8 *buf) |
310 | { | 310 | { |
311 | int i, bufidx, data; | 311 | int i, bufidx, data; |
312 | 312 | ||
313 | mt8173_nor_set_addr(mt8173_nor, addr); | 313 | mtk_nor_set_addr(mtk_nor, addr); |
314 | 314 | ||
315 | bufidx = 0; | 315 | bufidx = 0; |
316 | for (i = 0; i < SFLASH_WRBUF_SIZE; i += 4) { | 316 | for (i = 0; i < SFLASH_WRBUF_SIZE; i += 4) { |
317 | data = buf[bufidx + 3]<<24 | buf[bufidx + 2]<<16 | | 317 | data = buf[bufidx + 3]<<24 | buf[bufidx + 2]<<16 | |
318 | buf[bufidx + 1]<<8 | buf[bufidx]; | 318 | buf[bufidx + 1]<<8 | buf[bufidx]; |
319 | bufidx += 4; | 319 | bufidx += 4; |
320 | writel(data, mt8173_nor->base + MTK_NOR_PP_DATA_REG); | 320 | writel(data, mtk_nor->base + MTK_NOR_PP_DATA_REG); |
321 | } | 321 | } |
322 | return mt8173_nor_execute_cmd(mt8173_nor, MTK_NOR_WR_CMD); | 322 | return mtk_nor_execute_cmd(mtk_nor, MTK_NOR_WR_CMD); |
323 | } | 323 | } |
324 | 324 | ||
325 | static ssize_t mt8173_nor_write(struct spi_nor *nor, loff_t to, size_t len, | 325 | static ssize_t mtk_nor_write(struct spi_nor *nor, loff_t to, size_t len, |
326 | const u_char *buf) | 326 | const u_char *buf) |
327 | { | 327 | { |
328 | int ret; | 328 | int ret; |
329 | struct mt8173_nor *mt8173_nor = nor->priv; | 329 | struct mtk_nor *mtk_nor = nor->priv; |
330 | size_t i; | 330 | size_t i; |
331 | 331 | ||
332 | ret = mt8173_nor_write_buffer_enable(mt8173_nor); | 332 | ret = mtk_nor_write_buffer_enable(mtk_nor); |
333 | if (ret < 0) { | 333 | if (ret < 0) { |
334 | dev_warn(mt8173_nor->dev, "write buffer enable failed!\n"); | 334 | dev_warn(mtk_nor->dev, "write buffer enable failed!\n"); |
335 | return ret; | 335 | return ret; |
336 | } | 336 | } |
337 | 337 | ||
338 | for (i = 0; i + SFLASH_WRBUF_SIZE <= len; i += SFLASH_WRBUF_SIZE) { | 338 | for (i = 0; i + SFLASH_WRBUF_SIZE <= len; i += SFLASH_WRBUF_SIZE) { |
339 | ret = mt8173_nor_write_buffer(mt8173_nor, to, buf); | 339 | ret = mtk_nor_write_buffer(mtk_nor, to, buf); |
340 | if (ret < 0) { | 340 | if (ret < 0) { |
341 | dev_err(mt8173_nor->dev, "write buffer failed!\n"); | 341 | dev_err(mtk_nor->dev, "write buffer failed!\n"); |
342 | return ret; | 342 | return ret; |
343 | } | 343 | } |
344 | to += SFLASH_WRBUF_SIZE; | 344 | to += SFLASH_WRBUF_SIZE; |
345 | buf += SFLASH_WRBUF_SIZE; | 345 | buf += SFLASH_WRBUF_SIZE; |
346 | } | 346 | } |
347 | ret = mt8173_nor_write_buffer_disable(mt8173_nor); | 347 | ret = mtk_nor_write_buffer_disable(mtk_nor); |
348 | if (ret < 0) { | 348 | if (ret < 0) { |
349 | dev_warn(mt8173_nor->dev, "write buffer disable failed!\n"); | 349 | dev_warn(mtk_nor->dev, "write buffer disable failed!\n"); |
350 | return ret; | 350 | return ret; |
351 | } | 351 | } |
352 | 352 | ||
353 | if (i < len) { | 353 | if (i < len) { |
354 | ret = mt8173_nor_write_single_byte(mt8173_nor, to, | 354 | ret = mtk_nor_write_single_byte(mtk_nor, to, |
355 | (int)(len - i), (u8 *)buf); | 355 | (int)(len - i), (u8 *)buf); |
356 | if (ret < 0) { | 356 | if (ret < 0) { |
357 | dev_err(mt8173_nor->dev, "write single byte failed!\n"); | 357 | dev_err(mtk_nor->dev, "write single byte failed!\n"); |
358 | return ret; | 358 | return ret; |
359 | } | 359 | } |
360 | } | 360 | } |
@@ -362,72 +362,72 @@ static ssize_t mt8173_nor_write(struct spi_nor *nor, loff_t to, size_t len, | |||
362 | return len; | 362 | return len; |
363 | } | 363 | } |
364 | 364 | ||
365 | static int mt8173_nor_read_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len) | 365 | static int mtk_nor_read_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len) |
366 | { | 366 | { |
367 | int ret; | 367 | int ret; |
368 | struct mt8173_nor *mt8173_nor = nor->priv; | 368 | struct mtk_nor *mtk_nor = nor->priv; |
369 | 369 | ||
370 | switch (opcode) { | 370 | switch (opcode) { |
371 | case SPINOR_OP_RDSR: | 371 | case SPINOR_OP_RDSR: |
372 | ret = mt8173_nor_execute_cmd(mt8173_nor, MTK_NOR_RDSR_CMD); | 372 | ret = mtk_nor_execute_cmd(mtk_nor, MTK_NOR_RDSR_CMD); |
373 | if (ret < 0) | 373 | if (ret < 0) |
374 | return ret; | 374 | return ret; |
375 | if (len == 1) | 375 | if (len == 1) |
376 | *buf = readb(mt8173_nor->base + MTK_NOR_RDSR_REG); | 376 | *buf = readb(mtk_nor->base + MTK_NOR_RDSR_REG); |
377 | else | 377 | else |
378 | dev_err(mt8173_nor->dev, "len should be 1 for read status!\n"); | 378 | dev_err(mtk_nor->dev, "len should be 1 for read status!\n"); |
379 | break; | 379 | break; |
380 | default: | 380 | default: |
381 | ret = mt8173_nor_do_tx_rx(mt8173_nor, opcode, NULL, 0, buf, len); | 381 | ret = mtk_nor_do_tx_rx(mtk_nor, opcode, NULL, 0, buf, len); |
382 | break; | 382 | break; |
383 | } | 383 | } |
384 | return ret; | 384 | return ret; |
385 | } | 385 | } |
386 | 386 | ||
387 | static int mt8173_nor_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, | 387 | static int mtk_nor_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, |
388 | int len) | 388 | int len) |
389 | { | 389 | { |
390 | int ret; | 390 | int ret; |
391 | struct mt8173_nor *mt8173_nor = nor->priv; | 391 | struct mtk_nor *mtk_nor = nor->priv; |
392 | 392 | ||
393 | switch (opcode) { | 393 | switch (opcode) { |
394 | case SPINOR_OP_WRSR: | 394 | case SPINOR_OP_WRSR: |
395 | /* We only handle 1 byte */ | 395 | /* We only handle 1 byte */ |
396 | ret = mt8173_nor_wr_sr(mt8173_nor, *buf); | 396 | ret = mtk_nor_wr_sr(mtk_nor, *buf); |
397 | break; | 397 | break; |
398 | default: | 398 | default: |
399 | ret = mt8173_nor_do_tx_rx(mt8173_nor, opcode, buf, len, NULL, 0); | 399 | ret = mtk_nor_do_tx_rx(mtk_nor, opcode, buf, len, NULL, 0); |
400 | if (ret) | 400 | if (ret) |
401 | dev_warn(mt8173_nor->dev, "write reg failure!\n"); | 401 | dev_warn(mtk_nor->dev, "write reg failure!\n"); |
402 | break; | 402 | break; |
403 | } | 403 | } |
404 | return ret; | 404 | return ret; |
405 | } | 405 | } |
406 | 406 | ||
407 | static void mt8173_nor_disable_clk(struct mt8173_nor *mt8173_nor) | 407 | static void mtk_nor_disable_clk(struct mtk_nor *mtk_nor) |
408 | { | 408 | { |
409 | clk_disable_unprepare(mt8173_nor->spi_clk); | 409 | clk_disable_unprepare(mtk_nor->spi_clk); |
410 | clk_disable_unprepare(mt8173_nor->nor_clk); | 410 | clk_disable_unprepare(mtk_nor->nor_clk); |
411 | } | 411 | } |
412 | 412 | ||
413 | static int mt8173_nor_enable_clk(struct mt8173_nor *mt8173_nor) | 413 | static int mtk_nor_enable_clk(struct mtk_nor *mtk_nor) |
414 | { | 414 | { |
415 | int ret; | 415 | int ret; |
416 | 416 | ||
417 | ret = clk_prepare_enable(mt8173_nor->spi_clk); | 417 | ret = clk_prepare_enable(mtk_nor->spi_clk); |
418 | if (ret) | 418 | if (ret) |
419 | return ret; | 419 | return ret; |
420 | 420 | ||
421 | ret = clk_prepare_enable(mt8173_nor->nor_clk); | 421 | ret = clk_prepare_enable(mtk_nor->nor_clk); |
422 | if (ret) { | 422 | if (ret) { |
423 | clk_disable_unprepare(mt8173_nor->spi_clk); | 423 | clk_disable_unprepare(mtk_nor->spi_clk); |
424 | return ret; | 424 | return ret; |
425 | } | 425 | } |
426 | 426 | ||
427 | return 0; | 427 | return 0; |
428 | } | 428 | } |
429 | 429 | ||
430 | static int mtk_nor_init(struct mt8173_nor *mt8173_nor, | 430 | static int mtk_nor_init(struct mtk_nor *mtk_nor, |
431 | struct device_node *flash_node) | 431 | struct device_node *flash_node) |
432 | { | 432 | { |
433 | const struct spi_nor_hwcaps hwcaps = { | 433 | const struct spi_nor_hwcaps hwcaps = { |
@@ -439,18 +439,18 @@ static int mtk_nor_init(struct mt8173_nor *mt8173_nor, | |||
439 | struct spi_nor *nor; | 439 | struct spi_nor *nor; |
440 | 440 | ||
441 | /* initialize controller to accept commands */ | 441 | /* initialize controller to accept commands */ |
442 | writel(MTK_NOR_ENABLE_SF_CMD, mt8173_nor->base + MTK_NOR_WRPROT_REG); | 442 | writel(MTK_NOR_ENABLE_SF_CMD, mtk_nor->base + MTK_NOR_WRPROT_REG); |
443 | 443 | ||
444 | nor = &mt8173_nor->nor; | 444 | nor = &mtk_nor->nor; |
445 | nor->dev = mt8173_nor->dev; | 445 | nor->dev = mtk_nor->dev; |
446 | nor->priv = mt8173_nor; | 446 | nor->priv = mtk_nor; |
447 | spi_nor_set_flash_node(nor, flash_node); | 447 | spi_nor_set_flash_node(nor, flash_node); |
448 | 448 | ||
449 | /* fill the hooks to spi nor */ | 449 | /* fill the hooks to spi nor */ |
450 | nor->read = mt8173_nor_read; | 450 | nor->read = mtk_nor_read; |
451 | nor->read_reg = mt8173_nor_read_reg; | 451 | nor->read_reg = mtk_nor_read_reg; |
452 | nor->write = mt8173_nor_write; | 452 | nor->write = mtk_nor_write; |
453 | nor->write_reg = mt8173_nor_write_reg; | 453 | nor->write_reg = mtk_nor_write_reg; |
454 | nor->mtd.name = "mtk_nor"; | 454 | nor->mtd.name = "mtk_nor"; |
455 | /* initialized with NULL */ | 455 | /* initialized with NULL */ |
456 | ret = spi_nor_scan(nor, NULL, &hwcaps); | 456 | ret = spi_nor_scan(nor, NULL, &hwcaps); |
@@ -465,34 +465,34 @@ static int mtk_nor_drv_probe(struct platform_device *pdev) | |||
465 | struct device_node *flash_np; | 465 | struct device_node *flash_np; |
466 | struct resource *res; | 466 | struct resource *res; |
467 | int ret; | 467 | int ret; |
468 | struct mt8173_nor *mt8173_nor; | 468 | struct mtk_nor *mtk_nor; |
469 | 469 | ||
470 | if (!pdev->dev.of_node) { | 470 | if (!pdev->dev.of_node) { |
471 | dev_err(&pdev->dev, "No DT found\n"); | 471 | dev_err(&pdev->dev, "No DT found\n"); |
472 | return -EINVAL; | 472 | return -EINVAL; |
473 | } | 473 | } |
474 | 474 | ||
475 | mt8173_nor = devm_kzalloc(&pdev->dev, sizeof(*mt8173_nor), GFP_KERNEL); | 475 | mtk_nor = devm_kzalloc(&pdev->dev, sizeof(*mtk_nor), GFP_KERNEL); |
476 | if (!mt8173_nor) | 476 | if (!mtk_nor) |
477 | return -ENOMEM; | 477 | return -ENOMEM; |
478 | platform_set_drvdata(pdev, mt8173_nor); | 478 | platform_set_drvdata(pdev, mtk_nor); |
479 | 479 | ||
480 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | 480 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
481 | mt8173_nor->base = devm_ioremap_resource(&pdev->dev, res); | 481 | mtk_nor->base = devm_ioremap_resource(&pdev->dev, res); |
482 | if (IS_ERR(mt8173_nor->base)) | 482 | if (IS_ERR(mtk_nor->base)) |
483 | return PTR_ERR(mt8173_nor->base); | 483 | return PTR_ERR(mtk_nor->base); |
484 | 484 | ||
485 | mt8173_nor->spi_clk = devm_clk_get(&pdev->dev, "spi"); | 485 | mtk_nor->spi_clk = devm_clk_get(&pdev->dev, "spi"); |
486 | if (IS_ERR(mt8173_nor->spi_clk)) | 486 | if (IS_ERR(mtk_nor->spi_clk)) |
487 | return PTR_ERR(mt8173_nor->spi_clk); | 487 | return PTR_ERR(mtk_nor->spi_clk); |
488 | 488 | ||
489 | mt8173_nor->nor_clk = devm_clk_get(&pdev->dev, "sf"); | 489 | mtk_nor->nor_clk = devm_clk_get(&pdev->dev, "sf"); |
490 | if (IS_ERR(mt8173_nor->nor_clk)) | 490 | if (IS_ERR(mtk_nor->nor_clk)) |
491 | return PTR_ERR(mt8173_nor->nor_clk); | 491 | return PTR_ERR(mtk_nor->nor_clk); |
492 | 492 | ||
493 | mt8173_nor->dev = &pdev->dev; | 493 | mtk_nor->dev = &pdev->dev; |
494 | 494 | ||
495 | ret = mt8173_nor_enable_clk(mt8173_nor); | 495 | ret = mtk_nor_enable_clk(mtk_nor); |
496 | if (ret) | 496 | if (ret) |
497 | return ret; | 497 | return ret; |
498 | 498 | ||
@@ -503,20 +503,20 @@ static int mtk_nor_drv_probe(struct platform_device *pdev) | |||
503 | ret = -ENODEV; | 503 | ret = -ENODEV; |
504 | goto nor_free; | 504 | goto nor_free; |
505 | } | 505 | } |
506 | ret = mtk_nor_init(mt8173_nor, flash_np); | 506 | ret = mtk_nor_init(mtk_nor, flash_np); |
507 | 507 | ||
508 | nor_free: | 508 | nor_free: |
509 | if (ret) | 509 | if (ret) |
510 | mt8173_nor_disable_clk(mt8173_nor); | 510 | mtk_nor_disable_clk(mtk_nor); |
511 | 511 | ||
512 | return ret; | 512 | return ret; |
513 | } | 513 | } |
514 | 514 | ||
515 | static int mtk_nor_drv_remove(struct platform_device *pdev) | 515 | static int mtk_nor_drv_remove(struct platform_device *pdev) |
516 | { | 516 | { |
517 | struct mt8173_nor *mt8173_nor = platform_get_drvdata(pdev); | 517 | struct mtk_nor *mtk_nor = platform_get_drvdata(pdev); |
518 | 518 | ||
519 | mt8173_nor_disable_clk(mt8173_nor); | 519 | mtk_nor_disable_clk(mtk_nor); |
520 | 520 | ||
521 | return 0; | 521 | return 0; |
522 | } | 522 | } |
@@ -524,18 +524,18 @@ static int mtk_nor_drv_remove(struct platform_device *pdev) | |||
524 | #ifdef CONFIG_PM_SLEEP | 524 | #ifdef CONFIG_PM_SLEEP |
525 | static int mtk_nor_suspend(struct device *dev) | 525 | static int mtk_nor_suspend(struct device *dev) |
526 | { | 526 | { |
527 | struct mt8173_nor *mt8173_nor = dev_get_drvdata(dev); | 527 | struct mtk_nor *mtk_nor = dev_get_drvdata(dev); |
528 | 528 | ||
529 | mt8173_nor_disable_clk(mt8173_nor); | 529 | mtk_nor_disable_clk(mtk_nor); |
530 | 530 | ||
531 | return 0; | 531 | return 0; |
532 | } | 532 | } |
533 | 533 | ||
534 | static int mtk_nor_resume(struct device *dev) | 534 | static int mtk_nor_resume(struct device *dev) |
535 | { | 535 | { |
536 | struct mt8173_nor *mt8173_nor = dev_get_drvdata(dev); | 536 | struct mtk_nor *mtk_nor = dev_get_drvdata(dev); |
537 | 537 | ||
538 | return mt8173_nor_enable_clk(mt8173_nor); | 538 | return mtk_nor_enable_clk(mtk_nor); |
539 | } | 539 | } |
540 | 540 | ||
541 | static const struct dev_pm_ops mtk_nor_dev_pm_ops = { | 541 | static const struct dev_pm_ops mtk_nor_dev_pm_ops = { |