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authorBjorn Helgaas <bhelgaas@google.com>2015-06-12 18:27:43 -0400
committerBjorn Helgaas <bhelgaas@google.com>2015-06-16 09:18:19 -0400
commit2393f79cf92ed3bfaf1a6982a18bae4d289aeda8 (patch)
tree7fab4320777f6618437f0701aabdd4e5b8471330
parent1c7fae18a1fb6b6bcd6669066ee801769de0e943 (diff)
PCI: imx6: Add #define PCIE_RC_LCSR
Define PCIE_RC_LCSR and use it instead of the bare offset "0x80." No functional change. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
-rw-r--r--drivers/pci/host/pci-imx6.c4
1 files changed, 3 insertions, 1 deletions
diff --git a/drivers/pci/host/pci-imx6.c b/drivers/pci/host/pci-imx6.c
index 776789f0ebe0..a4ee579421df 100644
--- a/drivers/pci/host/pci-imx6.c
+++ b/drivers/pci/host/pci-imx6.c
@@ -47,6 +47,8 @@ struct imx6_pcie {
47#define PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN2 0x2 47#define PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN2 0x2
48#define PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK 0xf 48#define PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK 0xf
49 49
50#define PCIE_RC_LCSR 0x80
51
50/* PCIe Port Logic registers (memory-mapped) */ 52/* PCIe Port Logic registers (memory-mapped) */
51#define PL_OFFSET 0x700 53#define PL_OFFSET 0x700
52#define PCIE_PL_PFLR (PL_OFFSET + 0x08) 54#define PCIE_PL_PFLR (PL_OFFSET + 0x08)
@@ -427,7 +429,7 @@ static int imx6_pcie_start_link(struct pcie_port *pp)
427 return ret; 429 return ret;
428 } 430 }
429 431
430 tmp = readl(pp->dbi_base + 0x80); 432 tmp = readl(pp->dbi_base + PCIE_RC_LCSR);
431 dev_dbg(pp->dev, "Link up, Gen=%i\n", (tmp >> 16) & 0xf); 433 dev_dbg(pp->dev, "Link up, Gen=%i\n", (tmp >> 16) & 0xf);
432 return 0; 434 return 0;
433} 435}