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authorRodrigo Vivi <rodrigo.vivi@intel.com>2017-06-19 17:21:47 -0400
committerJani Nikula <jani.nikula@intel.com>2017-07-03 09:12:53 -0400
commit2347728934b501b07bea8b1b6e8fa27a56dc098f (patch)
treed7bec536850c4903ed6bac76dc73ba8069ce2e0a
parent4ec654bf3a63d503e3c5336eade5c369ae17db56 (diff)
drm/i915/cfl: Fix Workarounds.
During the review of Coffee Lake workarounds Mika pointed out that WaDisableKillLogic and GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC should be removed from CFL and with that I should carry the rv-b. However when doing the v2 I removed another Workaround that should remain because although not mentioned by spec the history of hangs around it advocates on its favor. On some follow-up patches I continued operating on the wrong workardound, but Ville noticed that, so here is the fix for the current CFL code that is upstream already. Fixes: 46c26662d2f ("drm/i915/cfl: Introduce Coffee Lake workarounds.") Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> Cc: Mika Kuoppala <mika.kuoppala@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> (cherry picked from commit 98eed3d1ade53596e1c8785e049f03da4480a820) Signed-off-by: Jani Nikula <jani.nikula@intel.com>
-rw-r--r--drivers/gpu/drm/i915/intel_engine_cs.c14
1 files changed, 7 insertions, 7 deletions
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
index a4487c5b7e37..5b4de719bec3 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -821,9 +821,10 @@ static int gen9_init_workarounds(struct intel_engine_cs *engine)
821 I915_WRITE(BDW_SCRATCH1, I915_READ(BDW_SCRATCH1) | 821 I915_WRITE(BDW_SCRATCH1, I915_READ(BDW_SCRATCH1) |
822 GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE); 822 GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE);
823 823
824 /* WaDisableKillLogic:bxt,skl,kbl,cfl */ 824 /* WaDisableKillLogic:bxt,skl,kbl */
825 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | 825 if (!IS_COFFEELAKE(dev_priv))
826 ECOCHK_DIS_TLB); 826 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
827 ECOCHK_DIS_TLB);
827 828
828 /* WaClearFlowControlGpgpuContextSave:skl,bxt,kbl,glk,cfl */ 829 /* WaClearFlowControlGpgpuContextSave:skl,bxt,kbl,glk,cfl */
829 /* WaDisablePartialInstShootdown:skl,bxt,kbl,glk,cfl */ 830 /* WaDisablePartialInstShootdown:skl,bxt,kbl,glk,cfl */
@@ -894,10 +895,9 @@ static int gen9_init_workarounds(struct intel_engine_cs *engine)
894 WA_SET_BIT_MASKED(HDC_CHICKEN0, 895 WA_SET_BIT_MASKED(HDC_CHICKEN0,
895 HDC_FORCE_NON_COHERENT); 896 HDC_FORCE_NON_COHERENT);
896 897
897 /* WaDisableHDCInvalidation:skl,bxt,kbl */ 898 /* WaDisableHDCInvalidation:skl,bxt,kbl,cfl */
898 if (!IS_COFFEELAKE(dev_priv)) 899 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
899 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | 900 BDW_DISABLE_HDC_INVALIDATION);
900 BDW_DISABLE_HDC_INVALIDATION);
901 901
902 /* WaDisableSamplerPowerBypassForSOPingPong:skl,bxt,kbl,cfl */ 902 /* WaDisableSamplerPowerBypassForSOPingPong:skl,bxt,kbl,cfl */
903 if (IS_SKYLAKE(dev_priv) || 903 if (IS_SKYLAKE(dev_priv) ||